`define s0

`define s1
`define s2
`timescale

2'd0
2'd1
2'd2
1ns/100ps

module compiler_d (clk,reset_n,coin,candy,return,state);

input clk;
input reset_n;
input [2:0]coin;
output candy;
output [3:0]return;
output [1:0]state;
reg candy;
reg [3:0]return;
reg [1:0]state;
always@(posedge clk)
if(reset_n==1)
begin
candy<=0;
return<=3'd0;
state<=`s0;
end
else
case(state)
`s0:
if(coin==3'd0)
begin
candy<=0;
state<=`s0;
return<=3'd0;
end
else if(coin==3'd1)
begin
candy<=0;
state<=`s1;
return<=3'd0;
end
else if(coin==3'd2)
begin
candy<=0;
state<=`s2;
return<=3'd0;
end
else if(coin==3'd5)
begin
candy<=1;
state<=`s0;
return<=3'd2;
end
else

;
`s1:
if(coin==3'd0)
begin
candy<=0;
state<=`s1;
return<=3'd0;
end
else if(coin==3'd1)
begin
candy<=0;
state<=`s2;
return<=3'd0;
end
else if(coin==3'd2)
begin
candy<=1;
state<=`s0;
return<=3'd0;
end
else if(coin==3'd5)
begin
candy<=1;
state<=`s0;
return<=3'd3;
end
else
;
`s2:
if(coin==3'd0)
begin
candy<=1;
state<=`s2;
return<=3'd0;
end
else if(coin==3'd1)
begin
candy<=1;
state<=`s0;
return<=3'd0;
end
else if(coin==3'd2)
begin
candy<=1;
state<=`s0;
return<=3'd1;
end
else if(coin==3'd5)
begin
candy<=1;

state<=`s0;
return<=3'd4;
end
else
;
endcase
endmodule