`include"compiler_d.

v"
`timescale 1ns/100ps
module compiler_d_tb;
reg clk;
reg reset_n;
reg [2:0]coin;
wire candy;
wire [3:0]return;
wire [1:0]state;
compiler_d a1 (clk,reset_n,coin,candy,return,state);
always
#10 clk=!clk;
initial
begin
clk=0;
reset_n=1;
coin=3'd0;
#10
reset_n=1;
coin=3'd1;
#20
reset_n=0;
coin=3'd2;
#20
reset_n=0;
coin=3'd1;
#20
reset_n=0;
coin=3'd1;
#20
reset_n=0;
coin=3'd1;
#20
reset_n=0;
coin=3'd1;
#20
reset_n=0;
coin=3'd5;
#20.35
reset_n=1;
coin=3'd1;
#20
reset_n=0;
coin=3'd5;
#20
reset_n=0;
coin=3'd2;

#20
reset_n=0;
coin=3'd5;
#20
$stop;
end
endmodule