`include "ff_d.

v"
`timescale 1ns/100ps
module ff_d_tb;
reg clk,reset_n,d;
wire q,q_n;
ff_d a1 (d,clk,q,reset_n,q_n);
initial
begin
clk=1'b0;
reset_n=1'b0;
d=1'b0;
end
always
#10 clk=~clk;
initial
begin
#20
reset_n=1'b1;
d=1'b1;
#20
reset_n=1'b1;
d=1'b0;
#20
reset_n=1'b0;
d=1'b1;
#20
$stop;
$finish;
end
endmodule