`include "ff_seq.

v"
`timescale 1ns/100ps

//including design fie.

//for time axis and resolution.

module ff_seq_tb;
reg s;
reg r;
reg d;
reg clk;
reg reset_n;
reg j;
reg k;
reg t;
wire
wire
wire
wire
wire
wire

//declaration of test module.

q_d;
q_s;
q_r;
q_j;
q_k;
q_t;

ff_seq a1

//declaration of output.

(d,
reset_n,
s,
r,
j,
k,
t,
clk,
q_d,
q_s,
q_r,
q_j,
q_k,
q_t);

always
#10 clk=~clk;
initial
begin
clk=1'b0;
reset_n=1'b0;
d=1'b0;
s=1'b1;
r=1'b0;
j=1'b1;
k=1'b0;
t=0;

// calling design module.

//list of all the input,output pins.

//clock of 50 mhz//

//initial input at t=0ns//

#10
reset_n=1'b1;
d=1'b1;
s=1'b1;
r=1'b0;
j=1;
k=0;

//input at 10 ns//

t=1;
#20

//input at 30 ns//
reset_n=1'b1;
d=1'b0;
s=1'b0;
r=1'b1;
j=0;
t=1;
k=1;

#20

// input at 50 ns//
reset_n=1'b1;
d=1'b1;
s=1'b0;
r=1'b0;
j=1;
k=1;
t=1;

#20

//input at 70 ns//
reset_n=1'b1;
d=1'b0;
s=1'b1;
r=1'b0;
j=0;
k=0;
t=1;

#20
$finish;
$stop;
end
endmodule

//hold value up to 90 ns//

//end simulation.
//stop testing.