LAB 4

MIPS PIPELINED CPU

I.Gii thiu i vi project ny bn phi thit k 1 CPU MIPS 32 bit vi pipelining .Cc lnh CPU thc hin trong bi lab ny l LW, SW, J, Jr, BNE, BNEZ, XOR, XORI, ADD, ADDI, SUB, and SLT (12 lnh) CPU pipelined ca chng ta s c 1 khe delay sau mi lnh load,branch,jump.N cng c nhim v covering vic forwarding d liu.Trong bi lab ny chng ta phi xem xt cn thn vic forwarding data v branches/jumps s tng tc vi nhau nh th no. y chng ta vn s dng y cc hm nh lab3. Trong pipeline,thay v s dng 1 single-cycle cho ton b cc lnh nh lab 3,clock s nhanh hn,v cc lnh s thc hin trong cc pha ca nhiu chu k clock.Mi pha ca lnh s chim 1 chu k clock.iu ny c ngha l khi 1 lnh c thc hin th ch c 1 phn ca CPU hot ng trong 1 chu k clock.

II.Thit k 1.Cu trc tng qut Pipelined chia thnh 5 state nh hnh di:

=>Cu trc MIPS:

*Cu trc thanh ghi PipeRegister: Mips pipelined chng ta s dng 4 PipeRegister: IF/ID ,ID/EX ,EX/MEM ,MEM/WB Cc reg ny c chc nng lu tr gi tr ca mi state v cp nht trng thi mi. PipeRegister c cu to t cc DFF tng t thanh ghi PC.

*Pipelining thay th b x l single-cycle bng 1 hng ca 5 miniprocessor,mi ci c kh nng hon thnh mt phn ca mi lnh. -Mi mt lnh c bt u mi chu k clock. -Cc thanh ghi inter-process (pipe register) lu tr thng tin lnh (data,write register,branch conditions)gia cc cycles m ton b instruction envelope c chuyn gia cc stage pipeline. -Khi pipeline c lp y cc lnh,mt lnh hon thnh mi chu k clock. -Cc thng tin iu khin phi c mang theo nh mt phn ca lnh bi v thng tin cng c yu cu cc stage khc ca pipeline.iu ny c th c lm bng cch thm vo cc bit thanh ghi lu tr inter-stage forward d liu iu khin cha c s dng. -Kt qu l cc thanh ghi inter-stage v cng ln.B x l cui cng s y cc tn hiu chc nng.

2.1 R-Type (add,sub,xor,slt) v I-Type (lw,sw,xori,addi)

2.2 Lnh Bne:

Kt qu c r nhnh hay khng c a ra MEM state,pht sinh xung t y s c gii quyt phn sau = Datapath (n cc tn hiu iu khin) :

Thm b muxSelRd chn thanh ghi ch gia cc lnh R-type v I-type (lw)

*Thm vo tn hiu iu khin:khi Control Unit

Cc tn hiu iu khin cng phi c chuyn theo cc state cng vi data. WB: RegWrite, MemtoReg M : MemRead, MemWrite EX : ALUop, Branch, ALUSrc, RegDst Bng tn hiu iu khin xy dng nh Mips single cycle ==>>Datapath bao gm c Control Unit:

2.3 Jr,Jump

a ch v tn hiu cho php nhy ca lnh J c a ra ID state. a ch v tn hiu cho php nhy ca lnh Jr c a ra EX state. 3.Xung t -Xung t xy ra v d liu c yu cu trong vic thc hin lnh hin ti c th cha c gi tr. -Mt lnh trong cycle IF c th cn d liu ca mt thanh ghi m gi tr ca n c th b thay i bng 1 lnh downstream(lnh trc) nhng vn trong tin trnh ca pipeline(trong ALU,memory,writeback cycle). -Do mt lnh upstream(lnh sau) c th truy cp 1 thanh ghi v ly d liu sai bi v d liu thanh ghi cha c cp nht bi lnh downstream(lnh trc). *C 2 loi hazard :data hazard control hazard.

3.1 Xung dt d liu -Data Hazard Data hazard xut hin khi mt lnh cn ni dung thanh ghi cho 1 lnh arithmetic/ logical/memory. Trng hp 1: add $5,$1,$4 sub $6,$4,$5

Trng hp 2: lw $4,12($0) add $5,$1,$4

Gii quyt xung t y chng ta c 2 cch: -Chuyn tip -Tr trng hp 2 c th dng phng php tr nhng trong thit k ny chng ta s dng k thut chuyn tip gii quyt ta thm : -1 b pht hin DataHazard l Forward Unit -1 b muxHazaLW gii quyt xung dt trng hp 2 m khng cn gy tr - 2 b mux3x32to32 *Thut ton c a ra cho b Forward Unit nh sau: -If ( RegWriteM=1) If (RsEX=RdM) CtrlA iu khin muxA sao cho u ra OutA=In2 Else CtrlA iu khin muxA sao cho u ra OutA=Rdata1 If (RtEX=RdM) CtrlB iu khin muxB sao cho u ra OutB=In2 Else CtrlB iu khin muxB sao cho u ra OutB=Rdata2 Else ( OutA=Rdata1 v OutB=Rdata2)

-If ( RegWriteWB=1) If (RsEX=RdWB) CtrlA iu khin muxA sao cho u ra OutA=In3 Else CtrlA iu khin muxA sao cho u ra OutA=Rdata1 If (RtEX=RdWB) CtrlB iu khin muxB sao cho u ra OutB=In3 Else CtrlB iu khin muxB sao cho u ra OutB=Rdata2 Else ( OutA=Rdata1 v OutB=Rdata2) V 2 b muxA v muxB l c 3 u vo nn CtrlA v CtrlB l 2 bit. Thay mux c 3 u vo bng b mux 4 u vo,mux 4 u vo ny c xy dng t 32 b mux4to1 xy dng trc

B muxHazaLW m u ra l In2 l b mux2x32to32 xy dng ,dng chn tn hiu ra da vo MemRead,nu MemRead=1 (ng vi lnh lw) th chn In2=ReadData (u ra ca DataMemory) v MemRead=0 th In2=DataAddress (ng vi cc lnh khc khng c b nh)

//=====================Forward unit===================== module Forward_unit(Rs,Rt,Rd1,Rd2,Rwrite1,Rwrite2,CtrlA,CtrlB); input Rwrite1,Rwrite2; input [4:0] Rs,Rt,Rd1,Rd2; output [1:0] CtrlA,CtrlB; wire [4:0] RsxorRd1,RsxorRd2,RtxorRd1,RtxorRd2; wire or1,or2,or3,or4; wire[1:0] CtrlA1,CtrlB1; //thuc hien xor giua Rs,Rt voi lan luot Rd1,Rd2 xor xor1(RsxorRd1[0],Rs[0],Rd1[0]), xor2(RsxorRd1[1],Rs[1],Rd1[1]), xor3(RsxorRd1[2],Rs[2],Rd1[2]), xor4(RsxorRd1[3],Rs[3],Rd1[3]), xor5(RsxorRd1[4],Rs[4],Rd1[4]), xor11(RsxorRd2[0],Rs[0],Rd2[0]), xor21(RsxorRd2[1],Rs[1],Rd2[1]),

xor31(RsxorRd2[2],Rs[2],Rd2[2]), xor41(RsxorRd2[3],Rs[3],Rd2[3]), xor51(RsxorRd2[4],Rs[4],Rd2[4]), xor12(RtxorRd1[0],Rt[0],Rd1[0]), xor22(RtxorRd1[1],Rt[1],Rd1[1]), xor32(RtxorRd1[2],Rt[2],Rd1[2]), xor42(RtxorRd1[3],Rt[3],Rd1[3]), xor52(RtxorRd1[4],Rt[4],Rd1[4]), xor113(RtxorRd2[0],Rt[0],Rd2[0]), xor213(RtxorRd2[1],Rt[1],Rd2[1]), xor313(RtxorRd2[2],Rt[2],Rd2[2]), xor413(RtxorRd2[3],Rt[3],Rd2[3]), xor513(RtxorRd2[4],Rt[4],Rd2[4]);

or or11(CtrlA1[0],RsxorRd1[0],RsxorRd1[1],RsxorRd1[2],RsxorRd1[3],
RsxorRd1[4]), //neu or11=0 =>Rs giong Rd1 or13(CtrlB1[0],RtxorRd1[0],RtxorRd1[1],RtxorRd1[2],Rtx orRd1[3], RtxorRd1[4]), //neu or13=0 =>Rt giong Rd1 or12(CtrlA1[1],RsxorRd2[0],RsxorRd2[1],RsxorRd2[2],RsxorRd2[3],Rs xorRd2[4]), //neu or12=0 =>Rs giong Rd2 or14(CtrlB1[1],RtxorRd2[0],RtxorRd2[1],RtxorRd2[2],RtxorRd2[3] ,RtxorRd2[4]); //neu or14=0 =>Rt giong Rd2 //khi co truong hop ghi vao thanh ghi thi moi can xem xet de dua ra tin hieu dieu khien,khong phai khi nao // rs,rt giong voi rd1,rd2 deu la xung dot,vi du lenh sw va add cung co thanh ghi dich nhung ko co xung dot //neu Rwrite1=0 thi CtrlA[0] va CtrlB[0] deu o muc cao or or21(CtrlA[0],CtrlA1[0],(~Rwrite1)), or22(CtrlB[0],CtrlB1[0],(~Rwrite1)), //neu Rwrite2=0 thi CtrlA[1] va CtrlB[1] deu o muc cao or23(CtrlA[1],CtrlA1[1],(~Rwrite2)), or24(CtrlB[1],CtrlB1[1],(~Rwrite2)); endmodule

//====================================================== === module mux4x32to32(DataIn0, DataIn1,DataIn2,DataIn3, Sel, DataOut); input [31:0] DataIn0, DataIn1,DataIn2,DataIn3; input [1:0] Sel; output [31:0] DataOut; mux4_1 mux0({DataIn0[0], DataIn1[0],DataIn2[0],DataIn3[0]},DataOut[0],Sel);

mux4_1 mux01({DataIn0[1], DataIn1[1],DataIn2[1],DataIn3[1]},DataOut[1],Sel); mux4_1 mux02({DataIn0[2], DataIn1[2],DataIn2[2],DataIn3[2]},DataOut[2],Sel); mux4_1 mux030({DataIn0[30], DataIn1[30],DataIn2[30],DataIn3[30]},DataOut[30],Sel); mux4_1 mux031({DataIn0[31], DataIn1[31],DataIn2[31],DataIn3[31]},DataOut[31],Sel); endmodule

module mux4_1(in4_1,out4_1,se4_1); input [3:0] in4_1; input [1:0] se4_1; output out4_1; assign out4_1= (in4_1[0]) && (!se4_1[0])&& (!se4_1[1]) || (in4_1[1]) && (se4_1[0])&& (!se4_1[1])

|| (in4_1[2]) && (!se4_1[0])&& (se4_1[1]) || (in4_1[3]) && (se4_1[0])&& (se4_1[1]) ; Endmodule 3.2 Xung t iu khin -Control Hazards ( Branch Hazards ) Control hazard xut hin khi 1 lnh r nhnh ang c gi v d liu cn thit bt u lnh r nhnh cha c ga tr trong cng 1 chui lnh trc . Xung t iu khin xy ra vi cc lnh bne,jr,j

Quyt nh r nhnh hay khng ca lnh bne xy ra Mem state Ca lnh Jr EX state cn ca lnh Jump ID state Nu r nhnh xy ra: Bne: Flush cc lnh i theo sau bne cho n trc lnh nhy n InstrMemory,ID state,EX state Jr : Flush cc lnh i theo sau Jr cho n trc lnh nhy n InstrMemory,ID state J : Flush cc lnh i theo sau bne cho n trc lnh nhy n InstrMemory

Gii quyt xung t: -Thay i datapath vi lnh bne sang EX state s gim bt cng vic Flush EX state -Thm b muxControl dng xa tn hiu iu khin (xa lnh ID state) - Thm b muxOpcode dng iu khin khi Control thc hin lnh NOP (xa lnh InstrMemory) -Thm b x l xung t Control Haza Unit vi u vo l cc iu kin nhy (Jreg,Jump,BranchSel )v u ra iu khin vic flush (Ctrl_1,Ctrl_2)nu xy ra r nhnh.Ctrl_1 xa tn hiu iu khin v 0 (xa lnh ID state), Ctrl_2 xa InstrMemory

module muxOpcode(DataIn0, DataIn1, Sel, DataOut); input [5:0] DataIn0, DataIn1; input Sel; output [5:0] DataOut; mux2to1 mux0 (DataIn0[0 ], DataIn1[0 ], Sel, DataOut[0 ]); mux2to1 mux1 (DataIn0[1 ], DataIn1[1 ], Sel, DataOut[1 ]); mux2to1 mux2 (DataIn0[2 ], DataIn1[2 ], Sel, DataOut[2 ]); mux2to1 mux3 (DataIn0[3 ], DataIn1[3 ], Sel, DataOut[3 ]); mux2to1 mux4 (DataIn0[4 ], DataIn1[4 ], Sel, DataOut[4 ]); mux2to1 mux5 (DataIn0[5 ], DataIn1[5 ], Sel, DataOut[5 ]); endmodule

module muxControl(DataIn0, DataIn1, Sel, DataOut); input [10:0] DataIn0, DataIn1; input Sel; output [10:0] DataOut; mux2to1 mux0 (DataIn0[0 ], DataIn1[0 ], Sel, DataOut[0 ]); mux2to1 mux1 (DataIn0[1 ], DataIn1[1 ], Sel, DataOut[1 ]); mux2to1 mux9 (DataIn0[9 ], DataIn1[9 ], Sel, DataOut[9 ]); mux2to1 mux10(DataIn0[10], DataIn1[10], Sel, DataOut[10]); endmodule

//==============Control Hazards Unit======================= module ControlHazard(jreg,jump,BranchSel,Ctrl_1,Ctrl_2); input jreg,jump,BranchSel; output Ctrl_1,Ctrl_2; or orjregbne(Ctrl_1,jreg,BranchSel); or or3branch(Ctrl_2,jreg,jump,BranchSel); endmodule

Xy dng cc Pipe Register: IF/ID : 32b u ra khi (ADD PC+4) + 32b Instr =64b ID/EX: 9b iu khin (RegDst,Branch,MemRead,MemtoReg,MemWrite,ALUSrc,RegWrite,ALUop,) +32b (PC+4) +32b Read Data1 + 32b Read Data2 + 32b Extend +5b Rs+5b Rt+5b d =152b EX/MEM : 5b iu khin (Branch,MemRead,MemtoReg,MemWrite,RegWrite) + 32b ALU out +32b Read Data2 +5b Rd =74b MEM/WB : 2b iu khin + 32b Read Data +32b ALU out +5b Rd =71b //----------reg IF/ID---------------module reg_1(in,out,clk,reset,enable); input clk, reset,enable; input [63:0] in; output [63:0] out; D_FF dffreg1(out[0] ,in[0] ,reset,clk,enable); D_FF dffreg2(out[1] ,in[1] ,reset,clk,enable); .. D_FF dffreg64(out[63] ,in[63] ,reset,clk,enable); Endmodule //----------reg ID/EX---------------module reg_2(in,out,clk,reset,enable); input clk, reset,enable; input [151:0] in; output [151:0] out; D_FF dffreg1(out[0] ,in[0] ,reset,clk,enable); D_FF dffreg2(out[1] ,in[1] ,reset,clk,enable); D_FF dffreg152(out[151] ,in[151] ,reset,clk,enable); Endmodule //----------reg EX/MEM---------------module reg_3(in,out,clk,reset,enable); input clk, reset,enable; input [73:0] in; output [73:0] out; D_FF dffreg1(out[0] ,in[0] ,reset,clk,enable); D_FF dffreg2(out[1] ,in[1] ,reset,clk,enable);

 D_FF dffreg74(out[73] ,in[73] ,reset,clk,enable); endmodule //----------reg MEM/WB---------------module reg_4(in,out,clk,reset,enable); input clk, reset,enable; input [70:0] in; output [70:0] out; D_FF dffreg1(out[0] ,in[0] ,reset,clk,enable); D_FF dffreg2(out[1] ,in[1] ,reset,clk,enable); . D_FF dffreg71(out[70] ,in[70] ,reset,clk,enable); Endmodule

*Code tng hp
`timescale 1 ps / 100 fs module mips(clk,reset,ZeroFlag, OverflowFlag, CarryFlag, NegativeFlag); input clk,reset; output ZeroFlag, OverflowFlag, CarryFlag, NegativeFlag; // PC and Instruction Memory wire [31:0] PC, PCin; wire [31:0] PC4,PC4_0,PC4_1A,PC4_1B,PC4_1C,PC4_2; // PC4 = PC+4 wire [31:0] instruction,instruction_out; // Main Control wire RegDst,Jump,Branch,MemRead,MemtoReg,MemWrite,ALUSrc,RegWrite,level, RegDst0,Jump0,Branch0,MemRead0,MemtoReg0,MemWrite0,ALUSrc0, RegWrite0,level0,RegDst1,Branch1,MemRead1,MemtoReg1,MemWrite1, ALUSrc1,RegWrite1,Branch2,MemRead2,MemtoReg2MemWrite2,RegWrite2, MemtoReg3,RegWrite3; wire [1:0] ALUop0,ALUop,ALUop1; // regfile wire [4:0] Rd,Rd11,Rd21,Rd3,Rd4,Rs1; wire [31:0] WD,RData1,RData2,RData1_out,RData2_out; // sign_extend wire [31:0] SignOut,SignOut1; // ALU2 --ALU main wire [31:0] BusA,BusB,BusBIn; wire [1:0] ALUcontrol; wire [31:0] ALUOut; wire zeroOut; // ALU control wire jreg; // Data Memory wire [31:0] DataAdd,DataAdd_out,WriteData,ReadData; wire [31:0] DataAddOut,ReadDataOut; // Branch wire BranchSel; wire [31:0] MuxBranchOut; // Jump wire [31:0] JleftOut,JleftOut1; wire [31:0] MuxJumpOut; //Forwar unit

wire [1:0] CtrlA,CtrlB; // Control Hazards Unit wire [5:0] muxOpcode_out; wire Ctrl_1,Ctrl_2; // Code here // PC4 = PC + 4 Add Add_PC4(PC,32'b100,PC4); // InstructionMem InstructionMem InstructionMem1(instruction, PC); // Main Control Control Control1(instruction_out[31:26],//Opcode RegDst,Jump,Branch, MemRead,MemtoReg,ALUop,MemWrite, ALUSrc,RegWrite,level); // Regfile regfile regfile1( instruction_out[25:21], //ReadRegister1 instruction_out[20:16], //ReadRegister2 Rd,WD,RegWrite3, RData1, RData2,clk,reset); // Sign-extend sign_extend sign_extend_1(instruction_out[15:0],SignOut,level0); // Select Bus B for ALU main mux2x32to32 mux_sel_BusB(BusBIn,SignOut1, ALUSrc1, BusB); // ALU control ALUcontrol_Block ALUcontrol1(ALUop1, SignOut1[5:0], // Function ALUcontrol,jreg); // ALU Block ALU ALU1(BusA, //BusA of ALU BusB, ALUcontrol, ALUOut,ZeroFlag,OverflowFlag,CarryFlag,NegativeFlag); // Data Memory datamem DataMem1(ReadData, //data DataAdd, //address WriteData, //writedata MemWrite2, //writeenable MemRead2, //readenable clk); // Select Data to WriteData for regfile mux2x32to32 mux_Sel_WriteData(DataAddOut, //DataIn0 ReadDataOut, //DataIn1

MemtoReg3, //Sel WD); //DataOut shift_left_2 shift_left_2_branch(SignOut1, //In32 PC4_1B); //Out32 Add BranchAdd(PC4_1A, //A PC4_1B, //B PC4_1C); // // Jump shift_left_2 shift_left_2_jump({6'b0,instruction_out[25:0]},JleftOut); //Out32 ~ 28-bit after shifting left 2 bits // Branch and #(50) BranchSelGate(BranchSel,Branch1,(~ZeroFlag)); mux2x32to32 muxBranch(PC4, //DataIn0 PC4_1C, //DataIn1 BranchSel, //Sel MuxBranchOut); //DataOut // mux cho lenh JUMP mux2x32to32 muxJump(MuxBranchOut, //DataIn0 {PC4_0[31:28],JleftOut[27:0]}, //DataIn1 Jump0, //Sel MuxJumpOut); //DataOut // mux dung cho lenh JR mux2x32to32 muxJr(MuxJumpOut,RData1_out,jreg,PCin); // PC Block PC_Block PC_Block1(PCin, PC,clk,reset,1); // module muxControl(DataIn0, DataIn1, Sel, DataOut); muxControl MuxControl1({RegDst,Jump,Branch,MemRead,MemtoReg,ALUop, MemWrite,ALUSrc,RegWrite,level},11'b0,Ctrl_1, {RegDst0,Jump0,Branch0,MemRead0,MemtoReg0, ALUop0,MemWrite0,ALUSrc0,RegWrite0,level0}); //muxOpcode(DataIn0, DataIn1, Sel, DataOut); muxOpcode muxOpcode1(instruction[31:26],6'b111111,Ctrl_2,muxOpcode_out); // module ControlHazard(jreg,jump,BranchSel,Ctrl_1,Ctrl_2); ControlHazard ControlHazard1(jreg,Jump,BranchSel,Ctrl_1,Ctrl_2); //module mux2x5to5(AddressIn0, AddressIn1, Sel, AddressOut) ; mux2x5to5 muxSelRd(Rd21,Rd11,RegDst1,Rd3); // xung dot data Forward_unit Forward_unit_DataHaza(Rs1,Rd21,Rd4,Rd,RegWrite2,

RegWrite3,CtrlA,CtrlB); //module mux4x32to32(DataIn0, DataIn1,DataIn2,DataIn3, Sel, DataOut); // Sel=00 :DataIn3 // Sel=10 :DataIn2 // Sel=01 :DataIn1 // Sel=11 :DataIn0 mux4x32to32 muxDataHaza_BusA(RData1_out,DataAdd_out, WD,32'b0, CtrlA, BusA); mux4x32to32 muxDataHaza_BusBIn(RData2_out,DataAdd_out, WD,32'b0, CtrlB, BusBIn); //mux haza lw mux2x32to32 muxHazaLW(DataAdd,ReadData,MemRead2,DataAdd_out); //reg_1 IF/ID reg_1 reg_IF_ID({PC4,muxOpcode_out,instruction[25:0]}, {PC4_0,instruction_out},clk,reset,1); //reg_2 ID/EX reg_2 reg_ID_EX({RegDst0,Branch0,MemRead0,MemtoReg0,MemWrite0, ALUSrc0,RegWrite0,ALUop0,PC4_0,RData1,RData2,SignOut, instruction_out[15:11],instruction_out[20:16],instruction_out[25:21]}, {RegDst1,Branch1,MemRead1,MemtoReg1,MemWrite1,ALUSrc1,RegWrite1,AL Uop1,PC4_1A,RData1_out,RData2_out,SignOut1,Rd11,Rd21,Rs1},clk,reset,1); //reg_3 EX_MEM reg_3 reg_EX_MEM({Branch1,MemRead1,MemtoReg1,MemWrite1,RegWrite1, ALUOut,BusBIn,Rd3}, {Branch2,MemRead2,MemtoReg2,MemWrite2,RegWrite2, DataAdd, WriteData,Rd4},clk,reset,1); //reg_4 MEM_WB reg_4 reg_MEM_WB({MemtoReg2,RegWrite2,ReadData,DataAdd,Rd4}, {MemtoReg3,RegWrite3,ReadDataOut,DataAddOut,Rd}, clk,reset,1); endmodule

*S khi MIPS PIPELINED CPU

C o n tro l : C o n tr o l 1 r e g _ 1 : r e g _ IF _ I D P C _ B l o c k :P C _ B lo c k 1 B r a n c h S e l G a te
S el D a t a In 0 [3 1 . .0] D a t a In 1 [3 1 . .0] D a ta O ut [31. .0 ] Reg D s t Jump Br a n c h M emR ead o u t[ 6 3 . 0 ] O p c o d e [5 . .0 ] M e m to R e g M e m W r it e AL U S r c R e g W r i te l e ve l 1 D at a In 0[ 1 0 ..0 ] D a taO u t[1 0 . .0 ]

m u x2 x 3 2 to 3 2 :m u xB r a n c h
Se l

m u x2 x 3 2 t o 3 2 :m u xJ u m p
S el D a t a O u t[ 3 1.. 0 ]

m u x 2 x 3 2 to 3 2 : m u x J r
1 D a t aO u t[ 3 1 .. 0]

c lk reset e n a bl e P C in [ 31 . .0] P C o u t [3 1 .. 0 ]

A d d :A d d _ P C 4
A [ 3 1 ..0 ] 1 Y[ 3 1 .. 0 ]

clk r e s et e n a bl e i n [6 3. .0 ]

C o n tr o l H a z a r d :C o n tr o l H a z a r d 1 m u x C o n tr o l :M u x C o n tr o l 1
jreg jum p B ranchSel C t r l_ 1 C t r l_ 2 c lk r e se t e n ab le S el

r e g _ 2 :r e g _ ID _ E X

D a ta In 0 [ 31 . .0 ] D a ta In 1 [ 31 . .0 ]

D a ta In 0[ 3 1 .. 0] D a ta In 1[ 3 1 .. 0]

3 2 ' h 0 0 0 0 0 0 0 4 B- [ 3 1 ..0 ] -

I n s tru c ti o n M e m :In s tr u c t i o n M e m 1m u x O p c o d e :m u x O p c o d e 1 r e g _ 3 :r e g _ E X _ M E M
cl k

A L U O p[ 1 .. 0 ]

r e g _ 4 :r e g _ M E M _ W B
clk reset 1 e n a b le o u t[ 70 . .0 ] i n [7 0 .. 0] a dd r es s _ i ns tr [ 3 1 ..0 ] i ns tr u c t io n [ 31 . .0]

S el D a t a In0 [ 5. .0 ] D a ta O u t[5 . .0 ]
6 ' h 3 F - - D a t a In1 [ 5. .0 ]

m u x 4 x 3 2 t o 3 2 :m u x D a ta H a z a _ B u s A
o u t [1 5 1 ..0 ] D a t aI n 0 [3 1. .0 ] D a t aI n 1 [3 1. .0 ] D a t aI n 2 [3 1. .0 ]
3 2 ' h 0 0 0 0 0 0 00 D- a t aI n 3 [3 1. .0 ] -

A L U :A L U 1
Zero D a t a O ut [3 1 .. 0 ] B u s A [ 3 1. .0 ] B u s B [ 3 1. .0 ] A L U C o n t r o l[ 1. .0 ] O ve r flo w C a r r yO u t N e g a ti ve O ut p u t[ 3 1. .0]

A L U c o n tr o l _ B l o c k :A L U c o n tr o l 1
A L U O p [1 . .0 ] F u n ct io n [5 . .0 ] jreg AL U c o n tr ol [1 . .0]

re s e t en m u x 4 x 3 2 to 3 2 :m u x D a t a H a z a _ B u s1 B In a b le D a t a In 0 [3 1 . .0] D a t a In 1 [3 1 . .0] D a t a In 2 [3 1 . .0] D a ta O ut [31. .0 ] in [7 3 .. 0 ] out[7 3 . .0 ]

r e g fi l e :r e g fi l e 1
R e g W r i te c lk reset R e a d R e g is t e r 1 [4 . .0 ] R e a d R e g is t e r 2 [4 . .0 ] W r i te R e g i s t e r [4 . .0 ] W r i te D a t a[3 1 . .0 ] R e ad D a ta 1 [31. .0 ] R e ad D a ta 2 [31. .0 ]

s i g n _ e x te n d : s i g n _ e x te n d _ 1
1 1 ' h 0 0 0 - - D at a In 1[ 1 0 ..0 ]

i n[ 15 1 .. 0 ]

l e ve l I n 1 6 [1 5 .. 0 ]

O ut3 2 [3 1 . .0 ]

S e l [1 . .0 ]

Z e ro F la g O v e r fl o w F l a g C a rry F la g N e g a t i ve F l a g

s h i ft_ l e f t_ 2 :s h i ft_ le ft_ 2 _ b r a n c h

A d d :B r a n c h A d d
A [3 1 . .0 ]

3 2 ' h 0 0 0 0 0 0 0 0 D- a t a In 3 [3 1 . .0] -

m u x2 x 3 2 to 3 2 : m u x _ s e l _ B u s B
Sel D a t aI n 0 [3 1. .0 ] D a t aI n 1 [3 1. .0 ] D a t a O ut [3 1 .. 0 ]

S e l[1 . .0 ] B [3 1 . .0 ] Y [ 3 1 .. 0 ]

In 3 2 [31 . .0 ]

O u t 3 2 [3 1 . .0 ]

s h ift_ l e ft_ 2 : s h i ft_ l e ft_ 2 _ j u m p

6' h 0 0 - -

In 3 2 [31 . .0 ]

O u t 3 2 [3 1 . .0 ]

d a t a m e m :D a ta M e m 1
w r i tee n a b l e r e a den ab l e

m u x 2 x 3 2 to 3 2 :m u x H a z a L W
S el D at a In 0 [ 31 .. 0] D a ta O u t[ 31 . .0 ]

clk

clk ad d r es s _ d a t a[ 3 1 .. 0] w r i ted a t a [3 1 .. 0 ]

d a ta [3 1 . .0 ]

D at a In 1 [ 31 .. 0]

m u x2 x 3 2 to 3 2 :m u x _ S e l _ W r i te D a ta
Sel D a ta In 0 [3 1 .. 0 ] D a ta In 1 [3 1 .. 0 ] D at a O u t[ 3 1 .. 0]

F o r w a r d _ u n i t :F o r w a r d _ u n i t _ D a ta H a z a
R w r it e 1 R w r it e 2 R s [4 ..0 ] R t[ 4 ..0 ] R d 1 [4. .0 ] R d 2 [4. .0 ] C tr lA[1 . .0 ] C tr lB[1 . .0 ]

m u x 2 x 5 to 5 :m u x S e l R d
Sel A d d re s s I n 0[ 4 .. 0 ] A d d re s s I n 1[ 4 .. 0 ] A d d r e s s O u t[ 4. .0 ]

re s e t

*M phng trn model sim

Cc lnh m phng :add, sub, xor, slt, addi, xori,sw, lw,bne, bne, j, jr. (12 lnh) 1,Trng hp 1: 0 Addi $21,$0,1 4 Addi $22,$0,2 8 Addi $23,$0,3 12 Addi $24,$0,80 16 sw $21,0($0) 20 sw $22,4($0) 24 sw $23,8($0) 28 sw $24,12($0) 32 lw $1,0($0) //[$1]=1 36 lw $2,4($0) //[$2]=2 40 lw $3,8($0) //[$3]=3 44 lw $4,12($0) //[$4]=80 Xung t d liu dng 1 $5 v dng 2 $4 48 add $5,$1,$4 //[$5]=81 52 sub $6,$4,$5 //[$6]=-1 56 xor $7,$1,$2 //[$7]=3 60 slt $8,$1,$2 //[$8]=1 64 xori $9,$1,2 //[$9]=3 68 sw $4,16($0) 72 jr $4 // nhay den vi tri dc luu tru trong $4

76 add $11,$0,$1 //[$11]=0+1=1 80 addi $10,$2,3 //[$10]=2+3=5 84 bne $1,$2,label_1 88 add $10,$3,$4 //[$10]=3+80=83 Xung t iu khin 92 label_1: lw $9,16($0) //[$9]=80 96 bnez $1,label_2 // <=> bne $1,$0,label_2 100 add $10,$2,$4 //[$10]=2+80=82 Xung t iu khin 104label_2: j label_2

2,Trng hp 2: 0 Addi $21,$0,2 //[$21]=2 4 Addi $22,$0,2 //[$22]=2 8 Addi $23,$0,3 //[$23]=3 12 Addi $24,$0,80 //[$24]=80 16 sw $21,0($0) 20 sw $22,4($0) 24 sw $23,8($0) 28 sw $24,12($0) 32 36 40 lw $1,0($0) lw $2,4($0) lw $3,8($0) //[$1]=2 //[$2]=2 //[$3]=3

44 lw $4,12($0) //[$4]=80 Xung t d liu dng 1 $5 v 48 add $5,$1,$4 //[$5]=82 dng 2 $4 52 sub $6,$4,$5 //[$6]=-2 56 xor $7,$1,$2 //[$7]=0 60 slt $8,$1,$2 //[$8]=0 64 xori $9,$1,2 //[$9]=0 68 sw $4,16($0) 72 jr $4 //nhay den Addi $10,$2,3 //[$10]=2+3=5 76 add $11,$0,$1 //[$11]=0+2=2 80 addi $10,$2,3 //[$10]=2+3=5 84 bne $1,$2,label_1 88 add $10,$3,$4 //[$10]=3+80=83 92 label_1: lw $9,16($0) //[$9]=80 96 bnez $1,label_2 // <=> bne $1,$0,label_2 100 add $10,$2,$4 //[$10]=2+80=82 Xung t iu khin 104label_2: j label_2

Kt lun:

Qua m phng trn phn mm ModelSim cho ta kt qu ng nh thit k mong mun,MIPS hot ng tt cho kt qu chnh xc tt c cc lnh thit k,gii quyt DataHazard v ControlHazard tt.Kt qu m phng cng cho thy so vi MIPS single cycle th MIPS pipeline hot ng nhanh hn rt nhiu.