LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
ENTITY fig9_60
PORT(
sw
oe
s
NTADO POR A
);

IS
: IN BIT_VECTOR(9 DOWNTO 0);
: IN BIT;
: OUT STD_LOGIC_VECTOR (4 DOWNTO 0) -- SEJA O ULTIMO BIT REPRESE

END fig9_60;
ARCHITECTURE a OF fig9_60 IS
BEGIN
s <=

END a;

"00000" WHEN ((oe = '0') OR

"10011" WHEN sw(9) =
"10001" WHEN sw(8) =
"01111" WHEN sw(7) =
"01101" WHEN sw(6) =
"01011" WHEN sw(5) =
"01001" WHEN sw(4) =
"00111" WHEN sw(3) =
"00101" WHEN sw(2) =
"00011" WHEN sw(1) =
"00001" WHEN sw(0) =

(sw = "1111111111")) ELSE

'0' ELSE
'0' ELSE
'0' ELSE
'0' ELSE
'0' ELSE
'0' ELSE
'0' ELSE
'0' ELSE
'0' ELSE
'0';