DLD MID-I

(1)(110101)2= (
[
]

) 10

(a) 52

(b) 40

(2)(0.6875)10=(
[

(c) 53

(d) 55

)2

(a)
0.0011
(d) 0.1000
(3) (25)10= (

(b) 0.1011

0.1010

(c)

11101

)2

10001
(d) 11001

(b)

(a)

(4) (C6B.F) 16= (

[
]

01000

)2

(a) 11001010.111
11001000.101
(5) Represent
[
]

(c)

(b)

10001010.001

(c)

11000010.100

(-17)10 in sign magnitude form.

(a) 010001
(d) 010011

(b)

110011

(6) (111011)G=(
[
]

)2

(a) (100001)
(d) 100100

(b) (101101)

(c)

110001

(c)

( 110001)

(7) x+xy=
[
]
(a) (x+x)(x+x)
(d) (X+X) (X+Y)
(8)---------------[
]

(b) (x+y)(x+x)

(c)

x2+xy

is a group of 8 logical is in a karnaugh map method.

(a) Quad
(d) Single
(9) (1110010)2= (
[
]

(b) Pair

(c) Octal
)G

(d)

(a) 1001010
(d) 1001011

(b) 1000011

(c)

1001000

(10) What is the complement of the function F=X1YZ1+X1Y1Z

[
]
(a) (x1+y1+z)(x+y+z1)
(d)(x+y1+z)(x1+y+z1)

(b) (X+Y1+Z)(X+Y+Z1) (c) (x+y+z1)(x+y1+z1)

(11) Simplify the Boolean function F=A1C+A1B+AB1C+BC

[
]
(a) C+A1B
(d) C1+AB1

(b) C1+AB

(c) C+A1B1

(12) Simplify the Boolean function F(X ,Y ,Z)=(0,2,4,5,6)

[
]
(a) Z+XY1
(d) Z1+X1Y1

(b) Z1+X1Y

(c) Z1+XY1

(13) ------------- is a combinational circuit that performs the substraction of 2 bits

taking in to account a
[

bit of lowest significant of age is known as.

]

(a) Half substractor

( d) Full subtract or
(14) ---------------n-input lines and
[

(b) Half Adder

(c)

Full Adder

is a combinational circuit that converts binary information from

products maximum of 2n output lines.

]

(a)
Encoder
(d) priority encoder

(b) Decoder

(c)

Multiplexer

(15) ------------------ is a combinational circuit that selects binary information from one
of many input lines
[

and directs at to a single output line is called.

]

(a) Data selector

(d) priority encoder

(b) Decoder

(c)

Encoder

(16) --------------- is a digital circuit that performs reverse operation from that of a
decoder.
[
]
(a) Decoder
(d) Encoder

(b)

Multiplexer

(c)

priority encoder

(17) Any Boolean function with 4 variables can be implemented with -----------multiplexer.
[
]
(a) 41 MUX
(d) 32x1 MUX

(b) 81 MUX

(c) 161 MUX

(18) For 3-varibles, these are ------------- to -------------- minterms are available.
[
]
(a) 0, 4
(d) 2x4

(b) 1,3

(c) 0,3

(19) Which of the following gates are called universal gates?

[
]
(a) AND and OR
(d) NAND and NOR gates

(b) NOT and AND

(c) EX-0R and EX-NOR

(20) --------------- is an elementary building block of a digital circuit.

[
]
(a) Integrated Circuit (b) Logic gate
(d) Sequential circuit

(c) Combinational circuit