1

2 RNG0 RNG1

COUNT F CH-AB SEL2 SEL1 SEL0 VCC VCC

Y1
F

PG0

C5 104 R3
IO15 IO14 IO13 IO12 IO11 IO10 IO9 IO8 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 32 31 30 29 28 27 26 25 22 21 20 19 18 17 16 15 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 TRIG7 DD6 DD5 DD4 DD3 DD2 DD1 DD0

10MHz C1 20pF
GND

Speed Option C2 20pF

GND

10MHz - 57Kb 20MHz - 115Kb

U6
COUNT ZZ-CLK READ 20 27 22 CE WE OE A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 26 2 23 21 24 25 3 4 5 6 7 8 9 10 PG0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 PG0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 X 3 SI 10 9 8 7 6 5 4 3 44 43 42 41 40 39 38 37 2 36 DD7 24 14 33

U2
IO31 IO30 IO29 IO28 IO27 IO26 IO25 IO24 IO23 IO22 IO21 IO20 IO19 IO18 IO17 IO16 IN3 MODE/IN2 SDO/IN1 SDI/IN0 SCLK/Y2 Y1/RESET Y0 35 11

1K0

GND

U1 Channel A/B clock control D-DATA

1 2 3 4 GND 5 6 7 8 9 RA2 RA3 RA4 MCLR VSS RB0 RB1 RB2 RB3 RA1 18 17 16 15 14 13 12 11 10 E

U4
SEL2 SEL1 SEL0 GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 9 10 11 6 4 2 5 1 12 15 14 13 C B A INH X7 X6 X5 X4 X3 X2 X1 X0

Range 1 Range 0

Spock

PIC

RA0 CLKI CLKO VDD RB7 RB6 RB5 RB4

E VCC

C11 104
GND

AD3 AD0 AD1 AD2 AD4 AD6 AD7 AD5

19 18 17 16 15 13 12 11

D7 D6 D5 D4 D3 D2 D1 D0

A-DATA SEL 0 SEL 1 SEL 2

____ store/read Serial In Serial Out ____ shift/count

5C2568

MAX4051

Scope BUS

U7
COUNT D ZZ-CLK READ 20 27 22 CE WE OE A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 26 2 23 21 24 25 3 4 5 6 7 8 9 10 PG0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

ISPEN

13

VCC

PIC16F84

LSI-1016 U5
SEL2 SEL1 SEL0 GND TRIG7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 9 10 11 6 4 2 5 1 12 15 14 13 C B A INH VCC X7 X6 X5 X4 X3 X2 X1 X0 VCC A-DATA D-DATA

____ shift/count ____ store/read R1

ZZ-CLK VCC

DD3 DD0 DD1 DD2 DD4 DD6 DD7 DD5

19 18 17 16 15 13 12 11

D7 D6 D5 D4 D3 D2 D1 D0

470R
VCC 4

R42 47K
3

U3B 5 6 4 3

U3A 2 1 VCC 5

R2 2K2
2 3

U8A
Q

D CLK

74AHC86

74AHC86 U3D 11 13 12 6

5C2568

MAX4051

Logic Analyser BUS

CL

R43 47K

PR

R11 * 220R
GND

STOR

GND 74AHC86

74AHC74
VCC 8

U19

C54

DIG-801
RNG1 RNG0 COUNT B STOR ZZ-CLK DD[0..7] RNG1 RNG0 COUNT STOR ZZ-CLK DD[0..7]

Interface
SER-I

22pF Clock Doubler disable * Default configuration is:Short C54, omit R11
SER-I

OUT

50MHz

8 Bit Logic Analyzer

POD-A POD-B

SER-O

SER-O

POWER SERIAL I/O

MCLR

MCLR

R4
B

2K2

C53 10n
VCC GND

JP1 OMIT
VCC 1 3 5 7 9 2 4 6 8 10

A/D-401
RNG1 RNG0 CH-AB PG0 STOR ZZ-CLK ZZ-CLK* AD[0..7] RNG1 RNG0 PG1 PG0 STOR ZZ-CLK ZZ-CLK* AD[0..7]

bs11-3.sch
POD-B POD-A

C6 104
GND GND

2 Channel Osilloscope
Modular ADC

isp-PIC
Normally Shorted GND

CNT-1 CNT-2

VDD

VCC

BitScope Designs
Title
BitScope CPU and Storage Engine

Sheet 1 of 5
Rev 1.1

(C) 2000 BitScope Designs

1 2 3

bs11-4.sch
4

bs11-2.sch
5 6

A3
GND 7 VSS VEE

Document Number PCB 11

23-Aug-2000
8 9

Date:

E:\WINDOWS\NJJ\BITSCOPE\SCH\BS11\BS11-1.SCH