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Philips Tda9321h
Philips Tda9321h
DATA SHEET
Philips Semiconductors
Preliminary specication
TDA9321H
Horizontal synchronization circuit with switchable time constant for the PLL and Macrovision/subtitle gating Horizontal synchronization pulse output or clamping pulse input/output Vertical count-down circuit Vertical synchronization pulse output Two-level sandcastle pulse output I2C-bus control of various functions Low dissipation. GENERAL DESCRIPTION The TDA9321H (see Fig.1) is an input processor for High-end television receivers. It contains the following functions: Multistandard IF amplifier with PLL demodulator QSS-IF amplifier and AM sound demodulator CVBS and Y/C switch with various inputs and outputs Multistandard colour decoder which can also decode the PALplus helper signal Integrated baseband delay line (64 s) Sync processor which generates the horizontal and vertical drive pulses for the feature box (100 Hz applications) or display processor (50 Hz applications). The supply voltage for the TDA9321H is 8 V.
VERSION SOT319-2
1998 Dec 16
Philips Semiconductors
Preliminary specication
TDA9321H
MAX.
UNIT
8.8 5
V mA V V V V V
V V V mA mV mV V V V V V mV
Vo(CVBSTXT)(p-p) CVBS output signal for teletext (peak-to-peak value) Io(TAGC) Vo(QSS)(rms) Vo(AM)(rms) Vo(V)(p-p) Vo(U)(p-p) Vo(Y)(b-w) Vo(hor) Vo(ver) Vo(sc)(p-p)
1998 Dec 16
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andbook, full pagewidth
XTALA
XTALB
XTALC
COMB FILTER
subcarrier
XTALD
1998 Dec 16
VIF1 2 VIFVCO1 VIFVCO2 TAGC 7 8 62 VIF AMPLIFIER AND PLL DEMODULATOR AGC/AFC AFC SOUND TRAP VIFO 10 TOP QSS MIXER AM DEMODULATOR SIF AMPLIFIER AGC SUPPLY VIF2 DECVIF VIFPLL 3 4 6 SIF1 63 SIF2 64 DECSIF QSS/AM 1 5 VP1 VP2 DECDIG DECBG 11 45 33 35 58 VIDEO AMPLIFIER MUTE mute GDI GDO 12 13 GROUP DELAY CORRECTION switch control Y/CVBS CVBSint 14 AV1 15 CVBS1 16 AV2 17 CVBS2 18 SW0 19 CVBS/Y3 C3 SW1 CVBS/Y4 C4 AS 20 21 22 23 24 48 VIDEO SWITCHES AND CONTROL Y/C DETECTOR AUTOMATIC CHROMINANCE CONTROL VIDEO IDENTIFICATION
BLOCK DIAGRAM
Philips Semiconductors
VA 61
SCL 46
SDA 47
PULSE GENERATOR
VERTICAL DIVIDER
I2C-BUS TRANSCEIVER
42 RGB MATRIX 43 40
Y-delay
Y Y
TDA9321H
49 50 51
Y-DELAY
Y/U/V SWITCH
IDENT Y SYNC SEPARATOR SYNC IN-LOCK DETECTOR Y-SWITCH AND TRAPS helper U V
R-Y
B-Y
CLOCHE FILTER
FILTER TUNING
fsc
SECAM DECODER
hue
BANDPASS FILTER
SYSTEM IDENTIFICATION
PAL/NTSC DEMODULATOR
34
32
26
25
27
28
29
9 GND1
31 GND2
44 GND3
30 REFO
54
55
56
57
52 LFBP
MGR473
Preliminary specication
TDA9321H
Philips Semiconductors
Preliminary specication
TDA9321H
DESCRIPTION digital supply decoupling CVBS output for teletext band gap decoupling red input 1 green input 1 blue input 1 RGB insertion input 1 RGB insertion input 2 red input 2 green input 2 blue input 2 ground 3 positive supply 2 (+8 V) serial clock input (I2C-bus) serial data input/output (I2C-bus) address select input (I2C-bus) luminance output U-signal output V-signal output loop lter burst phase detector SECAM PLL decoupling crystal A (4.433619 MHz) crystal B (3.582056 MHz) crystal C (3.575611 MHz) crystal D (3.579545 MHz) phase 1 loop lter sandcastle pulse output horizontal pulse output or clamp pulse input/output vertical pulse output tuner AGC output SIF input 1 SIF input 2
1998 Dec 16
Philips Semiconductors
Preliminary specication
TDA9321H
60 HA/CLP
57 XTALD
56 XTALC
55 XTALB
54 XTALA
53 DECSEC
58 PH1LF
62 TAGC
52 LFBP 51 VO 50 UO 49 YO 48 AS 47 SDA 46 SCL 45 VP2 44 GND3 43 BI2 42 GI2 41 RI2 40 RGB2 39 RGB1 38 BI1 37 GI1 36 RI1 35 DECBG 34 CVBSTXT 33 DECDIG CVBSPIP 32
1 2 3 4 5 6 7 8 9
VIFO 10 VP1 11 GDI 12 GDO 13 CVBSint 14 AV1 15 CVBS1 16 AV2 17 CVBS2 18 SW0 19 CVBS/Y3 20 C3 21 SW1 22 CVBS/Y4 23 C4 24
TDA9321H
SYS1 25
59 SCO
64 SIF2
63 SIF1
61 VA
CVBSCF 26
SYS2 27
YCF 28
CCF 29
REFO 30
GND2 31
MGR474
1998 Dec 16
Philips Semiconductors
Preliminary specication
TDA9321H
The input of the ident circuit is connected to pin 14 (see Fig.3). This has the advantage that the ident circuit can also be made operative when a scrambled signal is received (descrambler connected between pins 10 and 14). A second advantage is that the ident circuit can be used when the VIF amplifier is not used (e.g. with built-in satellite tuners). The video ident circuit can also be used to identify the selected CBVS or Y/C signal. The switching between the 2 modes can be realized with bit VIM. The TDA9321H contains a group delay correction circuit which can be switched between the BG and a flat group delay response characteristic. This has the advantage that in multistandard receivers no compromise has to be made for the choice of the SAW filter. Both the input and output of the group delay correction circuit are externally available so that the sound trap can be connected between the VIF output and the group delay correction input. The output signal of the correction circuit can be supplied to the internal video processing circuit and to the external SCART plug. The IC has several (I2C-bus controlled) output ports which can be used to switch sound traps or other external components. When the VIF amplifier is not used the complete VIF amplifier can be switched off with bit IFO. Sound circuit The SIF amplifier is similar to the VIF amplifier and has a gain control range of approximately 66 dB. The AGC circuit is related to the SIF carrier levels (average level of AM or FM carriers) and ensures a constant signal amplitude to the AM demodulator and the QSS mixer. The single reference QSS mixer is realized by a multiplier. In this multiplier the SIF signal is converted to the intercarrier frequency by mixing it with the regenerated picture carrier from the VCO. The mixer output signal is supplied to the output via a high-pass filter for attenuation of the residual video signals. With this system a high performance hi-fi stereo sound processing can be achieved. The AM sound demodulator is realized by a multiplier. The modulated SIF signal is multiplied in phase with the limited SIF signal. The demodulator output signal is supplied to the output via a low-pass filter for attenuation of the carrier harmonics.
1998 Dec 16
Philips Semiconductors
Preliminary specication
TDA9321H
The luminance output signal which is derived from the incoming CVBS or Y/C signal can be varied in amplitude by means of a separate gain setting control via the I2C-bus control bits GAI1 and GAI0. The gain variation which can be realized with these bits is 1 to +2 dB. Colour decoder The colour decoder can decode PAL, NTSC and SECAM signals. The PAL/NTSC decoder contains an alignment-free crystal oscillator with 4 separate pins for crystal connection, a killer circuit and two colour difference demodulators. The 90 phase shift for the reference signal is produced internally. Because it is possible to connect 4 different crystals to the colour decoder, all colour standards can be decoded without external switching circuits. Which crystals are connected to the decoder must be indicated via the I2C-bus. The crystal connection pins which are not used must be left open-circuit. The horizontal oscillator is calibrated by means of the crystal frequency of the colour PLL. For a reliable calibration it is very important that the crystal indication bits XA to XD are not corrupted. For this reason bits XA to XD can be read in the output bytes so that the software can check the I2C-bus transmission. The IC contains an Automatic Colour Limiting (ACL) circuit which is switchable via the I2C-bus and prevents oversaturation occuring when signals with a high chrominance-to-burst ratio are received. The ACL circuit is designed such that it only reduces the chrominance signal and not the burst signal. This has the advantage that the colour sensitivity is not affected by this function. The ACL function is mainly intended for NTSC signals but it can also be used for PAL signals. For SECAM signals the ACL function should be switched off. The SECAM decoder contains an auto-calibrating PLL demodulator which has two references: the 4.43 MHz subcarrier frequency which is obtained from the crystal oscillator which is used to tune the PLL to the desired free-running frequency and the band gap reference to obtain the correct absolute value of the output signal. The VCO of the PLL is calibrated during each vertical blanking period, when the IC is in search or SECAM mode. The circuit can also decode the PALplus helper signal and can insert the various reference signals: set-ups and timing signals which are required for the PALplus decoder ICs. The baseband delay line (TDA4665 function) is integrated.
1998 Dec 16
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VIM VIDEO IDENTIFICATION ident
Philips Semiconductors
TDA9321H
to luminance/sync processing to chrominance processing
+
9
14 CVBSint 16 CVBS1 18 CVBS2 20 CVBS/Y3 21 C3 23 CVBS/Y4 24 C4 28 YCF 29 CCF
+ +
26 CVBSCF
34
32
CVBSPIP
CVBSTXT
MGR475
Preliminary specication
TDA9321H
Philips Semiconductors
Preliminary specication
TDA9321H
If required the IC can select the time constant depending on the noise content of the incoming video signal. The free-running frequency of the oscillator is determined by a digital control circuit which is locked to the reference signal of the colour decoder. When the IC is switched on the HA/CLP is suppressed and the oscillator is calibrated as soon as all subaddress bytes have been sent. When the frequency of the oscillator is correct the HA/CLP signal is switched on again. When the coincidence detector indicates an out-of-lock situation the calibration procedure is repeated. The VA pulse is obtained via a vertical count-down circuit. The count-down circuit has various windows depending on the incoming signal (50 or 60 Hz standard or non-standard). The count-down circuit can be forced in various modes via the I2C-bus. To obtain short switching times of the count-down circuit during a channel change the divider can be forced in the search window by means of bit NCIN. I2C-BUS SPECIFICATION The slave address of the IC is given in Table 1. Bit A1 is controlled via pin AS. When pin AS is connected to pin GND2 it is at logic 0 and when connected to VP2 it is at logic 1. When pin AS is left open-circuit it is connected to ground via an internal pull-up resistor. The circuit operates at clock frequencies of up to 400 kHz. Table 1 A6 1 Slave address bits A5 0 A4 0 A3 0 A2 1 A1 1/0 A0 1 R/W 1/0
Start-up procedure Read the status bytes until bit POR = 0 and send all subaddress bytes. It is advised to check the I2C-bus transmission by reading the output status bits SXA to SXD. This ensures a good operation of the calibration system of the horizontal oscillator. The horizontal output signal is switched on when the oscillator is calibrated. Each time before the data in the IC is refreshed, the status bytes must be read. If bit POR = 1, then the procedure mentioned above must be carried out to restart the IC. When this procedure is not carried out the horizontal frequency may be incorrect after power-up or after a power dip. The valid subaddresses are 00 to 0E. Subaddresses FE and FF are reserved for test purposes. Auto-increment mode is available for the subaddresses.
Philips Semiconductors
Preliminary specication
TDA9321H
FUNCTION Colour decoder 0 Colour decoder 1 Luminance Hue control Spare Synchronization 0 Synchronization 1 Spare Video switches 0 Video switches 1 RGB switch Output switches Vision IF Tuner takeover Adjustment IF-PLL INPUT CONTROL BITS Table 3
Table 4
Colour decoder mode DECODER MODE PAL/NTSC/SECAM PAL/NTSC PAL NTSC SECAM PAL/NTSC PAL NTSC PAL/NTSC PAL NTSC PAL/NTSC PAL/NTSC PAL NTSC XTAL A A A A A B B B C C C A/B/C/D D D D
XA to XD 0 1 Note
PAL/NTSC/SECAM A/B/C/D
1. When a comb filter is used, the various crystals must be connected to the IC as indicated in the pinning diagram. This is required because the ident system switches automatically to the comb filter when a signal is identified which can be combed (correct combination of colour standard and crystal frequency). For applications without comb filter only the crystal on pin XTALA is important (4.43 MHz); to pins XTALB to XTALD an arbitrary 3.5 MHz crystal can be connected.
1998 Dec 16
11
Philips Semiconductors
Preliminary specication
TDA9321H
Table 10 Chrominance band-pass centre frequency CB 0 1 fc 1.1 fc CENTRE FREQUENCY
Table 11 Bypass of chrominance baseband delay line BPS 0 1 active bypassed DELAY LINE MODE
Note 1. The black set-up will only be present in a norm sync condition. Table 6 HOB 0 1 1 1 Note 1. X = dont care. Table 7 HD 0 1 Note 1. Black and helper set-up will only be present in a norm sync condition. Table 8 FCO 0 1 Table 9 ACL 0 1 not active active not active active Automatic colour limiting COLOUR LIMITING Forced colour on MODE off on; PALplus mode with helper set-up 400 mV and black set-up 200 mV; note 1 PALplus helper demodulation active CONDITIONS Helper output blanking (PALplus/EDTV-2) HBC X(1) 0 1 1 SNR X(1) X(1) 0 1 off on off on BLANKING
Table 13 Y-delay adjustment; note 1 YD0 to YD3 YD3 YD2 YD1 YD0 Note 1. For an equal delay of the luminance and chrominance signal the delay must be set at a value of 280 ns (YD3 to YD0 = 1011). This is only valid for a CVBS signal without group delay distortions. Table 14 Forced eld frequency FORF FORS 0 0 1 1 Note 1. When switched to this mode the divider will directly switch to forced 60 Hz only. 0 1 0 1 FIELD FREQUENCY auto (60 Hz when line not synchronized) forced 60 Hz; note 1 keep last detected eld frequency auto (50 Hz when line not synchronized) Y-DELAY YD3 160 ns + YD2 160 ns + YD1 80 ns + YD0 40 ns
1998 Dec 16
12
Philips Semiconductors
Preliminary specication
TDA9321H
1. Except for PALplus with black set-up. Table 20 Condition of horizontal output MODE HO 0 1 CONDITIONS clamp pulse available on pin HA/CLP horizontal pulse available on pin HA/CLP
ident coupled to internal CVBS (pin 14) ident coupled to selected CVBS
Table 21 Enable Macrovision/subtitle gating EMG 0 1 disable gating enable gating MODE
Table 18 Video ident mode VID 0 1 not active VIDEO IDENT MODE 1 loop switched-on and off
Table 22 Vertical divider mode NCIN 0 1 VERTICAL DIVIDER MODE normal operation switched to search window
Table 23 Video switch control ECMB(1) 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 DEC3 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 DEC2 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 DEC1 0 1 1 0 0 1 1 0 1 0 1 1 0 1 0 1 DEC0 X(2) 0 1 0 1 0 1 0 0 X(2) 0 1 0 0 0 0 SELECTED SIGNAL CVBSint CVBS1 CVBS2 CVBS3 Y3/C3 CVBS4 Y4/C4 AUTO Y3/C3; note 3 AUTO Y4/C4; note 3 YCF/CCF YCF/CCF YCF/CCF YCF/CCF YCF/CCF AUTO COMB3; note 4 AUTO COMB4; note 4 SIGNAL TO COMB CVBSint CVBS1 CVBS2 CVBS3 Y3 + C3 CVBS4 Y4 + C4 CVBS3 or Y3 + C3 CVBS4 or Y4 + C4 CVBSint CVBS1 CVBS2 CVBS3 CVBS4 CVBS3 or Y3 + C3 CVBS4 or Y4 + C4
1998 Dec 16
13
Philips Semiconductors
Preliminary specication
TDA9321H
1. When bit ECMB = 1 the subcarrier frequency is present on pin 30. The YCF and CCF signals coming from the comb filter are only switched on when a signal is received that can be combed. 2. X = dont care. 3. AUTO YC means the decoder switches between CVBS and Y/C depending on the presence of the burst signal on these signals. 4. AUTO COMB means the decoder switches to Y/C mode if the burst is present on the C input and to the comb filter output if the burst is present on the CVBS signal. Table 24 Video switch outputs TXT2 PIP2 0 0 0 1 1 1 1 TXT1 PIP1 0 1 1 0 0 1 1 TXT0 PIP0 0 1 0 1 0 1 OUTPUT SIGNAL TXT OUTPUT SIGNAL PIP CVBSint CVBS1 CVBS2 CVBS3 Y3 + C3 CVBS4 Y4 + C4 Table 31 IF circuit not active Table 25 Enable YUV input (on RGB1 input) YUV 0 1 RGB1 input active YUV input active Table 32 Group delay correction Table 26 External RGB clamp mode ECL 0 1 MODE off; internal clamp pulse used on; external clamp pulse has to be supplied to pin HA/CLP GD 0 1 at according to BG standard GROUP DELAY CHARACTERISTIC MODE IFO 0 1 MODE normal operation of IF amplier IF amplier switched off Table 30 Fast lter IF-PLL FFI 0 1 CONDITIONS normal time constant fast time constant Table 29 Output switches OS0 and OS1 OS0; OS1 0 1 CONDITIONS output = LOW output = HIGH
Table 27 Enable fast blanking RGB1 IE1 0 1 not active active FAST BLANKING
Table 28 Enable fast blanking RGB2 IE2 0 1 not active active FAST BLANKING
1998 Dec 16
14
Philips Semiconductors
Preliminary specication
TDA9321H
Table 36 Search tuning mode STM 0 1 normal operation reduced sensitivity of video ident circuit MODE
Table 38 PLL demodulator frequency shift LFA 0 1 MODE normal IF frequency frequency shift for L standard
Table 39 Output status bits FUNCTION Output status bytes SUBADDRESS (HEX) 00 01 02 03 Note 1. X = dont care. OUTPUT CONTROL BITS Table 40 Power-on reset POR 0 1 normal power-down MODE Table 43 Phase 1 (1) lock indication SL 0 1 not locked locked INDICATION DATA BYTE D7 POR CD3 IN1 ID3 D6 X(1) CD2 IN2 ID2 D5 X(1) CD1 CMB ID1 D4 X(1) CD0 YC ID0 D3 SNR SXD S2A IFI D2 FSI SXC S2B PL D1 SL SXB S1A AFA D0 IVW SXA S1B AFB
Table 44 Condition vertical divider IVW 0 1 STANDARD VIDEO SIGNAL no standard video signal standard video signal in narrow window or standard TV norm (525 or 625 lines)
Table 41 Signal-to-noise ratio of sync signal SNR 0 1 SIGNAL-TO-NOISE RATIO S/N > 20 dB S/N < 20 dB
Table 45 Crystal indication (SXA to SXD) SXA to SXD 0 1 CONDITIONS no crystal connected crystal connected
1998 Dec 16
15
Philips Semiconductors
Preliminary specication
TDA9321H
XTAL A/B/C/D A A B B C C D D A
1. This mode is generated when trying (e.g. via software control) to force the decoder to a standard with a crystal which is not connected to the IC. Table 47 Indication RGB1/RGB2 insertion IN1; IN2 0 1 no insertion full insertion RGB INSERTION Table 51 Output video identication IFI 0 1 VIDEO SIGNAL no video signal identied video signal identied
Table 48 Condition YCF/CCF inputs from comb lter CMB 0 1 CONDITION YCF/CCF INPUTS not selected selected
Table 52 In-lock indication IF-PLL PL 0 1 PLL not locked PLL locked CONDITIONS
Table 49 Input signal condition; note 1 YC 0 1 Note 1. During the search mode for the colour system, bit YC will indicate logic 1. Table 50 Condition of AV1 and AV2 inputs S1A; S2A 0 0 1 S1B; S2B 0 1 0 CONDITIONS no external source external source with 4 : 3 input signal external source with 16 : 9 input signal CONDITIONS CVBS signal available Y/C signal available
Table 53 AFC output AFA 0 0 1 1 AFB 0 1 0 1 CONDITIONS outside window; too low outside window; too high in window; below reference in window; above reference
1998 Dec 16
16
Philips Semiconductors
Preliminary specication
TDA9321H
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP Tstg Tamb Tsld Tj Ves PARAMETER supply voltage on pins VP1 and VP2 storage temperature operating ambient temperature soldering temperature junction temperature electrostatic handling on all pins notes 1 and 2 notes 1 and 3 Notes 1. All pins are protected against ESD by means of internal clamping diodes. 2. Human Body Model (HBM): R = 1.5 k; C = 100 pF. 3. Machine Model (MM): R = 0 ; C = 200 pF. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 50 UNIT K/W for 5 s CONDITIONS 25 25 3000 300 MIN. MAX. 9.0 +150 +70 260 150 +3000 +300 V C C C C V V UNIT
QUALITY SPECIFICATION Quality specification in accordance with SNW-FQ-611E. Latch-up performance At an ambient temperature of 70 C all pins meet the following specification: Positive stress test: Itrigger 100 mA or Vpin 1.5 VP(max) Negative stress test: Itrigger 100 mA or Vpin 0.5 VP(max).
1998 Dec 16
17
Philips Semiconductors
Preliminary specication
TDA9321H
MAX.
UNIT
Supply (pins VP1 and VP2); note 1 VP IP Ptot supply voltage (pins VP1 and VP2) supply current (pins VP1 and VP2) total power dissipation 7.2 8.0 120 960 8.8 140 V mA mW
Vision IF circuit VISION IF AMPLIFIER INPUTS (PINS VIF1 AND VIF2) Vi(rms) input sensitivity (RMS value) note 2 fi(VIF) = 38.90 MHz fi(VIF) = 45.75 MHz fi(VIF) = 58.75 MHz Vi(max)(rms) Ri(dif) Ci(dif) Gv fPLL fcr(PLL) tacq(PLL) fVCO/T ftune(VCO) fDAC fshift Vo(z) maximum input signal (RMS value) differential input resistance differential input capacitance voltage gain control range note 3 note 3 150 70 35 35 40 200 2 3 75 2.7 3.7 29 5.5 100 100 100 80 V V V mV k pF dB
PLL DEMODULATOR (PLL FILTER ON PIN VIFPLL); note 4 PLL frequency range PLL catching range PLL acquisition time VCO frequency dependency with temperature VCO tuning frequency range frequency variation per step of the DAC (A0 to A6) frequency shift with bit LFA notes 5 and 6 via I2C-bus 32 2.0 3.0 23 60 3.3 20 20 4.2 33 106 MHz MHz ms K1 MHz kHz MHz
VIDEO AMPLIFIER OUTPUT (PIN VIFO); note 7 zero signal output level note 8 negative modulation positive modulation Vo(ts) Vo(w) Vo top-sync level white level difference in amplitude between negative and positive modulation video output impedance internal bias current of NPN emitter follower output transistor negative modulation positive modulation 4.6 1.9 1.9 4.4 4.7 2.0 2.0 4.5 0 4.8 2.1 2.1 4.6 15 V V V V %
Zo(v) Ibias(int)
1.0
50
mA
1998 Dec 16
18
Philips Semiconductors
Preliminary specication
TDA9321H
SYMBOL Isource(max) Bv(3dB) Gdif dif NLvid Vclamp Nclamp Nins dblue
PARAMETER maximum source current 3 dB bandwidth of demodulated output signal differential gain differential phase video non-linearity white spot clamping level noise inverter clamping level noise inverter insertion level (identical to black level) intermodulation at blue
CONDITIONS
MIN. 6 8
TYP. 5 10
MAX.
note 9 notes 6 and 9 note 10 note 11 note 11 notes 6 and 12 f = 0.92 or 1.1 MHz f = 2.66 or 3.3 MHz
1.5 2.5 5
60 60 56 60 56 49
66 66 62 66 60 53 5.5 2.5 40
65
dB dB dB dB dB dB mV mV dB
dyellow
intermodulation at yellow
weighted signal-to-noise ratio residual carrier signal 2nd harmonic of residual carrier signal power supply ripple rejection
1998 Dec 16
19
Philips Semiconductors
Preliminary specication
TDA9321H
SYMBOL
PARAMETER
CONDITIONS
MIN. 100
TYP.
MAX.
UNIT
V mV mA A dB
for complete tuner control 0.5 normal window mode enlarged window mode 65 195
VIDEO IDENTIFICATION OUTPUT (VIA I2C-BUS) td delay time for identication after the AGC has stabilized on a new transmitter 10 ms
Sound IF circuit SOUND IF AMPLIFIER (PINS SIF1 AND SIF2) Vi(rms) Vi(max)(rms) Ri(dif) Ci(dif) Gv ct(SIF-VIF) input sensitivity (RMS value) maximum input signal (RMS value) differential input resistance differential input capacitance voltage gain control range crosstalk between inputs SIF and VIF FM mode (3 dB) AM mode (3 dB) FM mode AM mode note 3 note 3 50 80 64 50 30 70 70 140 2 3 70 100 V V mV mV k pF dB dB
1998 Dec 16
20
Philips Semiconductors
Preliminary specication
TDA9321H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
General
Ro VO Ibias(int) Isink(max) Isource(max) output resistance DC output voltage internal bias current of emitter follower maximum AC and DC sink current maximum AC and DC source current 0.7 3.3 1.0 0.7 2.0 250 V mA mA mA
44/25
48/30
dB
45/44 46/45
51/50 52/51
dB dB
AM output signal
Vo(rms) THD B3dB S/NW output signal amplitude (RMS value) total harmonic distortion 3 dB bandwidth weighted signal-to-noise ratio 54% modulation 400 100 47 500 0.5 125 53 600 1.0 mV % kHz dB
1998 Dec 16
21
Philips Semiconductors
Preliminary specication
TDA9321H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Video switches and comb lter interface VIDEO SWITCHES FOR CVBS, Y AND C SIGNALS
1998 Dec 16
22
Philips Semiconductors
Preliminary specication
TDA9321H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Switching levels of SYS1 and SYS2 outputs (pins SYS1 and SYS2); note 21
VOH VOL Io(sink) Io(source) Vdet(int-ext) HIGH-level output voltage LOW-level output voltage output sink current output source current 4.0 2 2 5.0 0.1 2.2 5.5 0.4 2.4 V V mA mA
DETECTION OF STATUS LEVELS OF SCART PLUG PIN 8; note 22 detection voltage between internal and external (16 : 9) source detection voltage between external (16 : 9) and external (4 : 3) source input resistance 2.0 V
Vdet(ext-ext)
5.3
5.5
5.7
Ri
60
100
Chrominance and luminance lters and delay lines CHROMINANCE TRAP CIRCUIT; note 23 ftrap B3dB trap frequency during SECAM reception 3 dB bandwidth fSC = 3.58 MHz fSC = 4.43 MHz during SECAM reception CSR colour subcarrier rejection CHROMINANCE BAND-PASS CIRCUIT fc Qbp CLOCHE FILTER fc B centre frequency bandwidth 4.26 241 4.29 268 4.31 295 MHz kHz centre frequency band-pass quality factor bit CB = 0 bit CB = 1 fosc 1.1fosc 3 MHz MHz 2.6 3.2 2.9 26 fosc 1% 4.3 1.5% 2.8 3.4 3.1 3.0 3.6 3.3 MHz MHz MHz MHz MHz dB
1998 Dec 16
23
Philips Semiconductors
Preliminary specication
TDA9321H
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
delay time
bits YD3 to YD0 = 1011; note 6 crystal A crystal B, C or D 490 530 280 520 560 550 590 +160 ns ns ns
td(tr)
bandwidth
8 1.8
MHz
GROUP DELAY CORRECTION (PINS GDI AND GDO); note 24 Vi(GDI)(p-p) Ii(GDI) Vo(GDO)(p-p) Vo(GDO) Vo(GDO)/T Zo(GDO) input signal amplitude on pin GDI (peak-to-peak value) input current on pin GDI output signal amplitude on pin GDO (peak-to-peak value) output top-sync level on pin GDO top-sync level on pin GDO variation with temperature output impedance on pin GDO V A V V mV/K
Colour demodulation part CHROMINANCE AMPLIFIER CRACC Vo(CRACC) THck(on) hysck(off) ACC control range change in amplitude of the output signals over CRACC threshold colour killer ON hysteresis colour killer OFF colour killer from OFF to ON note 6 strong signal; S/N 40 dB noisy input signals ACL CIRCUIT; note 26 C/CACL ACL chrominance burst ratio when the ACL starts to operate 3.0 3 1 dB dB note 25 26 40 2 35 dB dB dB
REFERENCE PART
1998 Dec 16
24
Philips Semiconductors
Preliminary specication
TDA9321H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Oscillator
TCfosc fosc/VP temperature coefcient of oscillator frequency oscillator frequency variation with respect to the supply voltage minimum negative resistance maximum load capacitance note 6 VP = 8 V 10%; note 6 1 25 Hz/K Hz
40 0 0
1.0 15
k pF
HUE CONTROL; note 28 hue control range hue dependency with respect to the supply voltage hue dependency with temperature deg deg deg
General
V/V spread of signal amplitude ratio between standards note 6 1 +1 dB
PAL/NTSC demodulator
G(B-Y)(R-Y) gain between both demodulators (B Y) and (R Y) 3 dB bandwidth of demodulators residual carrier output (peak-to-peak value) note 29 f = fosc; (R Y) output f = fosc; (B Y) output f = 2fosc; (R Y) output f = 2fosc; (B Y) output RRH/2(p-p) Vo/T Vo/VP e H/2 ripple rejection (peak-to-peak value) output voltage variation with temperature output voltage variation with respect to the supply voltage phase error in the demodulated signals at (R Y) output note 6 note 6 note 6 1.60 1.78 1.96
B3dB(dem) Vo(rc)(p-p)
650 0.1
5 5 5 5 25 0.3 5
1998 Dec 16
25
Philips Semiconductors
Preliminary specication
TDA9321H
SYMBOL
PARAMETER
CONDITIONS
MIN. 77 3 85 3 4
TYP.
MAX.
UNIT
SECAM demodulator
fblos fblos/T fp fp/fz NL Vcal Vo Vr(clk)(p-p) td Vo black level offset frequency black level offset frequency variation with temperature pole frequency of de-emphasis ratio pole and zero frequency non-linearity calibration voltage 7 60 93 3 5 % V kHz Hz/K kHz
64.0 60
residual signal total harmonic distortion helper output timing to Y output offset voltage
36 36
10 5
dB dB ns mV
for demodulated mid grey to inserted mid grey level; mid grey line 23 to line 22
tW(su)(helper) td
helper set-up pulse width delay between mid sync of input bits YD3 to YD0 = 1011; and start of helper set-up note 30 delay between start of black only lines 22 and 23 set-up and start of helper set-up
s s s MHz
Bhelper(3dB)
1998 Dec 16
26
Philips Semiconductors
Preliminary specication
TDA9321H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
RGB switch and YUV switch RGB SWITCH (PINS RI1 TO BI1 AND RI2 TO BI2) Vi(p-p) Zsource(max) Vbl(int-ext) input signal amplitude (peak-to-peak value) maximum source impedance difference between black level of internal and external signals at the outputs input current delay difference between the three channels no clamping; note 3 note 6 0.7 1.0 1.0 10 V k mV
Ii td
0.1 0
1 20
A ns
YUV INPUTS (WHEN ACTIVATED) Vi(Y)(p-p) Vi(U)(p-p) Vi(V)(p-p) Zsource(max) Vbl(int-ext) Y input signal amplitude (peak-to-peak value) U input signal amplitude (peak-to-peak value) V input signal amplitude (peak-to-peak value) maximum source impedance difference between black level of internal and external signals at the outputs input current no clamping; note 3 1.0 1.33 1.05 1.0 10 V V V k mV
0.9
0.1
A V V V mA ns dB dB ns
FAST BLANKING (PINS RGB1 AND RGB2) input voltage maximum input pulse input current delay difference between blanking and RGB signals suppression of internal YUV signals suppression of external RGB signals delay between blanking input and YUV outputs note 6 data insertion; fi = 0 to 5 MHz; note 6 no data insertion; fi = 0 to 5 MHz; note 6 no data insertion data insertion 0.4 3.5 0.2 tbf tbf
55 55
LUMINANCE OUTPUT (PIN YO); note 31 Vo(p-p) Vo Vbl(YUV-RGB) output signal amplitude (peak-to-peak value) output voltage during PALplus difference in black level between YUV and RGB mode black-to-white black-to-white 1.0 0.8 10 V V mV
1998 Dec 16
27
Philips Semiconductors
Preliminary specication
TDA9321H
PARAMETER output impedance output DC voltage level 3 dB bandwidth of the RGB switch circuit signal-to-noise ratio black set-up amplitude black set-up pulse width
MIN. 2.8 7
UNIT V MHz dB mV s s mV
delay between mid sync at input note 30 and black set-up offset voltage gain from internal Y/CVBS to YO Ybl to re-inserted black bit MACP = 1 or bit HD = 1
UO AND VO SIGNAL OUTPUTS (PINS UO AND VO) Vo(VO)(p-p) Vo(UO)(p-p) Zo VO Vbl(YUV-RGB) output voltage on pin VO (peak-to-peak value) output voltage on pin UO (peak-to-peak value) output impedance output DC voltage level difference in black level between YUV and RGB mode standard EBU colour bar standard EBU colour bar 0.88 1.12 2.2 1.05 1.33 2.4 1.25 1.58 250 2.6 10 V V V mV
COLOUR MATRIX FROM RGB TO YUV G gain from RI to YO from GI to YO from BI to YO from RI to UO from GI to UO from BI to UO from RI to VO from GI to VO from BI to VO Horizontal and vertical synchronization SYNC VIDEO INPUTS Vsync SLhor SLvert sync pulse amplitude slicing level for horizontal sync slicing level for vertical sync note 3 note 32 note 32 35 50 35 300 55 40 350 60 45 mV % % 0.40 0.79 0.15 0.40 0.79 1.19 0.94 0.79 0.15 0.43 0.84 0.16 0.43 0.84 1.27 1.00 0.84 0.16 0.46 0.90 0.17 0.46 0.90 1.35 1.07 0.90 0.17
1998 Dec 16
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Philips Semiconductors
Preliminary specication
TDA9321H
PARAMETER
CONDITIONS
MIN.
TYP. 2
MAX.
UNIT
free-running frequency spread on free-running frequency frequency dependency with respect to the supply voltage frequency variation with temperature VP = 8.0 V 10%; note 6 Tamb = 0 to 70 C; note 6
15625 0.2
Hz % % Hz
0.5 80
FIRST CONTROL LOOP (PIN PH1LF); note 33 fhr(PLL) fcr(PLL) S/N PLL holding range PLL catching range signal-to-noise ratio note 6 for the video input signal at which the time constant is switched in automatic mode; 3 0.6 15 0.9 0.9 17 1.2 19 kHz kHz dB
hyssw
4 5
dB ns
td2
delay between mid sync of input note 30 and start CLP pulse
3.0
3.2
3.4
1998 Dec 16
29
Philips Semiconductors
Preliminary specication
TDA9321H
CONDITIONS
MIN. 3 45 488 50 60
TYP. 10
MAX.
UNIT mV M
VERTICAL OSCILLATOR; note 34 free-running frequency frequency locking range divider ratio locking range not locked 50 Hz mode 60 Hz mode Hz Hz Hz lines lines/ frame
64.5 722
625/525
VERTICAL PULSE OUTPUT (PIN VA) VOH VOL Io(sink) Io(source) tW td HIGH-level output voltage LOW-level output voltage output sink current output source current pulse width delay between start of vertical sync of input and positive edge of vertical pulse on pin VA output impedance fVA = 50 Hz fVA = 60 Hz note 35 Io(source) = 2 mA Io(sink) = 2 mA 4.0 2 2 5.0 0.2 2.5 3.0 37.7 5.5 0.4 V V mA mA lines lines s
Zo
bit ECL = 1
General
Vz Io(sink) Vo Io(source) tW(h) td zero level voltage output sink current 0 2.2 0.5 0.5 1.0 2.8 V mA
Horizontal/vertical blanking
output voltage level output source current horizontal blanking pulse width delay between start horizontal blanking and start clamping pulse 2.5 0.7 10 6.4 V mA s s
Clamping pulse
Vo Io(source) tW output voltage level output source current pulse width 4.2 4.5 0.7 3.6 4.8 V mA s
1998 Dec 16
30
Philips Semiconductors
Preliminary specication
TDA9321H
SYMBOL td
PARAMETER
CONDITIONS
MIN. 3.0
TYP. 3.2
MAX. 3.4
UNIT s
delay between mid sync of input note 30 and start of clamping pulse
I2C-BUS CONTROL SCL AND SDA INPUTS/OUTPUTS (PINS SCL AND SDA) Vi VIL VIH IIL IIH VOL(SDA) input voltage range LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level output voltage on pin SDA VIL = 0 V VIH = 5.5 V IOL(SDA) = 3 mA 0 3.5 5.5 1.5 10 10 0.4 V V V A A V
SW0 AND SW1 OUTPUTS (PINS SW0 AND SW1); note 36 VOH VOL IO(sink) IO(source) HIGH-level output voltage LOW-level output voltage output sink current output source current 4.0 2 2 5.0 0.2 5.5 0.4 V V mA mA
Notes to the characteristics 1. The two supply pins VP1 and VP2 must be decoupled separately but they must be connected to a single power supply to avoid too big differences between them. 2. On set AGC. 3. This parameter is not tested during production and is just given as application information for the designer of the television receiver. 4. Loop filter bandwidth Blpf = 60 kHz (natural frequency fn = 15 kHz; damping factor d = 2; calculated with top sync level as fPLL input signal level). LC-VCO circuit between pins 7 and 8: Q0 = 60; Cint = 30 pF. 5. The optimum temperature stability of the PLL can be obtained when a TOKO coil as given in Table 55 is applied. 6. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 7. Measured at 10 mV (RMS value) top sync input signal. 8. So called projected zero point, i.e. with switched demodulator. 9. Measured in accordance with the test line given in Fig.5. For the differential phase test the peak white setting is reduced to 87%. The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and smallest value relative to the subcarrier amplitude at blanking level. The differential phase is defined as the difference in degrees between the largest and smallest phase angle. 10. This figure is valid for the complete video signal amplitude (peak white-to-black). See Fig.6. 11. The noise inverter is only active in the strong signal mode (no noise detected in the incoming signal).
1998 Dec 16
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Philips Semiconductors
Preliminary specication
TDA9321H
12. The input conditions and test set-up are given in Figs 8 and 9. The figures are measured with an input signal of 10 mV (RMS value). The intermodulation figures are defined: V 0 at 3.58 MHz 0.92 = 20 log -------------------------------------- + 3.6 dB ; 0.92 value at 0.92 MHz referenced to black or white signal; V 0 at 0.92 MHz V 0 at 3.58 MHz 2.76 = 20 log -------------------------------------- ; 2.76 value at 2.76 MHz referenced to colour carrier. V 0 at 2.76 MHz 13. Measured at an input signal of 10 mV (RMS value). The S/N is the ratio of black-to-white amplitude with respect to the black level noise voltage (RMS value). B = 5 MHz. Weighted in accordance with CCIR 567. 14. The AGC response time also depends on the acquisition time of the PLL demodulator. The values given are valid when the PLL is in lock. 15. The AFC control voltage is obtained from the control voltage of the VCO of the PLL demodulator. The tuning information is supplied to the tuning system via the I2C-bus. Two bits are reserved for this function. The AFC value is valid only when bit PL = 1. 16. The weighted S/N ratio is measured under the following conditions: a) The VIF modulator must meet the following specifications: Incidental phase modulation for black-to-white jumps less than 0.5 degrees. QSS AF performance, measured with the television-demodulator AMF2 (audio output, weighted S/N ratio) better than 60 dB (deviation 27 kHz) for 6 kHz sine wave black-to-white modulation. Picture-to-sound carrier ratio: PC/SC1 = 13 dB (transmitter). b) The measurements must be carried out with the Siemens SAW filters G3962 for VIF and G9350 for SIF. Input level for SIF at 10 mV (RMS value) with 27 kHz deviation. c) The PC/SC ratio at the VIF input is calculated as the addition of the TV transmitter ratio and the SAW filter PC/SC ratio. This PC/SC ratio is necessary to achieve the S/NW values as indicated. 17. Signal with negative-going sync. Amplitude includes sync pulse amplitude. 18. Indicated is a signal for a colour bar with 75% saturation (chrominance to burst amplitude ratio = 2.2 : 1). 19. When a signal is identified which can be combed (correct combination of colour standard and reference crystal) the comb filter is switched to that mode via pins 25 and 27 and then the filter is activated by switching on the reference carrier signal and connecting the output signals of the comb filter (pins 28 and 29) to the video processing circuits. 20. The subcarrier output signal can be used as a reference signal for external comb filter ICs (e.g. SAA4961). When bit ECMB = 0 the subcarrier signal is suppressed and the DC level is LOW. When bit ECMB = 1 the output level is HIGH and the subcarrier signal is present. 21. The outputs SYS1 and SYS2 can be used to switch the comb filter to the different colour standards (e.g. PAL-M, PAL-N, PAL-B/G and NTSC-M) and are controlled by the colour decoder identification circuit. The setting of the outputs for the various standards is given in Table 56. 22. For the detection of the status of the incoming SCART signal a voltage divider with a ratio of 2 : 3 has to be connected between pin 8 of the SCART plug and the detection input. The impedance of the voltage divider should not be too high-ohmic because of the input impedance of 100 k. 23. When the decoder is forced to a fixed subcarrier frequency (via bits XA to XD or bit CM) the chrominance trap is always switched on, also when no colour signal is identified. When 2 crystals are active the chrominance trap is switched off if no colour signal is identified. 24. The typical group delay characteristic for the B/G standard is given in Fig.7. 25. At a chrominance input voltage of 660 mV (p-p) [colour bar with 75% saturation i.e. burst signal amplitude 300 mV (p-p)] the dynamic range of the ACC is +6 and 20 dB. 26. The ACL function can be activated by bit ACL. The ACL circuit reduces the gain of the chrominance amplifier for input signals with a C/CACL which exceeds a value of 3.0. 1998 Dec 16 32
Philips Semiconductors
Preliminary specication
TDA9321H
27. All frequency variations are referenced to 3.58 or 4.43 MHz carrier frequency. All oscillator specifications are measured with the Philips crystal series 9922 520 with a series capacitance Cs = 18 pF. The oscillator circuit is rather insensitive to the spurious responses of the crystal. As long as the resonance resistance of the third overtone is higher than that of the fundamental frequency the oscillator will operate at the correct frequency. The typical crystal parameters for the crystal series are: a) Load resonance frequencies fL: 4.433619, 3.579545, 3.582056 and 3.575611 MHz; Cs = 20 pF. b) Motional capacitance Cmot = 20.6 fF (4.43 MHz crystal) or Cmot = 14.7 fF (3.58 MHz crystal). c) Parallel capacitance Cp = 5.0 pF. The minimum detuning range can only be specified if both the IC and the crystal tolerances are known and therefore the figures regarding catching range are only valid for the specified crystal series. In this figure tolerances of the crystal with respect to the nominal frequency, motional capacitance and ageing have been taken into account and have been counted for gaussic addition. Whenever different typical crystal parameters are used the following equation might be helpful for calculating the impact on the tuning capabilities: C mot Detuning range = ------------------------ Cp 2 1 + ------ Cs The resulting detuning range should be corrected for temperature shift and supply voltage deviation of both the IC and the crystal. To guarantee a catching range of 300 Hz on 4.43 MHz the minimum motional capacitance of the crystal must have a value 13.2 fF or higher. For a catching range of 250 Hz with the 3.58 MHz crystal the minimum motional capacitance must have a value of 9 fF. The actual series capacitance in the application should be Cs = 18 pF to account for parasitic capacitances on-chip and off-chip. 28. The hue control is active for NTSC on the demodulated colour difference signals and for PALplus on the demodulated helper signal. 29. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance band-pass filter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz. 30. This delay is partially caused by the low-pass filter at the sync separator input. 31. The internal luminance signal (signal which is derived from the incoming CVBS or Y/C signals) has a separate gain control setting (controlled by the I2C-bus bits GAI1 and GAI0 and with a gain variation between 1 and +2 dB) which can be used to get an optimal input signal amplitude for the feature box. 32. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing level and the black level (back porch). When the amplitude of the sync pulse exceeds the value of 350 mV the sync separator will slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is 4 V (peak-to-peak value). 33. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is switched depending on the input signal condition and the condition of the I2C-bus. Therefore the circuit contains a noise detector and the time constant is switched to the slow mode when too much noise is present in the signal. In the fast mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to head-switching of the VCR are corrected as soon as possible. Switching between the two modes can be automatic or overruled by the I2C-bus. The circuit contains a video identification circuit which is independent of the first control loop. This identification circuit can be used to close or open the first control loop when a video signal is present or not present on the input. This enables a stable On Screen Display (OSD) when just noise is present at the input. The coupling of the video identification circuit with the first control loop can be revoked via the I2C-bus.
1998 Dec 16
33
Philips Semiconductors
Preliminary specication
TDA9321H
To prevent the horizontal synchronization being disturbed by anti copy signals such as Macrovision the phase detector is gated during the vertical retrace period from line 11 to 17 (60 Hz signal) or from line 11 to 22 (50 Hz signal) so that pulses during scan have no effect on the output voltage. The width of the gate pulse is approximately 22 s. During weak signal conditions (noise detector active) the gating is active during the complete scan period and the width of the gate pulse is reduced to 5.7 s so that the effect of noise is reduced to a minimum. The output current of the phase detector in the various conditions is shown in Table 57. 34. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. This divider circuit has 3 modes of operation: a) Search mode large window. This mode is switched on when the circuit is not synchronized or when a non-standard signal [number of lines per frame outside the range between 311 and 314 (50 Hz mode) or between 261 and 264 (60 Hz mode)] is received. In the search mode the divider can be triggered between line 244 and line 361 (approximately 43.3 to 64.5 Hz). b) Standard mode narrow window. This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window. c) Standard TV-norm [divider ratio 525 (60 Hz) or 625 (50 Hz)]. When the system is switched to the narrow window a check is performed to establish whether the incoming vertical sync pulses are in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical sync pulse is missing. When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window. The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the divider is required during channel-switching the system can be forced to the search window by means of bit NCIN in subaddress 06. 35. The delay between the positive edge of VA and the positive edge of CLP ( negative edge of HA) after VA is 32.0 s for field 1 and 0 s for field 2. Especially for PALplus signals the regenerated VA pulses must have a fixed and known phase relation to the undisturbed VA pulses of the incoming video signal. This relationship must remain correct as long as the vertical divider is in the standard mode (indirect sync mode). Therefore the coincidence window used here must be a half line window. With a well defined phase relationship of the generated VA pulses to the generated HA pulses a correct field identification and all the required timing signals referring to a certain line in each frame can be generated externally in the PALplus decoder environment. 36. Pins 19 and 22 are for general purpose outputs that can be used to switch external circuits e.g. sound traps, etc. They are controlled via the I2C-bus by bits OS0 (pin 19) and OS1 (pin 22).
1998 Dec 16
34
Philips Semiconductors
Preliminary specication
TDA9321H
Table 56 Switching conditions of pins SYS1 and SYS2 COLOUR STANDARD PAL-M PAL-B, G, H, D and I NTSC-M PAL-N SYS1 LOW LOW HIGH HIGH SYS2 LOW HIGH LOW HIGH ACTIVE CRYSTAL C A D B
Table 57 Output current of the phase detector in the various conditions I2C-BUS COMMANDS VID 0 Note 1. When the Macrovision is active a gating is present during a part of the vertical retrace, pulse width 22 s. In the other gating conditions the pulse width is 5.7 s and the gating is continuous. POC 0 0 0 0 0 0 0 0 1 FOA 0 0 0 0 0 1 1 1 FOB 0 0 0 1 1 0 0 1 IC CONDITIONS IDENT yes yes yes yes yes yes yes no COIN yes yes no yes no yes yes NOISE no yes no yes SCAN 180 30 180 30 180 180 30 180 6 -1 CURRENT/MODE V-RETR 270 30 270 30 270 270 30 270 6 GATING no(1) yes no yes no yes yes no no MODE auto auto auto slow slow fast slow fast OSD off
1998 Dec 16
35
Philips Semiconductors
Preliminary specication
TDA9321H
MLA739
50 (deg) 30
10
10
30
50
10
20
30 40 DAC (HEX)
MBC212
16 %
100% 92%
1998 Dec 16
36
Philips Semiconductors
Preliminary specication
TDA9321H
MBC211
MGR476
handbook, halfpage
500
td(g) (ns)
400
300
200
100
0 0 1 2 3 4 f (MHz) 5
1998 Dec 16
37
Philips Semiconductors
Preliminary specication
TDA9321H
SC CC BLUE
PC
SC CC YELLOW
PC
MBC213
SC = sound carrier, with respect to top sync level. CC = colour carrier, with respect to top sync level. PC = picture carrier, with respect to top sync level.
PC
SC
ATTENUATOR
TEST CIRCUIT
SPECTRUM ANALYZER
CC
1998 Dec 16
38
Philips Semiconductors
Preliminary specication
TDA9321H
TAGC 62 36 37 38 39 VIF1 2 IF SAW FILTER VIF2 3 40 41 42 43 49 50 51 YO UO VO YIN UIN VIN 30 31 32 33 28 27 26 35 36 37 38 40 41 42 43 RO GO BO BCL BLKIN VDOA VDOB EWO HOUT HFB
16 15 18 17 20 21 23 24 34 32 26 CVBSCF 28 YCF
TDA9321H
FEATURE BOX
TDA9330H
44 1
HA 60 61 29 CCF VA
HD VD
2 24 23 8 13
MGR477
CVBSTXT CVBSPIP
COMB FILTER
1998 Dec 16
39
Philips Semiconductors
Preliminary specication
TDA9321H
SOT319-2
y X
51 52
33 32 ZE
e E HE A A2 A1 (A 3) Lp bp 64 1 w M D HD ZD B v M B 19 v M A 20 detail X L
pin 1 index
wM
bp
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
1998 Dec 16
40
Philips Semiconductors
Preliminary specication
TDA9321H
The footprint must incorporate solder thieves at the downstream end. For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1998 Dec 16
41
Philips Semiconductors
Preliminary specication
TDA9321H
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1998 Dec 16
42
Philips Semiconductors
Preliminary specication
TDA9321H
This data sheet contains target or goal specications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains nal product specications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specication is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specication. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1998 Dec 16
43
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
545104/750/01/pp44