QUESTION BANK

JAMES COLLEGE OF ENGINEERING & TECHNOLOGY, NAVALCAUD

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Subject Name: VLSI DESIGN Year / Sem : Third / Sixth UNIT I CMOS TECHNOLGY PART - A ( 2 marks)
1. What are the different MOS layers? 2. What are the two types of layout design rules? 3. Define rise time and fall time. 4. What is a pull down device? 5. What is mean by Epitaxy? 6. What is isolation? 7. What are the steps involved in manufacturing of IC? 8. What is the special feature of Twin-Tub process? 9. Draw the Isotropic etching process diagram. 10. What is silicide? 11. What is AOI? 12. Define fabrication process. 13. Draw the graph of n-MOS depletion mode. 14. Draw the Dc transfer characteristics curve. 11. Define noise margin. 15. Draw the symbol for tristate inverter. 16. Differentiate the nMOS from pMOS. 17. What are all the factors can be extracted from the Vth equation. 18. Define the Power dissipation 19. Give the advantages and disadvantages of SOI. 20.What are the different modes fo operation in MOSFET?

Subject code: EC 64 Department : ECE

PART-B (16&8 Marks)

1. Differentiate the p-well CMOS process from n-well CMOS process. Explain the n-well CMOS process to fabricate the n-switches. 2. Discuss the steps involved in IC fabrication process. 3. Describe n-well process in detail. 4. Explain the DC characteristics of CMOS inverter with neat sketch. 5. Explain channel length modulation and body effect. 6. Explain the different regions of operation in a MOS transistor. 7. Write a note on MOS models. 8. List out the layout design rule. And draw the physical layout for one basic gate and two universal gates. 9. Explain the n MOS and p MOS enhancement transistor with its physical structure. 10. Explain the complimentary CMOS inverter DC characteristics.