Sommaire I. Register ...............................................................................................................2 III. Comparateur 4 bits.........................................................................................5 IV. Comparateur 4 bits-test bench ......................................................................7 V. Compateur 8bits.................................................................................................9 VI.

Compateur 8bits-test bench .........................................................................12 VII. Compteur modulo 16 ...................................................................................14 VIII. Competeur 16 test bench ..........................................................................15 IX. Compteur_coparateur ..................................................................................19

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I. Register
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY reg IS PORT(clk,rst: in std_logic; datain : in std_logic_vector(7 downto 0); dataout : out std_logic_vector(7 downto 0)); END reg; ARCHITECTURE RTL OF reg IS BEGIN PROCESS(clk,rst) BEGIN IF (rst ='0') THEN dataout<= (OTHERS =>'0'); ELSIF(clk'event AND CLK='1')THEN dataout<= datain; END IF; END PROCESS; END RTL; --rest asynchrone --

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II.

Register- test bench

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY reg_tb IS END reg_tb; ARCHITECTURE RTL OF reg_tb IS COMPONENT reg is PORT(rst : in std_logic; clk : in std_logic; datain : in std_logic_vector(7 downto 0); dataout : out std_logic_vector(7 downto 0)); END COMPONENT; SIGNAL clk,rst : std_logic; SIGNAL datain : std_logic_vector(7 downto 0); SIGNAL dataout : std_logic_vector(7 downto 0); BEGIN U1: reg port map ( clk => clk, rst => rst, datain => datain, dataout => dataout); -- Attention virgule , pas de point virgule --

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PROCESS BEGIN clk <= '1'; WAIT FOR 10 ns; clk <= '0'; WAIT for 10 ns; END PROCESS; PROCESS BEGIN rst <= '0'; WAIT FOR 10 ns; rst <= '1'; WAIT for 10 ns; END PROCESS; PROCESS BEGIN datain <= "10111110"; WAIT FOR 50ns; datain <= "00111111" ; WAIT for 50 ns; END PROCESS;
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III. Comparateur 4 bits

LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY comp_4_bits IS PORT( A:in std_logic_vector(3 downto 0); B:in std_logic_vector(3 downto 0); sup:out std_logic; ega:out std_logic; inf:out std_logic ); END comp_4_bits; ARCHITECTURE RTL of comp_4_bits is BEGIN PROCESS(A,B) BEGIN IF (A>B) THEN SUP<='1'; ega<='0'; inf<='0';

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ELSIF (A=B) THEN SUP<='0'; ega<='1'; inf<='0'; ELSIF (A<B) THEN SUP<='0'; ega<='0'; inf<='1'; END IF; END PROCESS; END RTL;

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IV. Comparateur 4 bits-test bench

LIBRARY ieee; USE ieee.std_logic_1164.all; Entity comp_tb is END comp_tb; ARCHITECTURE RTL OF comp_tb IS COMPONENT comp_4_bits PORT ( A:in std_logic_vector(3 downto 0); B:in std_logic_vector(3 downto 0); sup:out std_logic; ega:out std_logic; inf:out std_logic END COMPONENT; SIGNAL A: std_logic_vector(3 downto 0); SIGNAL B: std_logic_vector(3 downto 0); SIGNAL sup: std_logic; SIGNAL ega: std_logic; SIGNAL inf: std_logic; BEGIN U1: ABDERRAHMAN BEKKALI comp_4_bits port map( &ABDELLAOUI ALAOUI El- Arbi ); --**attention il faut garder le meme nom de la synthse**--tout en majiscule--

A=>A, B=>B, sup=>sup, ega=>ega, inf=>inf); PROCESS BEGIN A<="1111"; WAIT FOR 10 ns; A<="1000"; WAIT FOR 20 ns; A<="1011"; WAIT FOR 30 ns; END PROCESS; PROCESS BEGIN B<="1001"; WAIT FOR 10 ns; B<="1000"; WAIT FOR 20 ns;

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B<="1100"; WAIT FOR 30 ns; END PROCESS; END RTL;

V. Compateur 8bits

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Programme
LIBRARY ieee; USE ieee.std_logic_1164.all; Entity comp_8bits is PORT( A_TOP:in std_logic_vector(7 downto 0); B_TOP:in std_logic_vector(7 downto 0); sup_TOP:out std_logic; ega_TOP:out std_logic; inf_TOP:out std_logic ); END comp_8bits; ARCHITECTURE RTL of comp_8bits is COMPONENT comp_4_bits --**attention il faut garder le meme nom de la synthse**---tout en majiscule--

PORT (A:in std_logic_vector(3 downto 0); B:in std_logic_vector(3 downto 0); sup:out std_logic; ega:out std_logic; inf:out std_logic ); END COMPONENT;

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SIGNAL sig1: std_logic; SIGNAL sig2: std_logic; SIGNAL sup1: std_logic; SIGNAL ega1: std_logic; SIGNAL inf1: std_logic; SIGNAL sup2: std_logic; SIGNAL ega2: std_logic; SIGNAL inf2: std_logic; BEGIN U1: comp_4_bits port map( A=>A_TOP(7 downto 4), B=>B_TOP(7 downto 4), sup => sup1, ega => ega1, inf => inf1); U2: comp_4_bits port map( A=>A_TOP(3 downto 0), B=>B_TOP(3 downto 0), sup => sup2, ega => ega2, inf => inf2); ega_TOP <= ega1 and ega2; inf_TOP <= inf1 or (ega1 and inf2); sup_TOP <= sup1 or (ega1 and sup2); END RTL;
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--***pour comprer MSB**--

--***pour comprer LSB**--

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VI. Compateur 8bits-test bench

LIBRARY ieee; USE ieee.std_logic_1164.all; Entity comp8b_tb is END comp8b_tb; ARCHITECTURE RTL of comp8b_tb is COMPONENT comp_8bits PORT (A_TOP:in std_logic_vector(7 downto 0); B_TOP:in std_logic_vector(7 downto 0); sup_TOP:out std_logic; ega_TOP:out std_logic; inf_TOP:out std_logic END COMPONENT; SIGNAL A: std_logic_vector(3 downto 0); SIGNAL B: std_logic_vector(3 downto 0); SIGNAL sup: std_logic; SIGNAL ega: std_logic; SIGNAL inf: std_logic; BEGIN U1: comp_8bits port map( A_TOP=>A_TOP, B=>B, A_TOP=>A,
BEKKALI ABDERRAHMAN &ABDELLAOUI ALAOUI El- Arbi

);

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B_TOP=>B_TOP, sup_TOP=>sup_TOP, ega_TOP=>ega_TOP, inf_TOP=>inf_TOP); PROCESS BEGIN A<="00000001"; WAIT FOR 10 ns; A<="00000000"; WAIT FOR 20 ns; A<="00000010"; WAIT FOR 30 ns; END PROCESS; PROCESS BEGIN B<="00000111"; WAIT FOR 10 ns; B<="00000000"; WAIT FOR 20 ns; B<="00000101"; WAIT FOR 30 ns; END PROCESS; END RTL;

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VII. Compteur modulo 16

Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; entity compteur16 is port (clear : in std_logic; clk : in std_logic; load : in std_logic; up : in std_logic;

precedent : in std_logic_vector (3 downto 0); sortie : out std_logic_vector (3 downto 0)); end compteur16; architecture rtl of compteur16 is signal sig_1: std_logic_vector (3 downto 0); begin process (clear,clk) begin if clear ='1' then sig_1 <= "0000"; elsif (clk ='1' and clk'event) then if (load ='1') then sig_1 <= precedent; elsif (up ='1') then
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sig_1 <= sig_1 + 1; else sig_1<= sig_1 - 1 ; end if; end if; end process; sortie <= sig_1; end rtl;

VIII. Competeur 16 test bench

Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; entity compteur_tb is end compteur_tb; architecture rtl of compteur_tb is component compteur16 is port (clear : in std_logic; clk : in std_logic; load : in std_logic; up : in std_logic;

precedent : in std_logic_vector (3 downto 0);

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sortie : out std_logic_vector (3 downto 0)); end component; signal clear:std_logic; signal clk :std_logic; signal load :std_logic; signal up :std_logic; signal precedent:std_logic_vector (3 downto 0); signal sortie :std_logic_vector (3 downto 0); begin u1:compteur port map( clk => clk,--c fait-clear => clear,--c fait-load =>load, up=>up, sortie=>sortie, precedent=>precedent); PROCESS begin clk<='1'; wait for 10 ns; clk<='0'; wait for 10 ns; END PROCESS;

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PROCESS begin clear<='0'; wait for 50 ns; clear<='1'; wait for 50 ns; END PROCESS; PROCESS begin load<='1'; wait for 10 ns; load<='0'; wait for 10 ns; END PROCESS; PROCESS begin up<='1'; wait for 10 ns; up<='0'; wait for 10 ns; END PROCESS; PROCESS begin

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precedent<="1100"; wait for 20 ns; precedent<="0001"; END PROCESS; end rtl;

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IX. Compteur_coparateur
Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; entity compt_compa is port (data : in std_logic_vector (7 downto 0); ABCD : out std_logic_vector (3 downto 0)); end compt_compa; architecture rtl of compt_compa is begin COMPONENT reg PORT (clk,rst: in std_logic; datain : in std_logic_vector(7 downto 0); dataout : out std_logic_vector(7 downto 0)); END COMPONENT; COMPONENT comp_8bits PORT (A_TOP:in std_logic_vector(7 downto 0); B_TOP:in std_logic_vector(7 downto 0); sup_TOP:out std_logic; ega_TOP:out std_logic; inf_TOP:out std_logic); END COMPONENT;

BEKKALI ABDERRAHMAN &ABDELLAOUI ALAOUI El- Arbi

elsif (clk ='1' and clk'eif (load ='1') then sig_1 <= precedent;

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COMPONENT compteur16 PORT (clear : in std_logic; clk : in std_logic; load : in std_logic; up : in std_logic;

precedent : in std_logic_vector (3 downto 0); sortie : out std_logic_vector (3 downto 0)); END COMPONENT;

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