IVA 2.

2Subsystem
TMS320DM64x+DSP
ImagingVideoand
AudioProcessor
32K/32KL1$
48KL1DRAM
64KL2$
32KL2RAM
16KL2ROM
VideoHardware
Accelerators
64 32
Async
64 32
64 64
Async
64 64
L2$
256K
MPU
Subsystem
ARMCortex-
A8
TM
Core
16K/16KL1$
POWERVR
SGX
Graphics
Accelerator
(3530only)
TM
32 32
32
Channel
System
DMA
32 32
Parallel TV
Amp
LCDPanel
CVBS
or
S-Video
DualOutput3-Layer
DisplayProcessor
(1xGraphics,2xVideo)
TemporalDithering
SDTV QCIFSupport
32
Camera
ISP
Image
Capture
Hardware
Image
Pipeline
and
Preview
Camera
(Parallel)
64
HSUSB
Host
(with
USB
TTL)
HS
USB
OTG
32
L3InterconnectNetwork-Hierarchial,Performance,andPowerDriven
64K
On-Chip
RAM
2KB
Public/
62KB
Secure
32
112K
On-Chip
ROM
80KB
Secure/
32KB
BOOT
32
SMS:
SDRAM
Memory
Scheduler/
Rotation
64
SDRC:
SDRAM
Memory
Controller
L4Interconnect
32
System
Controls
PRCM
2xSmartReflex
TM
Control
Module
External
Peripherals
Interfaces
Peripherals:
3xUART,3xHigh-SpeedI2C,
5xMcBSP
(2xwithSidetone/AudioBuffer)
4xMcSPI,6xGPIO,
3xHigh-SpeedMMC/SDIO,
HDQ/1Wire,
2xMailboxes
12xGPTimers,2xWDT,
32KSyncTimer
GPMC:
General
Purpose
Memory
Controller
NAND/
NOR
Flash,
SRAM
32
Emulation
Debug:SDTI,ETM,JTAG,
Coresight
TM
DAP
Externaland
StackedMemories
32
OMAP ApplicationsProcessor

































































2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
A
B
C
D
E
F
G
H
J
K
L
M
N
P
T
R
U
V
W
Y
AA
AB
AC
24
25
26
27
28
AD
AE
AF
AG
AH
1
030-001








A
C
D
E
G
K
L
M
N
P
T
R
U
V
W
Y
AB
B
F
H
J
AA
AC
22
21
20 18
17
16
15 13
12 10
9
8
7
6
5
4
3
2
1 11
14
19 23
030-002





AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26




AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1




AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24









A
9
sdrc_d7
8
vdds_mem
7 6 5 4
sdrc_a0
3 2
pop_a2_a2
1
B vdds_mem sdrc_a1 vss
C sdrc_d4
D sdrc_a10
E
F
G
H
J
K
sdrc_d5 sdrc_dqs0 vdds_mem pop_a1_a1
sdrc_d6 vdds_mem sdrc_dm0 sdrc_d2 sdrc_a2 pop_b1_b1
sdrc_d3 vss sdrc_d1 sdrc_a3
vss
sdrc_a4 sdrc_a6 sdrc_a7 sdrc_a8
vdd_core vdd_core sdrc_d0 sdrc_a5 sdrc_a11 sdrc_a12
vss vss sdrc_a13 sdrc_a14
gpmc_nwe
gpmc_nadv
_ale
vdds_mem vdds_mem
sdrc_ba0
gpmc_nbe0
_cle
gpmc_noe
NC
gpmc_wait3
vdd_core gpmc_ncs1 gpmc_d8 gpmc_nwp
vss
vdd_core vss vdds_mem vdds_mem
vdd_mpu
_iva
gpmc_wait1
gpmc_a10 gpmc_d9 gpmc_d0 gpmc_a4 gpmc_wait2
vdd_mpu
_iva
gpmc_ncs0
sdrc_a9 vss
L
M
N
P
vdd_mpu
_iva
gpmc_wait0
gpmc_a9 gpmc_d2 gpmc_d1
gpmc_ncs7
gpmc_a2 gpmc_a8 pop_k2_m2
pop_y23
_m1
vss
gpmc_a1 gpmc_a7 pop_l2_n2 pop_u1_n1
vss gpmc_d3 gpmc_d10 vss gpmc_ncs6
vss
gpmc_a3
14
sdrc_nclk
13
sdrc_clk
12 11 10
sdrc_d17
sdrc_d8
vdds_mem sdrc_d21 sdrc_dqs2
sdrc_d9 sdrc_d22 vdds_mem sdrc_dm2
vss sdrc_d20 sdrc_d18 vss
sdrc_d23 vss sdrc_d16 vss
sdrc_nras sdrc_ncas sdrc_ncs0 sdrc_ba1
vss vss
vdd_mpu
_iva
vdd_mpu
_iva
vdd_mpu
_iva
vss
vdd_mpu
_iva
vdd_mpu
_iva
vss
vdd_mpu
_iva
sdrc_ncs1
sdrc_d19
vdd_mpu
_iva
vdd_mpu
_iva
vdd_mpu
_iva
vss





A
20
sdrc_dqs3
21
sdrc_d29
22 23 24 25
cam_d5
26 27
pop_a22
_a27
28
B cam_d2 cam_d10 vss
C sdrc_dm3
D dss_hsync
E
F
G
H
J
K
vdds_mem cam_vs cam_hs
pop_a23
_a28
sdrc_d27 sdrc_d30 vdds_mem cam_wen cam_xclkb
pop_b23
_b28
sdrc_d31 vss cam_fld cam_d3
vss
cam_xclka cam_d11 cam_pclk vdds_mem
sdrc_d28 vss vdd_core cam_d4 dss_vsync dss_pclk
vdd_core dss_data6 dss_acbias dss_data20
vdds vdds dss_data8 dss_data7
uart3_rx
_irrx
dss_data9 vss vdds_mem
dss_data19 dss_data18 dss_data17 vdds
vdd_core
hdq_sio dss_data21 pop_h22
_j27
pop_k1_j28
vss
mcbsp1_fsx cam_d8 cam_d6 vdds_mmc1
vdd_core
dss_data16
cam_strobe vdd_core
L
M
N
P
vss
vss cam_d9 cam_d7
vdd_core
pop_k22
_m26
mmc1_cmd vss
vdd_core
mmc1_dat2 mmc1_dat1 mmc1_dat0 mmc1_clk
mmc1_dat5 mmc1_dat4 mmc1_dat3
vdds_
mmc1a
vdd_core
vdd_core
15
pop_a12
_a15
16
sdrc_dm1
17 18 19
sdrc_d26
sdrc_d10
sdrc_dqs1 vdds_mem sdrc_d25
pop_b12
_b15
sdrc_d11 sdrc_d14 vdds_mem
vdds_mem sdrc_d13 sdrc_d24 vss
vdd_core vdds_mem sdrc_d15 vss
sdrc_nwe sdrc_cke0
uart3_cts
_rctx
uart3_rts
_sd
vss vss vdd_core
vdds_dpll
_dll
vdd_core vss
vss
vss vss
vdd_mpu
_iva
sdrc_cke1
sdrc_d12
vdd_core
vdd_core
vdd_core
vss
i2c1_sda
cap_vdd
_sram_core
i2c1_scl
mcbsp2_dx
mcbsp2
_clkx
mcbsp2_fsx
uart3_tx
_irtx




AH
9
etk_d5
8
etk_d15
7 6 5 4
mmc2_dat1
3 2
pop_ac2
_ah2
1
AG mmc2_cmd mmc2_dat2 vss
AF etk_d8
AE mmc2_dat7
AD
AC
AB
AA
Y
W
etk_d13 vdds_mem mmc2_dat0
pop_ac1
_ah1
etk_d9 etk_d14 etk_d12 vss vss
pop_ab1
_ag1
vdds etk_d11 mcbsp3_dx
mcbsp3
_clkx
mmc2_dat5
mmc2_dat3 mmc2_dat6
pop_u2
_af2
pop_ac8
_af1
vdd_core vdds mcbsp3_dr mcbsp3_fsx mmc2_clk mcbsp4
_clkx
vdds vdds mcbsp4_dx mcbsp4_dr
vdd_core mcspi1_cs1
mcspi1
_cs0
mcbsp4
_fsx
mcspi1_clk
mcspi1
_cs3
mcspi1
_cs2
uart1_tx
mcspi1
_somi
mcspi2_clk
pop_aa2
_aa2
pop_aa1
_aa1
vdd_mpu
_iva
mcspi2
_cs0
mcspi2
_somi
mcspi2_
simo
gpmc_d15
vdd_mpu
_iva
uart1_cts vss gpmc_d7 gpmc_d14 vdds
uart1_rx
uart1_rts
mcspi1
_simo
mmc2_dat4 etk_d10
V
U
T
R
vss gpmc_ncs2
mcspi2
_cs1
gpmc_d6 gpmc_d5
gpmc_ncs3 NC gpmc_nbe1 vss vdds_mem
vdd_mpu
_iva
gpmc_clk gpmc_a5 gpmc_d13 gpmc_d4
vdd_mpu
_iva
gpmc_ncs5 gpmc_a6 gpmc_d12 gpmc_d11 vdds_mem
gpmc_ncs4
vss
cap_vdd
_sram
_mpu_iva
14
etk_d7
13
pop_ac11
_ah13
12 11 10
pop_ab8
_ag10
i2c3_scl
etk_d2
pop_ac9
_ah11
pop_ac13
_ah10
i2c3_sda
pop_ab11
_ag13
etk_d1
pop_ab9
_ag11
etk_d6 vss etk_d0 etk_clk
sys_boot2 etk_d3 etk_d4 etk_ctl
jtag_tck jtag_rtck jtag_emu1
vdd_mpu
_iva
vdd_mpu
_iva
vdd_mpu
_iva
vss
vss vss
vdds_wkup
_bg
vss
jtag_emu0
vss
vdd_mpu
_iva
vdd_mpu
_iva
vdd_mpu
_iva
vss
vdd_mpu
_iva
vss
vdd_mpu
_iva




AH
20
cap_vdd_d
21
vss
22 23 24 25
sys
_nrespwron
26 27
pop_ac22
_ah27
28
AG dss_data4 sys_clkout1 vdds
AF vss
AE i2c4_sda
AD
AC
AB
AA
Y
W
dss_data1 dss_data3 dss_data5
pop_ac23
_ah28
vdds vdds dss_data0 dss_data2 sys_boot1
pop_ab23
_ag28
sys_boot6 sys_off
_mode
vdds sys
_nreswarm
sys_boot0
sys_clkreq sys_nirq pop_aa22
_af27
pop_h23
_af28
vss sys_boot5 vdds vdd_core vdds pop_aa23
_ae28
uart2_rx i2c4_scl dss_data11 dss_data10
vss vss dss_data22 dss_data23
uart2_cts dss_data13 dss_data12
uart2_tx vss dss_data15 dss_data14
vss vssa_dac
tv_vfb1
tv_out1
tv_vref tv_vfb2 tv_out2 vss
uart2_rts
sys_32k sys_clkout2
V
U
T
R
hsusb0
_data7
hsusb0
_data6
hsusb0
_data5
hsusb0
_data4
hsusb0
_data3
hsusb0
_data2
hsusb0
_data1
hsusb0_stp hsusb0_nxt hsusb0
_data0
hsusb0_clk
vss mmc1_dat6 hsusb0_dir
mmc1_dat7
vdda_dac
15
pop_l1
_ah15
16
pop_ac14
_ah16
17 18 19
gpio_112
i2c2_scl
cam_d1 gpio_115 gpio_113
pop_ab13
_ag15
vss cam_d0 gpio_114
vdds sys_xtalout sys_boot3 sys_boot4
i2c2_sda vdds vdd_core vdd_core sys_xtalin
jtag_tdi
mcbsp1
_clkr
vdd_core
vdd_core
mcbsp1_dx
mcbsp1
_clkx
vdd_core
vdd_core
mcbsp1_dr
mcbsp_clks
vss mcbsp2_dr
vss
cap_vdd
_wkup
vdds_dpll
_per
jtag_tms
_tmsc
jtag_tdo
vdd_core vss vdd_core
vdd_mpu
_iva
vdd_core vss
vss
vdds_sram vss
vdd_mpu
_iva
jtag_ntrst
vdd_core
vdd_core
vdd_core
vss
mcbsp1_fsr




A
9 8 7 6 5 4 3 2
pop_a1_a1
1
B vss
C
D
E
F
G
H
J
K
NC
gpmc_ncs3 NC
gpmc_ncs2
sys_boot2 i2c2_sda
gpmc_a10
vss
uart1_rx gpmc_a3
vss
vdd_mpu
_iva
mmc2_dat7
vdd_mpu
_iva
vdds
sys_boot6 vss
L
M
N
vdd_mpu
_iva
gpmc_d14 pop_j1_l1
vdds
cap_vdd
_sram_mpu
_iva
vss mcbsp3_dr
uart1_tx
13
vss
12 11 10
vss vdds
vdd_mpu
_iva
vss
vdd_mpu
_iva
vdds_dpll
vdd_core
vdd_mpu
_iva
vss
NC
NC NC vss NC vss NC NC NC NC
NC NC NC NC NC NC NC gpmc_ncs6 gpmc_ncs4 gpmc_wait2
i2c2_scl gpmc_ncs5 gpmc_ncs7 gpmc_wait3 NC NC NC NC NC
vss NC vdds NC NC NC sys_boot1 gpmc_a9
gpmc_a7 gpmc_a8 sys_boot3 sys_boot4
gpmc_a5 gpmc_a6 sys_boot0 NC
gpmc_a4 sys_boot5
gpmc_a2 vss
gpmc_nbe1 gpmc_a1 NC NC
vss gpmc_nbe0
_cle
NC
mmc2_dat6
gpmc_nwe gpmc_d15 mmc2_dat5
gpmc_clk gpmc_noe
vss
vdd_core
NC
NC NC NC NC NC NC
vdd_mpu
_iva
NC NC NC NC NC NC NC
NC NC NC NC NC
vdds NC vss
vdd_mpu
_iva
NC
vdd_mpu
_iva
vdd_mpu
_iva





A
18
vdds
19 20 21 22 23
cam_d3
24 25
pop_a20
_a25
26
B
cam_d2
cam_fld vss
C
D
E
F
G
H
J
K
pop_b16
_a20
pop_a21
_a26
cam_wen
cam_xclka
pop_b21
_b26
cam_hs cam_d5 cam_pclk
vss vdd_core cam_d4
dss_data6
dss_acbias dss_data20
dss_data9
uart3_rx
_irrx
dss_data7
hdq_sio
pop_h21
_k26
mmc1_dat2 vss
cam_d8
cam_strobe
L
M
N
dss_vsync
vdds_mmc1 mmc1_clk
14
NC
15 16 17
vdd_core
vss
cap_vdd
_sram
_core
cap_vdd
_wkup
vss
NC NC NC NC NC NC
NC NC NC NC NC NC NC NC NC
NC NC NC NC NC NC NC NC NC
cam_d10 cam_vs NC vss NC NC NC vss NC
cam_d11 cam_xclkb vdds NC vss
uart3_rts
_sd
uart3_cts
_rctx
dss_pclk
uart3_tx
_irtx
vss
dss_data8 NC
i2c1_scl i2c1_sda
NC dss_hsync
dss_data17 dss_data16 vdds vss
dss_data19 dss_data18 NC
dss_data21 cam_d9
NC NC NC NC vdd_core NC vss
vdd_core NC NC NC NC NC NC
NC NC vdds NC NC vdds NC
NC NC NC
vdds vss mmc1_cmd vss
mmc1_dat4 mmc1_dat0 mmc1_dat1
NC mmc1_dat3




AF
9 8 7 6 5 4 3 2
pop_aa1
_af1
1
AE
AD
AC
AB
AA
Y
W
V
U
NC
sys_
nreswarm
gpmc_wait1
i2c3_scl
etk_d9
gpmc_d11 gpmc_d12
vdd_mpu
_iva
T
R
P
mmc2_dat1
vss uart1_rts
gpmc_d13 NC
pop_n2_t2 vdds
13 12 11 10
vss
jtag_rtck
vdd_mpu
_iva
sys_off
_mode
sys_clkout2
mmc2_cmd
vdd_mpu
_iva
vss
vdd_core
vdd_mpu
_iva
vdd_mpu
_iva
vdds_sram
mcbsp3_dx NC
mcspi1
_somi
mcspi1_clk
mcspi1
_simo
mcspi1_cs1 mcspi1_cs2 mcspi1_cs0 mcbsp4_dx vss
gpmc_d10 mcbsp4_fsx mcspi1_cs3 mmc2_dat0
mmc2_dat2 mmc2_dat3
mcspi2
_somi
vdd_mpu
_iva
mcbsp4_dr mcbsp3
_clkx
gpmc_d8
mcbsp4
_clkx
NC
vdd_mpu
_iva
mcspi2_cs0 mcspi2_cs1 mmc2_dat4
sys_
nrespwron
NC mmc2_clk
mcspi2
_simo
mcspi2_clk vss mcbsp3_fsx uart1_cts vss
gpmc_d9 pop_t2_y2 etk_d4 vdds vss vdd_core
vdd_mpu
_iva
vss
vdd_mpu
_iva
vdd_core jtag_tdo
etk_d8 etk_d3 gpmc_d0 gpmc_d1
etk_d5 etk_clk etk_ctl
gpmc_d3 gpmc_d2 etk_d0 i2c3_sda gpmc_d7 gpmc_nwp vdds NC gpmc_wait0 NC NC
NC NC NC
gpmc_nadv
_ale
NC gpmc_ncs0 gpmc_d5 gpmc_d6 etk_d1 etk_d2 etk_d7 gpmc_ncs1
pop_w2
_ae2
etk_d6 etk_d10 gpmc_d4 etk_d12 vss NC etk_d15 vdds NC NC NC
NC NC
pop_y2
_af4
pop_aa6
_af5
etk_d11 etk_d13
pop_y7
_af8
etk_d14
pop_y9
_af10
NC
pop_aa10
_af12
pop_aa11
_af13




AF
18 19 20 21 22 23 24 25
pop_aa20
_af25
26
AE cam_d1
AD
AC
AB
AA
Y
W
V
U
pop_aa21
_af26
cap_vdd_d sys_32k dss_data3
vss vdd_core
dss_data15
dss_data12 dss_data14
uart2_cts vss
vdds
vdds
hsusb0
_data2
pop_p21
_u26
tv_vfb2
cam_d6
dss_data13
T
R
P
vdds
cam_d7
vss
vdds
_mmc1a
NC
vss
14 15 16 17
sys_clkout1
gpio_112
vss
vss
sys_nirq
i2c4_sda
vdd_core
mmc1_dat5
jtag_tdi
vdds_dpll
_per
hsusb0_stp
mcbsp1_fsx mmc1_dat6 mmc1_dat7
mcbsp2_dx
mcbsp1_dr
mcbsp
_clks
mcbsp2_dr
mcbsp1
_clkx
mcbsp1
_clkr
mcbsp2
_fsx
mcbsp2
_clkx
mcbsp2_dx
mcbsp1_dx jtag_ntrst
jtag_tck
jtag_tms
_tmsc
mcbsp1_fsr hsusb0_dir
hsusb0
_data0
hsusb0
_data3
hsusb0_clk hsusb0_nxt
hsusb0
_data4
sys_clkreq
vdds_wkup
_bg
jtag_emu1 jtag_emu0
hsusb0
_data7
hsusb0
_data5
hsusb0
_data6
hsusb0
_data1
NC NC NC NC
NC NC
NC vss
tv_out2 vdda_dac vssa_dac tv_vref
vss tv_vfb1 tv_out1
NC
uart2_rts NC
vss NC dss_data23
dss_data10 dss_data22 vdds NC NC NC vdds NC vdds NC dss_data10
dss_data11 vss dss_data5 dss_data4 uart2_tx uart2_rx vdds vdds vdds gpio_113 i2c4_scl vss
cam_d0 gpio_115 gpio_114 dss_data0 dss_data1 dss_data2
pop_y20
_ae25
pop_y21
_ae26
pop_y19
_af24
vss
pop_aa19
_af22
pop_y17
_af21
sys_xtalout sys_xtalin
pop_aa17
_af18
pop_y14
_af17
pop_aa14
_af16
pop_aa13
_af15
pop_aa12
_af14




A
9 8
sdrc_dqs2
7 6 5 4
sdrc_a0
3 2
NC
1
B sdrc_d3 sdrc_a1 sdrc_a4
C sdrc_d16
D sdrc_a10
E
F
G
H
J
K
sdrc_dm2 sdrc_dqs0 NC
sdrc_d19 sdrc_d18 sdrc_d7 sdrc_dm0 sdrc_a3 NC
sdrc_d6 sdrc_d2 sdrc_d1 sdrc_a5 gpmc_wait3 gpmc_wait0
sdrc_d4 sdrc_a2 gpmc_ncs3
sdrc_a6 gpmc_ncs0 gpmc_nwp
gpmc_ncs4 gpmc_ncs6 gpmc_noe gpmc_nadv
_ale
vdd_mpu
_iva
gpmc_nwe gpmc_a10
vdd_mmc1a gpmc_ncs1 gpmc_a9 gpmc_a8
vdd_mpu
_iva
gpmc_a4 gpmc_a5 gpmc_a6 gpmc_a7
vdds_mem gpmc_a2 gpmc_a3 gpmc_a1
vdds_mem
vdd_mpu
_iva
gpmc_ncs7
sdrc_d0
L
M
vss gpmc_d0 gpmc_nbe1
vdd_mpu
_iva
mcspi2_cs1 gpmc_d4 gpmc_d2 gpmc_d1 vss
12 11 10
sdrc_d21
sdrc_nclk sdrc_clk
sdrc_d10 sdrc_d8
sdrc_d9 sdrc_d20
sdrc_d5
vdd_mpu
_iva
vdd_core
vdd_mpu
_iva
vss vdd_mpu
_iva
vss
vss
vdd_core
sdrc_d22
vss
vss
vss
sdrc_a9 sdrc_a10
sdrc_a14 sdrc_a7 sdrc_a13
sdrc_d17 sdrc_a8
vdd_mpu
_iva
vdd_core
sdrc_a11 gpmc_ncs5 sdrc_a12
vss
vdd_mpu
_iva
vss
vdd_mpu
_iva
vdd_mpu
_iva
vdds_mem
mcspi2_cs0
vdd_mpu
_iva
vdds_mem
vdds_mem
vdd_mpu
_iva
gpmc_nbe0
_cle
vdds_mem





A
16
sdrc_dm3
17
sdrc_dqs3
18 19 20 21 22 23
uart3_cts
_rctx
24
B sdrc_cke0 cam_d5
uart3_rts
_sd
C sdrc_d28
D
E
F
G
H
J
K
sdrc_ncs0 sdrc_nwe hdq_sio
sdrc_d27 sdrc_d30 sdrc_d31 sdrc_ncs1 cam_xclka
uart3_rx
_irrx
sdrc_ba0 sdrc_ncas sdrc_cke1
cam_hs
cam_xclkb uart3_tx
_irtx
sdrc_d29 dss_data20 dss_data6
dss_hsync dss_data7 dss_data8
cam_d10 dss_vsync dss_data9
vdds_mem dss_pclk dss_data17
dss_data18
cap_vdd
_sram_core
dss_data19 cam_fld
vss dss_acbias dss_data16 cam_d8
dss_data21 cam_d9 cam_d7 i2c1_sda
vss
cam_d11
sdrc_ba1
L
M
mmc1_cmd cam_d6
mmc1_dat1 mmc1_dat0 mmc1_clk vss
13 14 15
sdrc_d15
sdrc_dqs1 sdrc_d14
sdrc_dm1 sdrc_d13
sdrc_d12 sdrc_d26
sdrc_d25
vdds_mem
vdd_core vdds_mem
vss vss
vdd_core
sdrc_d11
vss
vdds_mem cam_vs
sdrc_nras
vdds_mem cam_d3 cam_wen
sdrc_d23 sdrc_d24
vdds_mem vdd_core
cam_d2 cam_d4
vdds_dpll
_dll
cam_pclk
i2c1_scl
cam_strobe
mmc1_dat2
vss vdd_core vdd_core
vss vss vdd_core vdd_core vdd_core
vss vdd_core vdd_core vss
vss vdd_core vdd_core vdds vdds vdds




AD
9 8 7 6 5 4 3 2 1
AC
etk_d5
AB
AA
Y
W
V
U
T
R
NC
jtag_tdi mmc2_cmd
jtag_rtck
mmc2_clk
mmc2_dat3
cap_vdd
_sram_mpu
_iva
gpmc_d13
vss
gpmc_d8 gpmc_d7
P
N
gpmc_d6
mcspi2
_somi
gpmc-d3
vss
12 11 10
i2c3_sda
sys_boot0
vdds
vss vss
vdds_sram
sys_clkout1 cap_vdd
_wkup
sys_
nreswarm
uart1_rx
vss
vdd_mpu
_iva
vdd_mpu
_iva
vdd_mpu
_iva
vdd_mpu
_iva
mcspi2
_somo
mcspi2
_clk
vdd_mpu
_iva
vss vss
vss vss vss vss gpmc_d5
mcspi1
_simo
mcspi1
_cs3
vdd_mpu
_iva
gpmc_d11 vss vss
vss
vdd_mpu
_iva
vdd_mpu
_iva
mcspi1
_cs0
mcspi1
_clk
mcspi1
_somi
gpmc_d12 gpmc_d9
gpmc_d10 vss vss
vdd_mpu
_iva
vdd_mpu
_iva
vdds vdds mcbsp3_dx mcbsp3_dr mcbsp3_fsx gpmc_d15 gpmc_d14
gpmc_clk mmc2_dat2 mcbsp3_
clkx
uart1_rts uart1_tx vdds vdds
vdd_mpu
_iva
vdds mmc2_dat1 mmc2_dat6
mmc2_dat7 mmc2_dat5 sys_clkout2
jtag_tms
_tmsc
sys_
nrespwron
jtag_tdo jtag_ntrst jtag_tck mmc2_dat0 mmc2_dat4
etk_d10 etk_clk uart1_cts
etk_ctl
etk_d8 etk_d4 etk_d1 etk_d2 etk_d6 etk_d11 etk_d12 etk_d14
etk_d15 etk_d13 etk_d7 etk_d3 etk_d0 etk_d9




AD
16 17 18 19 20 21 22 23
sys_off_
mode
24
AC dss_data3 dss_data5 dss_data11
AB
AA
Y
W
V
U
T
R
sys_boot1 sys_boot4 cam_d1 dss_data0 dss_data10 jtag_emu0
cam_d0 dss_data1
mcbsp1
_fsr
dss_data12 tv_vfb1
sys_32k tv_out2
tv_vfb2 tv_vref
dss_data15
hsusb0
_data5
vdds_dpll
_per
vss
mcbsp2
_clkx
hsusb0
_data7
hsusb0
_data1
hsusb0
_data0
hsusb0_nxt hsusb0_stp hsusb0_clk
dss_data22
sys_boot6
P
N
hsusb0_dir mmc1_dat7
mmc1_dat5 mmc1_dat4 mmc1_dat3 vdds_mmc1 vdds
13 14 15
i2c2_scl i2c3_scl i2c2_sda
vdda_dac vssa_dac
vdd_mpu
_iva
vss vss
mcbsp1
_dr
mcbsp1
_clkr
mcbsp1
_dx
vdds_wkup
_bg
vss
mcbsp2_dr mcbsp2
_fsx
mcbsp1
_clkx
vss
mcbsp2_dx
mmc1_dat6 vss vss vss vdds vdds
vss vss vss vss
vss vss vdd_core vdd_core vdd_core
vdd_core vdd_core vdd_core vdd_core vss
vss vss vss
hsusb0
_data3
hsusb0
_data2
vss vss
vdd_mpu
_iva
vdd_mpu
_iva
sys_nirq dss_data23 dss_data14
hsusb0
_data6
hsusb0
_data4
dss_data13 sys_clkreq i2c4_sda i2c4_scl
mcbsp
_clks
mcbsp1
_fsx
tv_out1 sys_boot5
jtag_emu1 dss_data4 dss_data2 sys_boot3 sys_boot2 sys_xtalin sys_xtalout

MPU
IVA2
vdd_mpu_iva1domain
Core
Periph1
vdd_coredomain
DPLL_MPU
LDO
in1.8V
out1.2V
DualVideoDAC
SRAM2
ARRAY
SRAM2LDO
0V/1.0V/1.2V
SRAM1
ARRAY
SRAM1LDO
0V/1.0V/1.2V
MMC1
vpp
DPLL_CORE
LDO
in1.8V
out1.2V
DPLL4
LDO
in1.8V
out1.2V
DPLL_IVA
LDO
in1.8V
out1.2V
LDO3
1.0V/1.2V
vdds
Periph2
DPLL5
LDO
in1.8V
out1.2V
WKUP
EMU
BandGap
BCK
MEM
vss
DLL/DCDL
HSDIVIDER
LDO
eFUSE
HSDIVIDER
LDO
cap_vdd_sram_mpu_iva
cap_vdd_sram_core
tv_ref
(forcapacitor)
vssa_dac
vdd_mpu_iva
vdds_dpll_dll
vdds_wkup_bg
cap_vdd_wkup
vdds_mem
vdds_sram
OMAP Device
vdd_core
vdds_mmc1
vdds_dpll_per
vdda_dac
030-003
V
D
D
S
M
E
M
V
D
D
S
vdds_mmc1a

SRAM_LDO1
cap_vdd_sram_mpu_
iva
SRAM_LDO2
cap_vdd_sram_core
BG
WKUP_LDO
vdds_wkup_bg
DPLL_MPU
DPLL_IVA
DPLL_CORE
vdds_dpll_dll
vdds_sram
DPLL5
DPLL4
vdds_dpll_per
Video DAC
vdda_dac
MMC IOs
vdds_mmc1
OMAP Device
VSS
vssa_dac
Cvdds_sram
Ccap_vdd_sram_mpu_iva
Ccap_vdd_sram_core
Cvdds_wkup_bg
Cvdds_dpll_dll
Cvdds_dpll_per
Cvdda_dac
Cvdds_mmc1
vdda_dac
vdds_mmc1
vdds_sram
vdds_wkup_bg
vdds_dpll_per
vdds_dpll_dll
Ccap_vdd_wkup
cap_vdd_wkup
MPU
Vdd_mpu_iva
Cvdd_mpu_iva
vdd_mpu_iva
Core
vdd_core
Cvdd_core
Vdd_core
030-004
vdds_mmc1a
vdds_mmc1a
Cvdds_mmc1a
Video DAC
DSS
cap_vdd_d
cap_vdd_d
Ccap_vdd_d
I/Os and Memory
vdds
vdds_mem
Cvdds_mem
Cvdds






























030-005
vdds_mem,vdds,
vdds_sram
vdd_mpu_iva
vdd_core
vdds_dpll_dll
vdds_wkup_bg
vdds_mmc1,vdds_mmc1a,
vdda_dac , vpp
(1)
sys_32k
sys_nrespwron
(2)
1.8 V
sys_xtalin
sys_nreswarm
EFUSE.RSTPWRON(internal)
vdds_dpll_per
ldo3 (internal)
(2)
1.8 V
1.8 V
1.8 V





034-009
vdds_dpll_dll,
vdds_dpll_per
vdd_core,
vdd_mpu_iva
sys_32k
sys_nrespwron
sys_xtalin
vdds_mmc1,vdds_mmc1a,
vdda_dac
vdds_sram
vdds_wkup_bg
vdds,
vdds_mem


















OMAP
PowerIC sys_32k
sys_altclk
sys_clkout1
AlternateClockSourceSelectable(54,48MHzorother[up
to59MHz])
ToQuartz (Oscillatoroutput)orUnconnected
ToQuartz (Oscillatorinput)orSquareClock
ClockRequest.ToSquareClockSourceorfromPeripherals
Oscillator
isUsed
Oscillator
isBypassed
Unconnected
Square
Clock
Source
ToPeripherals (FromOSC_CLK:12,13,16.8,19.2,26,or
38.4MHz,core_clk[DPLL,upto332MHz],DPLL-96MHz
orDPLL-54MHzoutputswithadividerof1,2,4,8,or16)
GPin
ToPeripherals (FromOSC_CLK:12,13,16.8,19.2,26,or
38.4MHz)
sys_clkout2
sys_xtalout
sys_xtalin
sys_clkreq
sys_xtalout
sys_xtalin
sys_clkreq
sys_xtalout
sys_xtalin
sys_clkreq
030-007




























sys_xtalin sys_xtalout
OMAP Device
Crystal
OptionalR
bias
OptionalR
d
C
f2 C
f1
030-008







































ESR=R
m
1+
C
0
C
L
2

sys_xtalin sys_xtalout
OMAP Device
sys_clkreq
ClockSquarerSource
Oscillator
InBypassMode
030-010

sys.xtalin
OCS0 OCS1 OCS1
030-011

sys_32k
CK0 CK1 CK1
030-012

sys_altclk
ALT0 ALT1 ALT1
030-013








































sys_clkout
CO0 CO1 CO1
030-014

sys_clkout
CO0 CO1 CO1
030-015


























OMAP
DLL
vdds_dpll_dll
PowerRail
DPLL4
DPLL1
DPLL2
DPLL3
vdds_dpll_per
DPLL5
030-016

OMAP Device
DPLL_MPU DPLL_IVA DPLL_CORE DLL
DPLL5 DPLL4
vdds_dpll_dll
vdds_dpll_per
C
NoiseFilter
C
NoiseFilter
030-017























OMAP Device
DSS
tv_vref
DIN1[9:0]
vssa_dac vdda_dac
VideoDAC 1
TVDCT
VideoDAC 2
TVOUT
BUFFER
DIN2[9:0]
TVOUT
BUFFER
TVOUT
BUFFER
tv_vfb1
tv_out1
CBG
tv_out2
tv_vfb2
V_ref
030-018
R
O
U
T
1
R
O
U
T
2

AC
OUTFS
OUT
DAC
V
I
I
PSRR
D

=
100
%FSR
V
1
100kHz 1MHz
10
PSRR(%FSR/V)
f
Firstpoleof
DACoutputload
030-019

Cycle(orPeriod)Jitter
T
n-1
T
n
T
n+1
Max.CycleJitter=Max(T )
i
Min.CycleJitter=Min(T )
i
JitterStandardDeviation(orrmsJitter)=StandardDeviation(T )
i
030-020

gpmc_clk
gpmc_ncsx
gpmc_a[10:1]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_noe
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Valid Address
D0
OUT OUT IN OUT
F0
F12
F13
F4
F6
F2
F8
F3
F7
F9
F11
F1
F1
F8
F19
F18
F20
F10
F6
F19
030-021
F23 F24





gpmc_clk
gpmc_ncsx
gpmc_a[10:1]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_noe
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Valid Address
D0 D1 D2 D3
OUT OUT IN OUT
F0
F12
F13 F13
F12
F4
F1
F1
F2
F6
F3
F7
F8 F8 F9
F10 F11
F21 F22
F6
F7
030-022
F23 F24





gpmc_clk
gpmc_ncsx
gpmc_a[10:1]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_nwe
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Valid Address
D0 D1 D2 D3
OUT
F4
F15 F15 F15
F1
F1
F2
F6
F8 F8
F0
F14 F14
F3
F17
F17
F17
F9 F6
F17
F17
F17
030-023





gpmc_clk
gpmc_ncsx
gpmc_nbe0_cle
gpmc_nbe1
gpmc_a[26:17]
gpmc_a[16:1]_d[15:0]
gpmc_nadv_ale
gpmc_noe
gpmc_waitx
gpmc_io_dir
Valid
Valid
Address(MSB)
Address(LSB) D0 D1 D2 D3
OUT OUT IN OUT
F4
F6
F4
F2
F8 F8
F10
F13
F12
F12
F11
F9
F7
F3
F0 F1
F1
F5
F6 F7
030-024
F23 F24





gpmc_clk
gpmc_ncsx
gpmc_a[26:17]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_nwe
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Address(MSB)
Address(LSB) D0 D1 D2 D3
OUT
F4
F15 F15 F15
F1
F1
F2
F6
F8 F8
F0
F3
F17
F17
F17
F9 F6
F17
F17
F17
F14 F14
030-025

GPMC_FCLK
gpmc_clk
gpmc_ncsx
gpmc_a[10:1]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_noe
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Valid Address
Valid
Valid
DataIN0 DataIN0
OUT OUT IN OUT
FA0
FA9
FA10
FA3
FA1
FA4
FA12
FA13
FA0
FA10
FA5
030-026
FA15
FA14
























GPMC_FCLK
gpmc_clk
gpmc_ncsx
gpmc_a[10:1]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_noe
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Address0 Address1
Valid Valid
Valid Valid
DataUpper
OUT OUT IN OUT IN
FA9
FA10
FA3
FA9
FA3
FA13 FA13
FA1 FA1
FA4 FA4
FA12 FA12
FA10
FA0 FA0
FA16
FA0 FA0
FA10 FA10
FA5 FA5
030-027
FA15 FA15
FA14 FA14










GPMC_FCLK
gpmc_clk
gpmc_ncsx
gpmc_a[10:1]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_noe
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Add0 Add1 Add2 Add3 Add4
D0 D1 D2 D3 D3
OUT IN
OUT
FA1
FA0
FA18
FA13
FA12
FA0
FA9
FA10
FA10
FA21 FA20 FA20 FA20
030-028
FA15
FA14














gpmc_fclk
gpmc_clk
gpmc_ncsx
gpmc_a[10:1]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_nwe
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Valid Address
DataOUT
OUT
FA0
FA1
FA10
FA3
FA25
FA29
FA9
FA12
FA27
FA0
FA10
030-029





GPMC_FCLK
gpmc_clk
gpmc_ncsx
gpmc_a[26:17]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_noe
gpmc_a[16:1]_d[15:0]
gpmc_io_dir
gpmc_waitx
Address(MSB)
Valid
Valid
Address(LSB) DataIN DataIN
OUT IN
OUT
FA0
FA9
FA10
FA3
FA13
FA29
FA1
FA37
FA12
FA4
FA10
FA0
FA5
030-030
FA15
FA14










gpmc_fclk
gpmc_clk
gpmc_ncsx
gpmc_a[26:17]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_nwe
gpmc_a[16:1]_d[15:0]
gpmc_waitx
gpmc_io_dir
Address(MSB)
Valid Address(LSB) DataOUT
OUT
FA0
FA1
FA9
FA10
FA3
FA25
FA29
FA12
FA27
FA28
FA0
FA10
030-031

GPMC_FCLK
gpmc_ncsx
gpmc_nbe0_cle
gpmc_nadv_ale
gpmc_noe
gpmc_nwe
gpmc_a[16:1]_d[15:0] Command
GNF0
GNF1
GNF2
GNF3 GNF4
GNF5
GNF6
030-032
GPMC_FCLK
gpmc_ncsx
gpmc_nbe0_cle
gpmc_nadv_ale
gpmc_noe
gpmc_nwe
gpmc_a[16:1]_d[15:0] Address
GNF0
GNF1
GNF7
GNF3 GNF4
GNF6
GNF8
GNF9
030-033







GPMC_FCLK
gpmc_ncsx
gpmc_nbe0_cle
gpmc_nadv_ale
gpmc_noe
gpmc_a[16:1]_d[15:0]
gpmc_waitx
DATA
GNF10
GNF13
GNF14
GNF15
GNF12
030-034
GPMC_FCLK
gpmc_ncsx
gpmc_nbe0_cle
gpmc_nadv_ale
gpmc_noe
gpmc_nwe
gpmc_a[16:1]_d[15:0] DATA
GNF0
GNF1
GNF4
GNF6
GNF9
GNF3
030-035













































sdrc_d0
sdrc_d7
sdrc_dm0
sdrc_dqs0
sdrc_d8
sdrc_d15
sdrc_dm1
sdrc_dqs1
sdrc_d16
sdrc_d23
sdrc_dm2
sdrc_dqs2
sdrc_d24
sdrc_d31
sdrc_dm3
sdrc_dqs3
sdrc_ba0
sdrc_ba1
sdrc_a0
sdrc_a14
sdrc_ncs0
sdrc_ncs1 N/C
sdrc_ncas
sdrc_nras
sdrc_nwe
sdrc_cke0
sdrc_cke1 N/C
sdrc_clk
sdrc_nclk
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
DQ0
DQ7
LDM
LDQS
DQ8
DQ15
UDM
UDQS
BA0
BA1
A0
A14
CS
CAS
RAS
WE
CKE
CK
CK
BA0
BA1
A0
A14
CS
CAS
RAS
WE
CKE
CK
CK
T
T
T
T
T
T
T
T
LPDDR
OMAP35x
DQ0
DQ7
LDM
LDQS
DQ8
DQ15
UDM
UDQS
LPDDR




sdrc_d0
sdrc_d7
sdrc_dm0
sdrc_dqs0
sdrc_d8
sdrc_d15
sdrc_dm1
sdrc_dqs1
sdrc_d16
sdrc_d23
sdrc_dm2
sdrc_dqs2
sdrc_d24
sdrc_d31
sdrc_dm3
sdrc_dqs3
sdrc_ba0
sdrc_ba1
sdrc_a0
sdrc_a14
sdrc_ncs0
sdrc_ncas
sdrc_nras
sdrc_nwe
sdrc_cke0
sdrc_clk
sdrc_nclk
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
BA0
BA1
A0
A14
CS
CAS
RAS
WE
CKE
CK
CK
T
T
T
T
T
T
T
T
OMAP35x
DQ0
DQ7
DM0
DQS0
DQ8
DQ15
DM1
DQS1
LPDDR
DQ16
DQ23
DM2
DQS2
DQ24
DQ31
DM3
DQS3
N/C
N/C
sdrc_ncs1
sdrc_cke1






































































A1
A1
X
Y
OFFSET
RecommendedLPDDRDevice
Orientation
Y
Y
OFFSET
LPDDR
Device
L
P
D
D
R
C
o
n
t
r
o
l
l
e
r
OMAP

A1
A1
L
P
D
D
R

C
o
n
t
r
o
l
l
e
r
LPDDRDevice
RegionshouldencompassallLPDDRcircuitryandvariesdepending
onplacement.Non-LPDDRsignalsshouldnotberoutedonthe
LPDDRsignallayerswithintheLPDDRkeepoutregion.Non-LPDDR
signalsmayberoutedintheregionprovidedtheyareroutedon
layersseparatedfromLPDDRsignallayersbyagroundlayer.No
breaksshouldbeallowedinthereferencegroundlayersinthis
region.Inaddition,the1.8Vpowerplaneshouldcovertheentirekeep
outregion.


































A1
A1
C
B
A
T
L
P
D
D
R
C
o
n
t
r
o
l
l
e
r
OMAP

A1
A1
E0
T
E1
T
E2
OMAP
E3
T
L
P
D
D
R
C
o
n
t
r
o
l
l
e
r
T

cam_xclki
cam_pclk
cam_vs
cam_hs
cam_d[11:0]
cam_wen
cam_fld
D(0) D(n-3) D(n-2) D(n-1) D(0) D(1) D(n-1)
ISP15
ISP16
ISP16
ISP17 ISP18
ISP19 ISP20
ISP21 ISP22
ISP24 ISP23
ISP25 ISP26
ISP18
030-056

cam_xclki
cam_pclk
cam_vs
cam_hs
cam_d[7:0]
cam_wen
cam_fld
D(0) D(n-3) D(n-2) D(n-1) D(0) D(1) D(n-1)
ISP1 ISP2 ISP2
ISP3 ISP4
ISP5 ISP6
ISP7 ISP8
ISP10
ISP4
ISP9
ISP11
030-059
ISP12

cam_xclki
cam_pclk
cam_vs
cam_hs
cam_d[11:0]
cam_wen
cam_fld
FRAME(0) FRAME(0)
L(0) L(n-1) L(0)
D(0) D(n-3) D(n-2) D(n-1) D(0) D(1) D(2) D(n-1)
PAIR IMPAIR
ISP15
ISP16
ISP16
ISP17 ISP18
ISP18
ISP27
ISP19
ISP21 ISP22
ISP23
ISP20
ISP28
ISP24
ISP25 ISP26
030-057

cam_xclki
cam_pclk
cam_vs
cam_hs
cam_d[7:0]
cam_wen
cam_fld
FRAME(0) FRAME(0)
L(0) L(n-1) L(0)
D(0) D(n-3) D(n-2) D(n-1) D(0) D(1) D(2) D(n-1)
PAIR IMPAIR
ISP1
ISP2
ISP2
ISP3 ISP4
ISP4
ISP13
ISP5
ISP7 ISP8
ISP9
ISP6
ISP14
ISP10
ISP11 ISP12
030-060

cam_xclki
cam_pclk
cam_d[9:0] SOF
D(0) D(n-1)
EOF SOF
D(0) D(n-1)
EOF
ISP15
ISP16
ISP16
ISP17
ISP23 ISP24
ISP18 ISP18
030-058










































































dss_pclk
dss_vsync
dss_hsync
dss_acbias
dss_data[23:0]
DL4
DL5
DL3
DL0
DL2
DL1
030-061









































dss_pclk
dss_vsync
dss_hsync
dss_acbias
dss_data[23:0]
DL4
DL5
DL3
030-062

rfbi_a0
WeCycleTime
CsPulseWidth
WeCycleTime
CsOffTime
CsOnTime
WeOnTime
WeOffTime
DATA1 DATA0
CsOffTime
CsOnTime
WeOffTime
WeOnTime
rfbi_csx
rfbi_wr
rfbi_da[15:0]
rfbi_rd
034-002
DATA1 DATA0
rfbi_a0
rfbi_csx
rfbi_wr
rfbi_da[15:0]
rfbi_rd
AccessTime
ReCycleTime
AccessTime
ReCycleTime
CsPulseWidth
CsOffTime
CsOnTime
CsOffTime
CsOnTime
ReOnTime
ReOffTime
ReOnTime
ReOffTime
DR0
DR1
034-003











WeCycleTime
WeCycleTime AccessTime
ReCycleTime
CsOffTime
CsOnTime CsOnTime CsOnTime
CsOffTime CsOffTime
WeOffTime
WeOnTime
WeOffTime
WeOnTime
ReOffTime
ReOnTime
CsPulseWidth CsPulseWidth
READ WRITE WRITE
rfbi_a0
rfbi_csx
rfbi_wr
rfbi_rd
rfbi_da[15:0]
034-004

mcbspx_clkr
mcbspx_fsr
mcbspx_dr D7 D6 D5
B2 B2
B3 B4
030-068
mcbspx_clkr
mcbspx_fsr
mcbspx_dr D7 D6 D5
B3 B4
B5 B6
030-069





























































































































mcbspx_clkx
mcbspx_fsx
mcbspx_dx D7 D6 D5
B2 B2
B8
030-070
mcbspx_clkx
mcbspx_fsx
mcbspx_dx D7 D6 D5
B8
B5 B6
030-071





































































































































mcbspx_clkr
mcbspx_fsr
mcbspx_dr D7 D6 D5
B2 B2
B3 B4
030-072
mcbspx_clkr
mcbspx_fsr
mcbspx_dr D7 D6 D5
B3 B4
B5 B6
030-073


















































mcbspx_clkx
mcbspx_fsx
mcbspx_dx D7 D6 D5
B2 B2
B8
030-074
































































mcbspx_clkx
mcbspx_fsx
mcbspx_dx D7 D6 D5
B8
B5 B6
030-075

mcspix_cs0(EPOL=1)
mcspix_clk(POL=0)
mcspix_clk(POL=1)
mcspix_simo
mcspix_somi
mcspix_cs0(EPOL=1)
mcspix_clk(POL=0)
mcspix_clk(POL=1)
mcspix_simo
mcspix_somi
Bitn-1 Bitn-2 Bitn-3 Bitn-4 Bit0
Bitn-1 Bitn-2 Bitn-3 Bitn-4 Bit0
Bitn-1 Bitn-2 Bitn-3 Bit1 Bit0
Bitn-1 Bitn-2 Bitn-3 Bit1 Bit0
SS4 SS5
SS6
SS3
SS1
SS0
SS2
SS1
SS0
SS4 SS5
SS3
SS1
SS0
SS1
SS0
SS2
SS6
SS7
Mode0&2
Mode1&3
030-076

mcspix_csn(EPOL=1)
mcspix_clk(POL=0)
mcspix_clk(POL=1)
mcspix_simo
mcspix_somi
mcspix_csn(EPOL=1)
mcspix_clk(POL=0)
mcspix_clk(POL=1)
mcspix_simo
mcspix_somi
Bitn-1 Bitn-2 Bitn-3 Bitn-4 Bit0
Bitn-1 Bitn-2 Bitn-3 Bitn-4 Bit0
Bitn-1 Bitn-2 Bitn-3 Bit1 Bit0
Bitn-1 Bitn-2 Bitn-3 Bit1 Bit0
SM5 SM6
SM4
SM3
SM1
SM0
SM2
SM1
SM0
SM5 SM6
SM3
SM1
SM0
SM1
SM0
SM2
SM4
SM7
Mode0&2
Mode1&3
030-077

mmx_txen_n
mmx_txdat
mmx_txse0
mmx_rxdp
mmx_rxdm
mmx_rxrcv
FSU5
FSU6 FSU7
FSU1
FSU1
FSU2
FSU2
FSU3 FSU4
FSU8
FSU9
Transmit
Receive
030-080

mmx_txen_n
mmx_txdat
mmx_txse0
mmx_rxrcv
FSU16
FSU14
FSU15
FSU10
FSU10
FSU11
FSU11
FSU12 FSU13
FSU17
FSU18
Transmit
Receive
030-081

mmx_txen_n
mmx_txdat
mmx_txse0
FSU23
FSU21
FSU22
FSU19
FSU19
FSU20
FSU20
FSU24
FSU25
Transmit
Receive
030-082

mmx_txen_n
mmx_txdat
mmx_txse0
mmx_rxdp
mmx_rxdm
mmx_rxrcv
FSUT3 FSUT5
FSUT4 FSUT6 FSUT7
FSUT8
FSUT1
FSUT1
FSUT2
FSUT2
Transmit Receive
030-083

mmx_txen_n
mmx_txdat
mmx_txse0
mmx_rxrcv
FSUT13
FSUT11
FSUT12
FSUT9
FSUT9
FSUT10
FSUT10
FSUT14
FSUT15
FSUT16
Receive Transmit
030-084

mmx_txen_n
mmx_txdat
mmx_txse0
FSUT21
FSUT19
FSUT20
FSUT17
FSUT17
FSUT18
FSUT18
FSUT22
FSUT23
Transmit
Receive
030-085

hsusb0_clk
hsusb0_stp
hsusb0_dir_&_nxt
hsusb0_data[7:0] Data_OUT Data_IN
HSU1
HSU0
HSU1
HSU4
HSU2 HSU2 HSU6
HSU3
HSU5
030-086

hsusbx_clk
hsusbx_stp
hsusbx_dir_&_nxt
hsusbx_data[7:0] Data_OUT Data_IN
HSU1
HSU0
HSU1
HSU4
HSU2 HSU2 HSU6
HSU3
HSU5
030-087

hsusbx_tll_clk
hsusbx_tll_stp
hsusbx_tll_dir_&_nxt
hsusbx_tll_data[7:0] Data_IN Data_OUT
HSU0
HSU6
HSU2
HSU3
HSU5
HSU4 HSU7
HSU7
HSU6
030-088

hsusbx_tll_clk
hsusbx_tll_stp
hsusbx_tll_dir_&_nxt
hsusbx_tll_data[3:0]
Data_IN Data_IN_(n+1) Data_IN_(n+2) Data_OUT Data_OUT_(n+1)
HSU0
HSU6
HSU2
HSU3
HSU6
HSU1 HSU1
HSU4 HSU4
HSU5 HSU5
HSU7
HSU8
HSU7
030-089

i2cX_sda
i2cX_scl
START REPEAT
STOP START
START
I1
I2
I3 I4
I5
I6 I6 I7
I8
030-093









i2cX_sda
i2cX_scl
STOP START REPEAT
I1 I2 I3 I4 I6 I5 I7
030-094

HDQ
tB tBR
030-095
HDQ
tHW1
tHW0
tCYCH
030-096

HDQ
tDW1
tDW0
tCYCD
030-097
HDQ
Break
0_(LSB)
1 6 7_(MSB)
tRSPS
0_(LSB)
1
6
Command _byte_written Data_byte_received
030-098

1-WIRE
tRSTH
tPDL tPDH tRTSL
030-099

1-WIRE
tLOWR
tRDV_and_ tREL
tSLOT_and_ tREC
030-100
1-WIRE
tLOW1
tLOW0
tSLOT_and_tREC
030-101

030-118
Pulseduration
90%
50%
10%
t
f
90%
50%
10%
t
r

mmcx_clk
mmcx_cmd
mmcx_dat[3:0]
MMC3
MMC7
MMC4
MMC8
MMC1 MMC2
030-104
mmcx_clk
mmcx_cmd
mmcx_dat[3:0]
MMC5 MMC5
MMC6 MMC6
MMC1 MMC2
030-105

mmcx_clk
mmcx_cmd
mmcx_dat[3:0]
HSSD3
HSSD7
HSSD4
HSSD8
HSSD1 HSSD2
030-106
mmcx_clk
mmcx_cmd
mmcx_dat[3:0]
HSSD5 HSSD5
HSSD6 HSSD6
HSSD1 HSSD2
030-107

mmcx_clk
mmcx_cmd
mmcx_dat[3:0]
SD3
SD7
SD4
SD8
SD1 SD2
030-108
mmcx_clk
mmcx_cmd
mmcx_dat[3:0]
SD1 SD2
SD5
SD6
SD5
SD6
030-109















etk_clk
etk_ctl
etk_d[15:0]
ETM0
ETM2
ETM3
ETM2
ETM1
ETM3
030-110












































sdti_clk
sdti_txd[3:0] Header Header Ad[7:4] Ad[3:0] Da[15:12] Da[11:8] Da[7:4] Da[3:0]
SD1 SD2
SD3 SD3
030-111

sdti_clk
sdti_txd[3:0] Header Header Ad[7:4] Ad[3:0] Da[15:12] Da[11:8] Da[7:4] Da[3:0]
SD1 SD2
SD3 SD3
030-112

jtag_tck
jtag_rtck
jtag_tdi
jtag_tms
jtag_emux(IN)
jtag_tdo
jtag_emux(OUT)
JT7
JT11
JT1
JT2 JT3
JT8
JT10 JT9
JT4
JT5 JT6
JT12 JT13
JT14
030-113

jtag_tck
jtag_tdi
jtag_tms
jtag_rtck
jtag_tdo
JA1
JA2 JA3
JA4
JA5 JA6
JA7 JA8
JA10 JA9
JA11
030-114

PREFIX
X OMAP3530 D
X = Experimental Device
P = Prototype Device
blank= Production Device
DEVICE
PACKAGE TYPE
CBB = 515 pin s-PBGA
CBC = 515 pin s-PBGA
CUS = 423 pin s-PBGA
SILICON REVISION
CBB ( ) ( )
blank = 0 C to 90 C (commercial temperature)
A = -40 C to 105 C (extended temperature)
blank = 600 MHz Cortex - A8
= 720 MHz Cortex - A8 72
( )
blank = Tray
R = Tape and Reel
























































PACKAGE OPTION ADDENDUM
www.ti.com 23-Apr-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
OMAP3525DCBB OBSOLETE POP-FCBGA CBB 515 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
OMAP3525DCBBA OBSOLETE POP-FCBGA CBB 515 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
OMAP3525DCBC OBSOLETE POP-FCBGA CBC 515 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
OMAP3525DCBCA OBSOLETE POP-FCBGA CBC 515 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
OMAP3525DCUS OBSOLETE FCBGA CUS 423 Green (RoHS
& no Sb/Br)
SNAGCU Level-4-260C-72 HR
OMAP3525DCUSA OBSOLETE FCBGA CUS 423 Green (RoHS
& no Sb/Br)
SNAGCU Level-4-260C-72 HR
OMAP3525ECBB ACTIVE POP-FCBGA CBB 515 90 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
OMAP3525ECBBA ACTIVE POP-FCBGA CBB 515 90 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
OMAP3525ECBC ACTIVE POP-FCBGA CBC 515 90 TBD Call TI Call TI
OMAP3525ECBCA ACTIVE POP-FCBGA CBC 515 119 TBD Call TI Call TI
OMAP3525ECUS ACTIVE FCBGA CUS 423 90 Green (RoHS
& no Sb/Br)
SNAGCU Level-4-260C-72 HR
OMAP3525ECUSA ACTIVE FCBGA CUS 423 90 Green (RoHS
& no Sb/Br)
SNAGCU Level-4-260C-72 HR
OMAP3530DCBB OBSOLETE POP-FCBGA CBB 515 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
OMAP3530DCBB72 OBSOLETE POP-FCBGA CBB 515 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
OMAP3530DCBBA OBSOLETE POP-FCBGA CBB 515 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
OMAP3530DCBC OBSOLETE POP-FCBGA CBC 515 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
OMAP3530DCBC72 OBSOLETE POP-FCBGA CBC 515 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
OMAP3530DCBCA OBSOLETE POP-FCBGA CBC 515 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
www.ti.com 23-Apr-2012
Addendum-Page 2
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
OMAP3530DCUS OBSOLETE FCBGA CUS 423 Green (RoHS
& no Sb/Br)
SNAGCU Level-4-260C-72 HR
OMAP3530DCUS72 OBSOLETE FCBGA CUS 423 Green (RoHS
& no Sb/Br)
SNAGCU Level-4-260C-72 HR
OMAP3530DCUSA OBSOLETE FCBGA CUS 423 Green (RoHS
& no Sb/Br)
SNAGCU Level-4-260C-72 HR
OMAP3530ECBB ACTIVE POP-FCBGA CBB 515 90 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
OMAP3530ECBB72 ACTIVE POP-FCBGA CBB 515 90 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
OMAP3530ECBBA ACTIVE POP-FCBGA CBB 515 90 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR
OMAP3530ECBC ACTIVE POP-FCBGA CBC 515 90 TBD Call TI Call TI
OMAP3530ECBC72 ACTIVE POP-FCBGA CBC 515 119 TBD Call TI Call TI
OMAP3530ECBCA ACTIVE POP-FCBGA CBC 515 90 TBD Call TI Call TI
OMAP3530ECUS ACTIVE FCBGA CUS 423 90 Green (RoHS
& no Sb/Br)
SNAGCU Level-4-260C-72 HR
OMAP3530ECUS72 ACTIVE FCBGA CUS 423 90 Green (RoHS
& no Sb/Br)
SNAGCU Level-4-260C-72 HR
OMAP3530ECUSA ACTIVE FCBGA CUS 423 90 Green (RoHS
& no Sb/Br)
SNAGCU Level-4-260C-72 HR

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 23-Apr-2012
Addendum-Page 3

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TIs terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TIs standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright 2012, Texas Instruments Incorporated