EE4292 Integrated Circuit Design Lab

Verilog RTL Coding Style

Hsi-Pin Ma
http://larc.ee.nthu.edu.tw/~hp/EE4292/ Department of Electrical Engineering National Tsing Hua University

Acknowledgement
Thanks for Verilog slides from Prof. Chih-Tsun Huang.

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References
Michael Keating and Pierre Bricaud, Reuse Methodology Manual, Kluwer Academic Publishers, Third Ed., 2002 M. Morris Mano, Digital Design, 3rd edition, 2002. Guide to HDL Coding Styles for Synthesis, SOLD. Preparing Design Files for Synthesis (Chapter 3 in Design Compiler User Guide), SOLD.

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Basic Design Concepts

Simple and regular
Use simple constructs and simple clocking schemes Consistent coding style, consistent naming and state machines Regular partitioning scheme Easy to understand by comments and meaningful names. No hard coded number

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Module Partition
Focus
Keep critical path within a module All module outputs are registered

Module
Well-selected the gate count number within a module (250 - 5000) Prepare to reuse hierarchical modules

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Register All Outputs

Guideline
For each subblock of a hierarchical macro design, register all output signals from the subblock.

Subblock 1

Subblock 2

Block A
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Locate Related Combinational Logic in a Single Module

Guideline
Keep related combinational logic together in the same module

Design Compiler must preserve port definitions. Logic optimization cannot cross block boundaries Path from Reg A to Reg C may be larger and slower than necessary.

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Locate Related Combinational Logic in a Single Module

Related combinational logic is grouped into one block. Sequential optimization may absorb some of the combinational logic into a more complex flip-flop. (Best)
(JK, T, Muxed, Clock-enabled,)

Better
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Best
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Separate Modules That Have Different Design Goals

Speed Optimization

Critical Path Logic

Reg A

Module A

Area Optimization

Non-critical Path Logic

Reg B

Module B

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Eliminate Glue Logic at the Top Level

Guideline
Do not instantiate gate-level logic at the top level of the macro hierarchy.

BAD
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Good
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Adding Structure
Focus
Explicit specify the separate assignment Make use of the parentheses

Modeling
Build the design as your knowledge Dont rely on CAD tools Separated combinational and sequential logic blocks

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Naming and Labeling Styles (1/3)

Using general naming conventions consistently
Document the naming convention Use lowercase letters for all signal names, variable names, and port names. Use uppercase letters for names of constants and userdefined types. Use meaningful names for signals, ports, and parameters.
Do not use ra for a RAM address bus, but use ram_addr.

Use a consistent name for the clock signal, such as clk.

If there is more than one clock, use clk as the prefix for all clock signals. (clk1, clk2, clk_interface).
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Naming and Labeling Styles (1/3)

Using general naming conventions consistently
Use the same name for all clock signals that are driven from the same source. For active-low signals, end the signal with an underscore followed by a lowercase character (_b, _n) Use a consistent name for reset signals, such as rst. If the reset signal is active-low, use a name like, rst_n. When describing multibit buses, use a consistent ordering bits. Use [x:0] for Verilog, (x downto 0) for VHDL. When possible, use the same name or similar names for ports and signals that are connected.

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Naming and Labeling Styles (2/3)

Using Named and Positional Association
Incorrect
BUFGS CLK_1 (.I(CLOCK_IN), CLOCK_OUT);

Correct
BUFGS CLK_1 (.I(CLOCK_IN), .O(CLOCK_OUT));

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Naming and Labeling Styles (3/3)

Port maps and generic maps Rule
Always use explicit mapping for ports and generics, using named association rather than positional association.
DW_ram_r_w_s_dff #((`ram_data_width+`ram_be_data_width), (`fifo_depth),1) U_int_txf_ram ( .clk (refclk), .rst_n (txfifo_ram_reset_n), .cs_n (1b0), .wr_n (txfifo_wr_en_n), .rd_addr (txfifo_rd_addr), .wd_addr (txfifo_wr_addr), .data_in (txfifo_wr_data), .data_out (txf_ram_data_out) )
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Do Not Use Hard-Coded Numeric Values

Guideline
Do not use hard-coded numeric values.

Poor coding style

wire [7:0] reg [7:0] my_in_bus; my_out_bus;

Advantages using constants

Constants are more intelligible as they associate a design intension with the value. Constant values can be changed in one place. Compilers can spot typos in constants but not in hardcoded values.

Recommended coding style

`define MY_BUS_SIZE 8 wire [`MY_BUS_SIZE-1:0] reg [`MY_BUS_SIZE-1:0] my_in_bus; my_out_bus;

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Constant Definition Files

Guideline
Keep constant and parameters definitions in one or a small number of files with names such as DesignName_constants.v or DesignName_parameters.v

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Specifying Constants
Use constants in your design to substitute numbers to more meaningful names. The use of constants helps make a design more readable and portable.
//Using parameters for OPCODE functions parameter ZERO = 2b00; parameter A_AND_B = 2b01; parameter A_OR_B = 2b10; parameter ONE = 2b11; always @ (OPCODE or A or B) begin if (OPCODE == ZERO) OP_OUT = 1b0; else if (OPCODE == A_AND_B) OP_OUT=A&B; else if (OPCODE == A_OR_B) OP_OUT = A|B; else OP_OUT = 1b1; end // Using a parameter for Bus Size parameter BUS_SIZE = 8; output [BUS_SIZE-1:0] OUT; input [BUS_SIZE-1:0] X,Y;

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Include Informational Headers in Source File

Rule
Include a commented, informational header at the top of every source file, including scripts.
Legal statement: confidentiality, copyright, restrictions on reproduction Filename Author Description of function and list of key features of the module. Date the file was created Modification history, including date, name of modifier, and description of the change

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Use Comments
Rule
Use comments appropriately to explain processes, functions, and declarations of types and subtypes.

Guideline
Use comments to explain ports, signals, and variables, or group of signals or variables.

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Keep Commands on Separate Line

Rule
Use a separate line for each HDL statement. More readable and maintainable.

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Line Length & Indentation

Line length guideline
Keep the line length to 72 characters or less.

Indentation guidelines
Use indentation of 2 spaces. Larger indentation restricts line length when there are several levels of nesting. Avoid of using tabs. Differences in editors and user setups make the positioning of tabs unpredictable and corrupt the intended indentation.

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Port Ordering
Rule
Declare ports in a logical order, and keeps this order consistent throughout the design

Guidelines
Declare one port per line, with a comment following it (preferably on the same line) For each instance, declare the ports in the following order
Inputs
Clocks Resets Enables Other control signals Data and address lines Clocks Resets Enables Other control signals Data

Outputs

Use comments to describe groups of ports.

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Coding for Synthesis

Omit the Wait for XX ns Statement
Do not use #XX;

Omit the ...After XX ns or Delay Statement

Do not use assign #XX Q=0;

Omit Initial Values

Do not use initial sum = 1b0;

Ignore by synthesizer

Order and Group Arithmetic Functions

ADD = A1 + A2 + A3 + A4; ADD = (A1 + A2) + (A3 + A4);
Not equivalent!

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Conditional Expressions (1/3)

If statement vs. Case statement
If statement
Priority-encoded logic For speed critical path

Case statement
Balanced logic For complex decoding

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Conditional Expressions (2/3)

Consideration when writing If statement
Make sure that all outputs are defined in all branches of an if statement.
If not, it can create latches or long equations on the CE signal. A good way to prevent this is to have default values for all outputs before the if statements.

Limiting the number of input signals into an if statement can reduce the number of logic levels.
If there are a large number of input signals, see if some of them can be pre-decoded and registered before the if statement.

Avoid bringing the dataflow into a complex if statement.

Only control signals should be generated in complex if-else statements.
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Conditional Expressions (3/3)

module if_ex (A, B, C, D, SEL, MUX_OUT); input A, B, C, D; input [1:0] SEL; output MUX_OUT; reg MUX_OUT; always @ (A or B or C or D or SEL) begin if (SEL == 2b00) MUX_OUT = A; else if (SEL == 2b01) MUX_OUT = B; else if (SEL == 2b10) MUX_OUT = C; else if (SEL == 2b11) MUX_OUT = D; else MUX_OUT = 0; end endmodule module case_ex (A, B, C, D, SEL, MUX_OUT); input A, B, C, D; input [1:0] SEL; output MUX_OUT; reg MUX_OUT; always @ (A or B or C or D or SEL) begin case (SEL) 2b00: MUX_OUT = A; 2b01: MUX_OUT = B; 2b10: MUX_OUT = C; 2b11: MUX_OUT = D; default: MUX_OUT = 0; endcase end endmodule

Default value
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Avoiding Combinational Feedback

Bad : Combinational processes are looped.
REG A REG B

COMB

COMB

COMB

Good : Combinational processes are not looped.

REG A

REG B

COMB

COMB

COMB

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Specify Complete Sensitivity Lists

Rule
Include a complete sensitivity list in each of your always blocks.

Incomplete sensitivity list

always @(a) c <= a or b;

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Guidelines for Clocks

Avoid using both positive- and negative-edge clocks
Post problem for timing analysis Problems for scan Separate pos and neg FFs in different modules

Avoid clock buffers in synthesis Avoid gated clock Avoid internally generated clocks
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Forbidden Coding Style

Syntax error for Verilog Simulator Mixed edge-triggered and level-sensitive control in an always block
always @(addr or posedge clk) begin ...... end

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Non-Synthesizable Style
Either non-synthesizable or incorrect after synthesis initial block is forbidden (non-synthesizable) Multiple assignments (multiple driving sources) (non-synthesizable) always @(src1 or src2)
result = src1 + src2; always @(inc1 or inc2 or offset) result = inc1 + inc2 + offset;

Mixed blocking and non-blocking assignment

always @(opcode or src1 or src2 or inc) begin ... des = src1 + src2; inc <= src1 - 4; if (opcode == SUB) ... end

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FSM Coding Style

Explicit FSM design
always @(state or in) begin case (state) S0: if (in) next_state = S1; else next_state = S0; S1: ... end always @(posedge clk) if (~reset) state <= S0; else state <= next_state;
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Reset
Asynchronous reset
Entering the reset state asynchronously, but leaving synchronous
always @(posedge clk or negedge rst) if (~rst) q <= 0; else q<= d;

Synchronous reset
Similar to an enable signal entering and leaving the reset state synchronously
always @(posedge clk) if (~rst) q <= 0; else q<= d;
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Specify explicit Vendor Macro Cell

`ifdef IMPLEMENTATION <macro cell instance implementation> `else <RTL behavior specification> `endif
`ifdef IMPLEMENTATION wire t1, t2, t3; XOR3 U1(t1, in[0], in[1], in[2]); XOR3 U2(t2, in[3], in[4], in[5]); XOR3 U3(t3, in[6], in[7], in[8]); XOR3 U4(perr, t1, t2, t3); `else perr = ^in; // calculate parity on in `endif

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Coding for Synthesis

No initial in the RTL code FFs are preferred Avoid unnecessary latches Avoid combinational feedback For sequential blocks, use no-blocking statements For combinational blocks, use blocking statements Coding state machines
Two procedure blocks: one for the sequential and one for the combinational Keep FSM logic and non-FSM logic in separate modules Assign a default state
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