Reg. No.

M.E. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2010 First Semester VLSI Design

VL 9211 DSP INTEGRATED CIRCUITS (Common to M.E. Applied Electronics) (Regulation 2009) Time : Three hours Answer ALL questions

PART A (10 2 = 20 Marks) 1. 2. 3. 4. 5. What is abstraction?

List main features of a structured design methodology.

What is the use of DCT?

What are the properties of IIR filter designed using impulse invariant techniques? A multirate system is required for converting the sampling rate from 48 K samples to 42.1 K samples. What are the interpolation factor, decimation factor to be used? What is separator Register? What is MAG?

6.

7. 8.

9.

What is redundancy factor? What are the fundamental operations in RNS signal processing?

10.

What are parasitic oscillations?

4
Maximum : 100 Marks

Question Paper Code : 98076

PART B (5 16 = 80 Marks) 11. (a) (i) Describe a systematic partitioning technique for the design of a complex DSP system. Also give a motivation for the chosen partitioning technique. (8) Describe the different types of transformations between two adjacent levels of abstraction in the design process. Also describe different types of transformations within a design level. (8)

(ii)

(b)

Explain the following VLSI process technologies : (i) (ii) Bulk CMOS technology. Bipolar Technology.

Or

(iii) GaAs Based Technology. 12. (a)

Explain Nyquist sampling theorem and also how to select sampling frequency for sampling analog signal.

(b) 13. (a)

Find radix 2, DIT, FFT of the sequence x(n ) = {1, 1, 1, 1, 2, 2, 2, 2} . Determine the impulse response coefficients of a digital filter whose frequency response is given by
0 for | w | < 0.85 H e jw = 1 for 0.85 <| w | <

( )

(b)

What is Round off noise? Explain the method to measure round off noise in digital system. Explain in detail the random, linear and regular topology architectures models used in the synthesis of VLSI layout. Or

14.

(a)

(b)

15.

(a)

Derive design W1 from design F using transformations such as edge reversal, associativity slow-down, retiming and pipelining. Explain the layout of Bit-serial architecture of VLSI circuits. Or

(b)

Design an FFT processor for computing the DFT. 2

4
Or

Or

0
(8) (4) (4)

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98076