Zilog Z80 CPU Specifications

by Sean Young (syoung@cs.vu.nl) Last update: September 21, 1997

Opcode Prefixes
There are four different opcode prefixes: CB, DD, ED and FD. If an opcode begins the DD prefix, the IX register is used in stead of the HL register and likewise the FD prefix results in use of the IY register in stead of the HL register. If HL refers to memory address, (e.g. LD A, (HL) ), an offset d is added to the opcode (e.g. LD A, (IX + d) ). If the instruction uses the H or L register, the high order byte or the low order byte of the IX or IY register is used. There are two exceptions to this rule, though: the EXX and EX DE, HL instructions. These instructions cannot be changed with a DD or FD prefix. If the instruction does not use the HL, H or L register, the instruction is executed as without the DD or FD prefix (except for the DDCB and FDCB opcode prefixes). Multiple DDs or FDs after each other operate like NOPs. If a instruction is preceded by an ED, a new set of instructions is used (see Opcode list). If the opcode is not listed, it will operate as two NOPs. Similarly the CB, FDCB and the DDCB select a new instruction set, though every possible instruction has a function and is listed.

The IM 0/1 and RETI/N instructions

The opcode list shows these two strange instructions. They are unofficial, and because both possibilities operate exactly the same way on a MSX, I can not determine which one they are. It is not important on a MSX though, but if anyone knows which one they are, please let me know.

Registers
The Z80 has the following (accessible) registers: I, R, A, F, BC, DE, HL, IX, IY, SP, PC, AF, BC, DE and HL. The R register is for memory refresh. It is increased by 1 after every instruction, whereby the CB, DD, DDCB, ED, FD and FDCB prefixes are viewed as separate instructions. Bit 7 is never modified, but it can be changed with LD A,R. The F register is the flag register. It has the following structure: Bit 7: The S flag: if the result of the operation is negative, this flag is high. This is a copy of the MSB of the result of the operation. Bit 6: The Z flag: if the result is zero, this flag is high. Bit 5: This bit has no official name. Throughout this document it is referred to as b5. It is a copy of bit 5 of the result of the operation. Bit 4: The H flag. This is the carry from bit 3 to bit 4 of the operation. Used with DAA instruction. Bit 3: This bit has no official name. Throughout this document it is referred to as b3. It is a copy of bit 3 of the result of the operation. Bit 2: The P/V flag. It contains the overflow (high if twos complements result does not fit in register) or the parity (parity of number of high bits in result of operation). See description of instructions for which one. Bit 1: The N flag. It is high if the last operation was an subtraction, otherwise it was an addition. Used with DAA instruction. Bit 0: The C flag. If the result of the operation does not fit in the register, this bit is high. Sometimes the flags have other meanings. See descriptions of instructions for details.

Interrupts
There are two types of interrupts: mask-able and non mask-able, and the are two flip-flops associated with interrupts: IFF1 and IFF2. DI resets both and EI sets both. If IFF1 is set then mask-able interrupts are accepted. When an non mask-able interrupt occurs, the IFF1 is reset, so disabling mask-able interrupts. When the CPU returns from a non mask-able interrupt (with RETN) the IFF2 is copied into IFF1 (and thus restored). Only IFF2 can be read (with LD A, I and LD A, R IFF2 is copied into the P/V flag).
MSX Specific: non mask-able interrupts never occur in a MSX, so the two interrupt flip-flops are always identical. Viewing the CPU as though it has one Interrupt flip-flop is not incorrect.

Interrupt Modes
Interrupt modes can be set with the IM x instructions. They only affect mask-able interrupts. When a mask-able interrupt occurs, the interrupting device must supply a value. Interrupt Mode 0: The value the interrupting device supplies is interpreted as an 8 bit opcode which is executed (usually RST p instructions). Interrupt Mode 1: A call is made to address 38h. The value the interrupting device supplies is ignored. Interrupt Mode 2: A call is made to an address read from address (register I 256 + value from interrupting device).
MSX Specific: The MSX has one interrupting device (the VDP), which always provides value FFh (instruction RST 38h), so the MSX operates the same in Interrupt Mode 0 as in 1. In IM 2 a call is made to an address read from address (register I 256 + FFh).

Instructions Descriptions
8 bit Load Group
Mnemonic LD r, r LD p, p* LD q, q* LD r, n LD p, n* Symbolic Operation r r p p Opcode No. of No. of M No. of T 76 543 210 Hex Bytes Cycles States 01 r r 1 1 4 11 011 101 DD 2 2 8 01 p p 11 111 101 FD 2 2 8 q q 01 q q 00 r 110 2 2 7 r n n 11 011 101 DD 3 3 11 p n 00 p 110 n 11 111 101 FD 3 3 11 q n 00 q 110 n 01 r 110 1 2 7 r (HL) 11 011 101 DD 3 5 19 r (IX + d) 01 r 110 d 11 111 101 FD 3 5 19 r (IY + d) 01 r 110 d 01 110 r 1 2 7 (HL) r 11 011 101 DD 3 5 19 (IX + d) r 01 110 r d 11 111 101 FD 3 5 19 (IY + d) r 01 110 r d 00 110 110 36 2 3 10 (HL) n n 11 011 101 DD 4 5 19 (IX + d) n 00 110 110 36 d n 11 111 101 FD 4 5 19 (IY + d) n 00 110 110 36 d n 00 001 010 0A 1 2 7 A (BC) 00 011 010 1A 1 2 7 A (DE) 00 111 010 3A 3 4 13 A (nn) n n 00 000 010 02 1 2 7 (BC) A 00 010 010 12 1 2 7 (DE) A 00 110 010 32 3 4 13 (nn) A n n 11 101 101 ED 2 2 9 A I 0 IFF2 0 01 010 111 57 11 101 101 ED 2 2 9 A R 0 IFF2 0 01 011 111 5F 11 101 101 ED 2 2 9 I A 01 000 111 47 11 101 101 ED 2 2 9 R A 01 001 111 4F r, r means any of the registers A, B, C, D, E, H, L. p, p means any of the registers A, B, C, D, E, IXH, IXL. q, q means any of the registers A, B, C, D, E, IY H, IYL. ddL, ddH refer to high order and low order eight bits of the register respectively. * means unofficial instruction. = flag is not affected, 0 = flag is reset, 1 = flag is set, = flag is set according to the result of the operation, IFF 2 = the interrupt flip-flop 2 is copied. Flags S Z F5 H F3 P/V N C Comments r, r Reg. 000 B 001 C 010 D 011 E 100 H 101 L 111 A p, p 000 001 010 011 100 101 111 q, q 000 001 010 011 100 101 111 Reg. B C D E IXH IXL A Req. B C D E IYH IYL A

LD q, n*

LD r, (HL) LD r, (IX + d)

LD r, (IY + d)

LD (HL), r LD (IX + d), r

LD (IY + d), r

LD (HL), n LD (IX + d), n

LD (IY + d), n

LD A, (BC) LD A, (DE) LD A, (nn)

LD (BC), A LD (DE), A LD (nn), A

LD A, I LD A, R LD I, A LD R, A Notes:

R is read after it is increased.

R is written after it is increased.

Flag Notation:

16 bit Load Group

Mnemonic LD dd, nn Symbolic Operation dd nn Flags S Z F5 H F3 P/V N C Opcode 76 543 210 00 dd0 001 n n 11 011 101 00 110 001 n n 11 111 101 00 110 001 n n 00 101 010 n n 11 101 101 01 dd1 011 n n 11 011 101 00 101 010 n n 11 111 101 00 101 010 n n 00 100 010 n n 11 101 101 01 dd0 011 n n 11 011 101 00 100 010 n n 11 111 101 00 100 010 n n 11 111 001 11 011 101 11 111 001 11 111 101 11 111 001 11 qq0 101 Hex No. of Bytes 3 No. of M Cycles 3 No. of T States 10 Comments dd Pair 00 BC 01 DE 02 HL 03 SP

LD IX, nn

IX

nn

DD 21

14

LD IY, nn

IY

nn

FD 21

14

LD HL, (nn)

L H

(nn) (nn+1)

2A

16

LD dd, (nn)

ddL (nn) ddH (nn+1) IXL IXH (nn) (nn+1)

ED

20

LD IX, (nn)

DD 2A

20

LD IY, (nn)

IYL IYH

(nn) (nn+1)

FD 2A

20

LD (nn), HL

(nn) L (nn+1) H (nn) ddL (nn+1) ddH (nn) IXL (nn+1) IXH

22

16

LD (nn), dd

DD

20

LD (nn), IX

DD 22

20

LD (nn), IY

(nn) IYL (nn+1) IYH

FD 22

20

LD SP, HL LD SP, IX LD SP, IY PUSH qq

SP SP SP SP (SP) SP (SP) SP (SP) SP (SP) SP (SP) SP (SP) (SP) SP (SP) SP (SP) SP (SP) SP (SP) SP (SP) SP

HL IX IY

F9 DD F9 FD F9

1 2 2

1 2 2

6 10 10

PUSH IX

PUSH IY

POP qq

POP IX

POP IY

Notes: Flag Notation:

1 3 11 qq Pair SP - 1 00 BC qqH 01 DE SP - 1 10 HL qqL 11 011 101 DD 2 4 15 11 AF SP - 1 11 100 101 E5 IXH SP - 1 IXL 11 111 101 FD 2 4 15 SP - 1 11 100 101 E5 IYH SP - 1 IYL 11 qq0 001 1 3 10 qqL SP + 1 qqH SP + 1 11 011 101 DD 2 4 14 IXL 11 100 001 E1 SP + 1 IXH SP + 1 11 111 101 FD 2 4 14 IYL 11 100 001 E1 SP + 1 IYH SP + 1 dd is any of the register pair BC, DE, HL, SP. qq is any of the register pair BC, DE, HL, AF. = flag is not affected, 0 = flag is reset, 1 = flag is set, = flag is set according to the result of the operation.

Exchange, Block Transfer and Search Groups

Mnemonic EX DE, HL EX AF, AF EXX Symbolic Flags Opcode No.of No.of M No.of T Operation S Z F5 H F3 P/V N C 76 543 210 Hex Bytes Cycles States Comments 11 101 011 EB 1 1 4 DE HL 00 001 000 08 1 1 4 AF AF 11 011 001 D9 1 1 4 BC BC DE DE HL HL 11 100 011 E3 1 5 19 (SP+1) H (SP) L 11 011 101 DD 2 6 23 (SP+1) 11 100 011 E3 IXH (SP) IXL 11 111 101 FD 2 6 23 (SP+1) 11 100 011 E3 IYH (SP) IYL 11 101 101 ED 2 4 16 (DE) (HL) 1 0 2 3 0 10 100 000 A0 DE DE + 1 HL HL + 1 BC BC - 1 11 101 101 ED 2 5 21 (DE) (HL) if BC 0 1 0 2 0 0 10 110 000 B0 2 4 16 if BC = 0 DE DE + 1 HL HL + 1 BC BC - 1 repeat until: BC = 0 11 101 101 ED 2 4 16 (DE) (HL) 1 0 2 3 0 10 101 000 A8 DE DE - 1 HL HL - 1 BC BC - 1 11 101 101 ED 2 5 21 (DE) (HL) if BC 0 1 0 2 0 0 10 111 000 B8 2 4 16 if BC = 0 DE DE - 1 HL HL - 1 BC BC - 1 repeat until: BC = 0 A - (HL) 11 101 101 ED 2 4 16 4 4 5 4 6 3 1 10 100 001 A1 HL HL + 1 BC BC -1 A - (HL) 11 101 101 ED 2 5 21 if BC 0 and 4 4 5 4 6 3 1 10 110 001 B1 HL HL + 1 A (HL). 2 4 16 BC BC -1 if BC = 0 or Repeat until: A = (HL) A = (HL) or BC = 0 A - (HL) 11 101 101 ED 2 4 16 4 4 5 4 6 3 1 10 101 001 A9 HL HL - 1 BC BC -1 A - (HL) 11 101 101 ED 2 5 21 if BC 0 and 4 4 5 4 6 3 1 10 111 001 B9 HL HL - 1 A (HL). 2 4 16 BC BC -1 if BC = 0 or Repeat until: A = (HL) A = (HL) or BC = 0 1 F5 is a copy of bit 1 of A + last transferred byte, thus (A + (HL))1 2 F3 is a copy of bit 3 of A + last transferred byte, thus (A + (HL)) 3 3 P/V flag is 0 if the result of BC - 1 = 0, otherwise P/V = 1. 4 These flags are set as in CP (HL) 5 F5 is copy of bit 1 of A - last compared address - H, thus (A - (HL) - H)1. H is as in F after the comparison. 6 F3 is copy of bit 3 of A - last compared address - H, thus (A - (HL) - H)3. H is as in F after the comparison. = flag is not affected, 0 = flag is reset, 1 = flag is set, = flag is set according to the result of the operation.

EX (SP), HL EX (SP), IX

EX (SP), IY

LDI

LDIR

LDD

LDDR

CPI

CPIR

CPD

CPDR

Notes:

Flag Notation:

8 bit Arithmetic and Logical Group

Mnemonic ADD A, r ADD A, p* ADD A, q* ADD A, n ADD A, (HL) ADD A, (IX + d) Symbolic Operation A A A A A A A+r A+p A+q A+n A + (HL) A + (IX + d) Flags S Z F5 H F3 P/V N C V V V V V V 0 0 0 0 0 0 Opcode 76 543 210 10 000 r 11 011 101 10 000 p 11 111 101 10 000 q 11 000 110 n 10 000 110 11 011 101 10 000 110 d 11 111 101 10 000 110 d 001 010 011 100 110 101 111 00 r 100 11 011 101 00 p 100 11 111 101 00 q 100 00 110 100 11 011 101 00 110 100 d 11 111 101 00 110 100 d 101 Hex No.of Bytes 1 2 2 2 1 3 No.of M Cycles 1 2 2 2 2 5 No.of T States 4 8 8 8 7 19 Comments r 000 001 010 011 100 101 111 Reg. B C D E H L A p 000 001 010 011 100 101 111 Reg. B C D E IXH IXH A

DD FD

DD

ADD A, (IY + d)

A + (IY + d)

FD

19

ADC A, s SUB A, s SBC A, s AND s OR s XOR s CP s INC r INC p* INC q* INC (HL) INC (IX + d)

A A A A A

A + s + CY A- s A - s - CY A AND s A OR s

1 0 0

V V V P P P V V V

0 1 1 0 0 0 1 0 0 0 0 0

0 0 0

A A XOR s A-s r r+1 p p+1 q q+1

s is any of r, n, (HL), (IX+d), (IY+d), p, q as shown for the ADD instruction. The underlined bits replace the underlined bits in the ADD set. DD FD 1 2 2 1 3 1 2 2 3 6 4 8 8 11 23 q 000 001 010 011 100 101 111 Reg. B C D E IYH IYL A

V V V

(HL) (HL) + 1 (IX + d) (IX + d) + 1 (IY + d) (IY + d) + 1 m m-1

DD

INC (IY + d)

FD

23

DEC m

m is any of r, p, q, (HL), (IX+d), (IY+d), as shown for the INC instruction. DEC same format and states as INC. Replace 100 with 101 in opcode.

Notes:

Flag Notation:

F5 and F3 are copied from the operand (s), not from the result of (A - s). The V symbol in the P/V flag column indicates that the P/V flags contains the overflow of the operation. Similarly the P symbol indicates parity. r means any of the registers A, B, C, D, E, H, L. p means any of the registers A, B, C, D, E, IXH, IXL. q means any of the registers A, B, C, D, E, IY H, IYL. ddL, ddH refer to high order and low order eight bits of the register respectively. CY means the carry flip-flop. * means unofficial instruction. = flag is not affected, 0 = flag is reset, 1 = flag is set, = flag is set according to the result of the operation.

16 bit Arithmetic Group

Mnemonic ADD HL, ss ADC HL, ss SBC HL, ss ADD IX, pp ADD IY, rr INC ss INC IX INC IY DEC ss DEC IX DEC IY Notes: Symbolic Operation HL HL + ss HL HL + ss + CY HL HL - ss - CY Opcode No.of No.of M No.of T 76 543 210 Hex Bytes Cycles States Comments 00 ss1 001 1 3 11 ss Reg. 11 101 101 ED 2 4 15 00 BC 01 ss1 010 01 DE 11 101 101 ED 2 4 15 10 HL 1 1 2 2 2 V 1 1 1 01 ss0 010 11 SP 11 011 101 DD 2 4 15 IX IX + pp 2 2 2 0 1 00 pp1 001 pp Reg. 11 111 101 FD 2 4 15 00 BC IY IY + rr 2 2 2 0 1 00 rr1 001 01 DE 00 ss0 011 1 1 6 10 IX ss ss + 1 11 011 101 DD 2 2 10 11 SP IX IX + 1 00 100 011 23 11 111 101 FD 2 2 10 rr Reg. IY IY + 1 00 100 011 23 00 BC 00 ss1 011 1 1 6 01 DE ss ss - 1 11 011 101 DD 2 2 10 10 IY IX IX - 1 00 101 011 2B 11 SP 11 111 101 FD 2 2 10 IY IY - 1 00 101 011 2B The V symbol in the P/V flag column indicates that the P/V flags contains the overflow of the operation. ss means any of the registers BC, DE, HL, SP. pp means any of the registers BC, DE, IX, SP. rr means any of the registers BC, DE, IY, SP. 16 bit additions are performed by first adding the two low order eight bits, and then the two high order eight bits. 1 Indicates the flag is affected by the 16 bit result of the operation. 2 Indicates the flag is affected by the 8 bit addition of the high order eight bits. CY means the carry flip-flop. = flag is not affected, 0 = flag is reset, 1 = flag is set, = flag is set according to the result of the operation. Flags S Z F5 H F3 P/V N C 2 2 2 0 1 1 1 2 2 2 V 1 0 1

Flag Notation:

General Purpose Arithmetic and CPU Control Groups

Mnemonic DAA Symbolic Operation Converts A into packed BCD following add or subtract with BCD operands. __ A A A 0-A __ CY CY Flags S Z F5 H F3 P/V N C P Opcode 76 543 210 00 100 111 Hex 27 No.of Bytes 1 No.of M Cycles 1 No.of T States 4 Comments

CPL NEG4 CCF SCF NOP HALT DI3 EI3 IM 04 IM 14 IM 24 Notes:

1 1

1 V

1 1 0

1 2 1

00 101 111 11 101 101 01 000 100 00 111 111

2F ED 44 3F

1 2 1

1 2 1

4 8 4

Ones complement. Twos complement. Complement carry flag.

Flag Notation:

00 110 111 37 1 1 4 CY 1 1 0 1 0 1 No operations 00 000 000 00 1 1 4 CPU halted 01 110 110 76 1 1 4 11 110 011 F3 1 1 4 IFF1 0 IFF2 0 11 111 011 FB 1 1 4 IFF1 1 IFF2 1 Set interrupt 11 101 101 ED 2 2 8 mode 0 01 000 110 46 Set interrupt 11 101 101 ED 2 2 8 mode 1 01 010 110 56 Set interrupt 11 101 101 ED 2 2 8 mode 2 01 011 110 5E The V symbol in the P/V flag column indicates that the P/V flags contains the overflow of the operation. Similarly the P symbol indicates parity. 1 F5 and F3 are a copy of bit 5 and 3 of register A _ 2 H contains the previous carry state (after instruction H C) 3 No interrupts are issued directly after a DI or EI. 4 This instruction has other unofficial opcodes, see Opcodes list. CY means the carry flip-flop. = flag is not affected, 0 = flag is reset, 1 = flag is set, = flag is set according to the result of the operation.

Rotate and Shift Group

Mnemonic RLCA RLA RRCA RRA RLC r Symbolic Operation Opcode No. of No. of No. of T 76 543 Hex Bytes M States Comments 210 Cycles 00 000 07 1 1 4 0 0 111 00 010 17 1 1 4 0 0 111 00 001 0F 1 1 4 0 0 111 00 011 1F 1 1 4 0 0 111 11 001 CB 2 2 8 r Reg. 0 P 0 011 000 B 00 000 r 11 001 CB 2 4 15 001 C 0 P 0 011 010 D 00 000 110 11 011 DD 4 6 23 011 E 0 P 0 101 CB 100 H 11 001 101 L 011 111 A d 00 000 110 11 111 FD 4 6 23 0 P 0 101 CB 11 001 011 d 00 000 110 11 011 DD 4 6 23 r (IX + d) 0 P 0 101 CB RLC r 11 001 (IX + d) r 011 d 00 000 r 11 111 FD 4 6 23 r (IY + d) 0 P 0 101 CB RLC r 11 001 (IY + d) r 011 d 00 000 r 010 Instruction format 0 P 0 001 and states are the 0 P 0 011 same as RLC. 0 P 0 100 Replace 000 with 0 P 0 110 new number. 0 P 0 101 0 P 0 111 0 P 0 11 101 ED 2 5 18 0 P 0 101 6F 01 101 111 11 101 ED 2 5 18 0 P 0 101 67 01 100 111 The P symbol in the P/V flag column indicates that the P/V flags contains the parity of the result. r means any of the registers A, B, C, D, E, H, L. * means unofficial instruction. CY means the carry flip-flop. = flag is not affected, 0 = flag is reset, 1 = flag is set, = flag is set according to the result of the operation. Flags S Z F5 H F3 P/V N C

RLC (HL)

RLC (IX + d)

RLC (IY + d)

LD r,RLC (IX + d)*

LD r,RLC (IY + d)*

RL m RRC m RR m SLA m SLL m* SRA m SRL m RLD

RRD

Notes:

Flag Notation:

Bit Manipulation Group

Mnemonic BIT b, r Z BIT b, (HL) BIT b, (IX + d)
5

Symbolic Operation _ rb ___ (HL)b _____ (IX + d)b

Flags S Z F5 H F3 P/V N C 1 1 1 2 1 2 1 2 1 3 4 0 3 4 0 3 4 0

Opcode 76 543 210 11 001 011 01 b r 11 001 011 01 b 110 11 011 101 11 001 011 d 01 b 110 11 111 101 11 001 011 d 01 b 110 11 001 011 11 b r 11 001 011 11 b 110 11 011 101 11 001 011 d 11 b 110 11 111 101 11 001 011 d 11 b 110 11 011 101 11 001 011 d 11 b r 11 111 101 11 001 011 d 11 b 10 r

Hex CB CB DD CB

No. of Bytes 2 2 4

No. of M Cycles 2 3 5

No. of T States 8 12 20

Comments r 000 001 010 011 100 101 111 Reg. B C D E H L A

Z Z

BIT b, (IY + d)5 Z

_____ (IY + d)b

2 1

3 4 0

FD CB

20

SET b, r

rb

CB

SET b, (HL) SET b, (IX + d)

(HL)b (IX + d)b

CB DD CB

2 4

4 6

15 23

b 000 001 010 011 100 101 110 111

Bit. 0 1 2 3 4 5 6 7

SET b, (IY + d)

(IY + d)b

FD CB

23

LD r,SET b, (IX + d)*

r (IX + d) rb 1 (IX + d) r

DD CB

23

LD r,SET b, (IY + d)*

r (IY + d) rb 1 (IY + d) r

FD CB

23

RES b, m

mb 0 m r, (HL), (IX+d), (IY+d)

To form new opcode replace 11 of SET b, s with 10. Flags and states are the same.

Notes:

Flag Notation:

The notation mb indicates bit b (0 to 7) of location m. BIT instructions are performed by an bitwise AND. 1 S is set if b = 7 and Z = 0 2 F5 is set if b = 5 and Z = 0 3 F3 is set if b = 3 and Z = 0 4 P/V is set like the Z flag 5 This instruction has other unofficial opcodes * means unofficial instruction. = flag is not affected, 0 = flag is reset, 1 = flag is set, = flag is set according to the result of the operation.

Input and Output Groups

Mnemonic IN A, (n) IN r, (C) IN (C)* or IN F, (C)* INI Symbolic Operation A (n) r (C) Flags S Z F5 H F3 P/V N C 0 0 P P 0 0 Opcode 76 543 210 11 011 011 n 11 101 101 01 r 000 11 101 101 01 110 000 11 101 101 10 100 010 11 101 101 10 110 010 Hex DB ED ED 70 ED A2 ED B2 No.of Bytes 2 2 2 2 No.of M Cycles 3 3 3 4 No.of T States 11 12 12 16 Comments r Reg. 000 B 001 C 010 D 011 E 100 H 101 L 111 A if B 0 if B = 0

INIR

IND

INDR

OUT (n), A OUT (C), r OUT (C), 0* OUTI

Just affects flags, value is lost. (HL) (C) HL HL + 1 B B-1 (HL) (C) HL HL + 1 B B-1 Repeat until B=0 (HL) (C) HL HL - 1 B B-1 (HL) (C) HL HL - 1 B B-1 Repeat until B=0 (n) A (C) (C) r 0

1 1 1 3 1 X 3 0

2 3 2 3

0 1

2 2

5 4

21 16

1 1 1 4 1 X 4 0

2 4 2 4

11 101 101 10 101 010 11 101 101 10 111 010

ED AA ED BA

16

0 1

2 2

5 4

21 16

if B 0 if B = 0

OTIR

OUTD

OTDR

Notes:

Flag Notation:

2 4 16 (C) (HL) 1 1 1 X 1 X X X HL HL + 1 B B-1 0 1 0 X 0 X X X 11 101 101 ED 2 5 21 (C) (HL) if B 0 10 110 011 B3 2 4 16 if B = 0 HL HL + 1 B B-1 Repeat until B=0 11 101 101 ED 2 4 16 (C) (HL) 1 1 1 X 1 X X X 10 101 011 AB HL HL - 1 B B-1 0 1 0 X 0 X X X 11 101 101 ED 2 5 21 (C) (HL) if B 0 10 111 011 BB 2 4 16 if B = 0 HL HL - 1 B B-1 Repeat until B=0 The V symbol in the P/V flag column indicates that the P/V flags contains the overflow of the operation. Similarly the P symbol indicates parity. r means any of the registers A, B, C, D, E, H, L. 1 flag is affected by the result of B B - 1 as in DEC B. 2 N is a copy bit 7 of the last value from the input (C). 3 this flag contains the carry of ( ( (C + 1) AND 255) + (C) ) 4 this flag contains the carry of ( ( (C - 1) AND 255) + (C) ) * means unofficial instruction. = flag is not affected, 0 = flag is reset, 1 = flag is set, X = flag is unknown, = flag is set according to the result of the operation.

11 010 011 n 11 101 101 01 r 001 11 101 101 01 110 001 11 101 101 10 100 011

D3 ED ED 71 ED A3

2 2 2

3 3 3

11 12 12

Jump Group
Mnemonic JP nn Symbolic Operation PC nn Flags S Z F5 H F3 P/V N C Opcode 76 543 210 11 000 011 n n 11 ccc 010 n n Hex C3 No.of Bytes 3 No.of M Cycles 3 No.of T States 10 Comments

JP cc, nn

if cc is true, PC nn

10

JR e JR ss, e

JP HL JP IX

PC PC + e if ss is true PC PC + e PC HL PC IX

00 011 000 e -2 00 ss 000 e -2 11 101 001 11 011 101 11 101 001 11 111 101 11 101 001 00 010 000 e -2

18

2 2 2

3 3 2 1 2

12 12 7 4 8

ccc 000 001 010 011 100 101 110 111

Condition NZ Z NC C PO PE P M

if ss is true if ss is false

E9 DD E9 FD E9 10

1 2

JP IY DJNZ e

PC

IY

Notes: Flag Notation:

2 2 8 B B-1 2 3 13 if B 0 PC PC + e e is a signed two-complement number in the range <-126, 129> e - 2 in the opcode provides an effective number of PC + e as PC incremented by 2 prior to the addition of e. = flag is not affected, 0 = flag is reset, 1 = flag is set, = flag is set according to the result of the operation.

ss Condition 111 C 110 NC 101 Z 100 NZ if B = 0 if B 0

Call and Return Group

Mnemonic CALL nn Symbolic Operation SP SP - 1 (SP) PCH SP SP - 1 (SP) PCL PC nn if cc is true, SP SP - 1 (SP) PCH SP SP - 1 (SP) PCL PC nn PCL (SP) SP SP + 1 PCH (SP) SP SP + 1 if cc is true, PCL (SP) SP SP + 1 PCH (SP) SP SP + 1 PCL (SP) SP SP + 1 PCH (SP) SP SP + 1 PCL SP PCH SP IFF1 SP (SP) SP (SP) PC (SP) SP + 1 (SP) SP + 1 IFF2 SP - 1 PCH SP - 1 PCL p Flags S Z F5 H F3 P/V N C Opcode 76 543 210 11 001 101 n n Hex CD No.of Bytes 3 No.of M Cycles 5 No.of T States 17 Comments

CALL cc, nn

11 ccc 100 n n

3 3

3 5

10 17

if cc is false if cc is true

RET

11 001 001

C9

10

RET cc

11 ccc 000

1 1

1 3

5 11

if cc is false if cc is true

RETI2

11 101 101 01 001 101

ED 4D

14

RETN1,2

11 101 101 01 000 101

ED 45

14

cc 000 001 010 011 100 101 110 111 t 000 001 010 011 100 101 110 111

Condition NZ Z NC C PO PE P M p 0h 8h 10h 18h 20h 28h 30h 38h

RST p

11 t 111

11

Notes:

This instruction has other unofficial opcodes, see Opcode list.

Flag Notation:

Instruction also IFF1 IFF2 = flag is not affected, 0 = flag is reset, 1 = flag is set, = flag is set according to the result of the operation.

Instructions sorted by opcode

If an EDxx instruction is not listed, it should operate as two NOPs. If a DDxx or FDxx instruction is not listed, it should operate as without the DD or FD prefix. An asterisk (*) after a instruction means it is unofficial.
00 01 n n 02 03 04 05 06 n 07 08 09 0A 0B 0C 0D 0E n 0F 10 n 11 n n 12 13 14 15 16 n 17 18 n 19 1A 1B 1C 1D 1E n 1F 20 n 21 n n 22 n n 23 24 25 26 n 27 28 n 29 2A n n 2B 2C 2D 2E n 2F 30 n 31 n n 32 n n 33 34 35 36 n 37 38 n 39 3A n n 3B 3C 3D 3E n 3F 40 41 42 43 44 45 NOP LD BC, nn LD (BC), A INC BC INC B DEC B LD B, n RLCA EX AF, AF ADD HL, BC LD A, (BC) DEC BC INC C DEC C LD C, n RRCA DJNZ PC + n LD DE, nn LD (DE), A INC DE INC D DEC D LD D, n RLA JR PC + n ADD HL, DE LD A, (DE) DEC DE INC E DEC E LD E, n RRA JR NZ, PC + n LD HL, nn LD (nn), HL INC HL INC H DEC H LD H, n DAA JR Z, PC + n ADD HL, HL LD HL, (nn) DEC HL INC L DEC L LD L, n CPL JR NC, PC + n LD SP, nn LD (nn), A INC SP INC (HL) DEC (HL) LD (HL), n SCF JR C, PC + n ADD HL, SP LD A, (nn) DEC SP INC A DEC A LD A, n CCF LD B, B LD B, C LD B, D LD B, E LD B, H LD B, L 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B LD B, (HL) LD B, A LD C, B LD C, C LD C, D LD C, E LD C, H LD C, L LD C, (HL) LD C, A LD D, B LD D, C LD D, D LD D, E LD D, H LD D, L LD D, (HL) LD D, A LD E, B LD E, C LD E, D LD E, E LD E, H LD E, L LD E, (HL) LD E, A LD H, B LD H, C LD H, D LD H, E LD H, H LD H, L LD H, (HL) LD H, A LD L, B LD L, C LD L, D LD L, E LD L, H LD L, L LD L, (HL) LD L, A LD (HL), B LD (HL), C LD (HL), D LD (HL), E LD (HL), H LD (HL), L HALT LD (HL), A LD A, B LD A, C LD A, D LD A, E LD A, H LD A, L LD A, (HL) LD A, A ADD A, B ADD A, C ADD A, D ADD A, E ADD A, H ADD A, L ADD A, (HL) ADD A, A ADC A, B ADC A, C ADC A, D ADC A, E 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 n n C3 n n C4 n n C5 C6 n C7 C8 C9 CA n n CB00 CB01 CB02 CB03 CB04 CB05 CB06 ADC A, H ADC A, L ADC A, (HL) ADC A, A SUB B SUB C SUB D SUB E SUB H SUB L SUB (HL) SUB A SBC A, B SBC A, C SBC A, D SBC A, E SBC A, H SBC A, L SBC A, (HL) SBC A, A AND B AND C AND D AND E AND H AND L AND (HL) AND A XOR B XOR C XOR D XOR E XOR H XOR L XOR (HL) XOR A OR B OR C OR D OR E OR H OR L OR (HL) OR A CP B CP C CP D CP E CP H CP L CP (HL) CP A RET NZ POP BC JP NZ, nn JP nn CALL NZ, nn PUSH BC ADD A, n RST 0h RET Z RET JP Z, nn RLC B RLC C RLC D RLC E RLC H RLC L RLC (HL)

CB07 CB08 CB09 CB0A CB0B CB0C CB0D CB0E CB0F CB10 CB11 CB12 CB13 CB14 CB15 CB16 CB17 CB18 CB19 CB1A CB1B CB1C CB1D CB1E CB1F CB20 CB21 CB22 CB23 CB24 CB25 CB26 CB27 CB28 CB29 CB2A CB2B CB2C CB2D CB2E CB2F CB30 CB31 CB32 CB33 CB34 CB35 CB36 CB37 CB38 CB39 CB3A CB3B CB3C CB3D CB3E CB3F CB40 CB41 CB42 CB43 CB44 CB45 CB46 CB47 CB48 CB49 CB4A CB4B CB4C CB4D CB4E CB4F CB50 CB51 CB52 CB53 CB54 CB55 CB56 CB57 CB58 CB59

RLC A RRC B RRC C RRC D RRC E RRC H RRC L RRC (HL) RRC A RL B RL C RL D RL E RL H RL L RL (HL) RL A RR B RR C RR D RR E RR H RR L RR (HL) RR A SLA B SLA C SLA D SLA E SLA H SLA L SLA (HL) SLA A SRA B SRA C SRA D SRA E SRA H SRA L SRA (HL) SRA A SLL B* SLL C* SLL D* SLL E* SLL H* SLL L* SLL (HL)* SLL A* SRL B SRL C SRL D SRL E SRL H SRL L SRL (HL) SRL A BIT 0, B BIT 0, C BIT 0, D BIT 0, E BIT 0, H BIT 0, L BIT 0, (HL) BIT 0, A BIT 1, B BIT 1, C BIT 1, D BIT 1, E BIT 1, H BIT 1, L BIT 1, (HL) BIT 1, A BIT 2, B BIT 2, C BIT 2, D BIT 2, E BIT 2, H BIT 2, L BIT 2, (HL) BIT 2, A BIT 3, B BIT 3, C

CB5A CB5B CB5C CB5D CB5E CB5F CB60 CB61 CB62 CB63 CB64 CB65 CB66 CB67 CB68 CB69 CB6A CB6B CB6C CB6D CB6E CB6F CB70 CB71 CB72 CB73 CB74 CB75 CB76 CB77 CB78 CB79 CB7A CB7B CB7C CB7D CB7E CB7F CB80 CB81 CB82 CB83 CB84 CB85 CB86 CB87 CB88 CB89 CB8A CB8B CB8C CB8D CB8E CB8F CB90 CB91 CB92 CB93 CB94 CB95 CB96 CB97 CB98 CB99 CB9A CB9B CB9C CB9D CB9E CB9F CBA0 CBA1 CBA2 CBA3 CBA4 CBA5 CBA6 CBA7 CBA8 CBA9 CBAA CBAB CBAC

BIT 3, D BIT 3, E BIT 3, H BIT 3, L BIT 3, (HL) BIT 3, A BIT 4, B BIT 4, C BIT 4, D BIT 4, E BIT 4, H BIT 4, L BIT 4, (HL) BIT 4, A BIT 5, B BIT 5, C BIT 5, D BIT 5, E BIT 5, H BIT 5, L BIT 5, (HL) BIT 5, A BIT 6, B BIT 6, C BIT 6, D BIT 6, E BIT 6, H BIT 6, L BIT 6, (HL) BIT 6, A BIT 7, B BIT 7, C BIT 7, D BIT 7, E BIT 7, H BIT 7, L BIT 7, (HL) BIT 7, A RES 0, B RES 0, C RES 0, D RES 0, E RES 0, H RES 0, L RES 0, (HL) RES 0, A RES 1, B RES 1, C RES 1, D RES 1, E RES 1, H RES 1, L RES 1, (HL) RES 1, A RES 2, B RES 2, C RES 2, D RES 2, E RES 2, H RES 2, L RES 2, (HL) RES 2, A RES 3, B RES 3, C RES 3, D RES 3, E RES 3, H RES 3, L RES 3, (HL) RES 3, A RES 4, B RES 4, C RES 4, D RES 4, E RES 4, H RES 4, L RES 4, (HL) RES 4, A RES 5, B RES 5, C RES 5, D RES 5, E RES 5, H

CBAD CBAE CBAF CBB0 CBB1 CBB2 CBB3 CBB4 CBB5 CBB6 CBB7 CBB8 CBB9 CBBA CBBB CBBC CBBD CBBE CBBF CBC0 CBC1 CBC2 CBC3 CBC4 CBC5 CBC6 CBC7 CBC8 CBC9 CBCA CBCB CBCC CBCD CBCE CBCF CBD0 CBD1 CBD2 CBD3 CBD4 CBD5 CBD6 CBD7 CBD8 CBD9 CBDA CBDB CBDC CBDD CBDE CBDF CBE0 CBE1 CBE2 CBE3 CBE4 CBE5 CBE6 CBE7 CBE8 CBE9 CBEA CBEB CBEC CBED CBEE CBEF CBF0 CBF1 CBF2 CBF3 CBF4 CBF5 CBF6 CBF7 CBF8 CBF9 CBFA CBFB CBFC CBFD CBFE CBFF

RES 5, L RES 5, (HL) RES 5, A RES 6, B RES 6, C RES 6, D RES 6, E RES 6, H RES 6, L RES 6, (HL) RES 6, A RES 7, B RES 7, C RES 7, D RES 7, E RES 7, H RES 7, L RES 7, (HL) RES 7, A SET 0, B SET 0, C SET 0, D SET 0, E SET 0, H SET 0, L SET 0, (HL) SET 0, A SET 1, B SET 1, C SET 1, D SET 1, E SET 1, H SET 1, L SET 1, (HL) SET 1, A SET 2, B SET 2, C SET 2, D SET 2, E SET 2, H SET 2, L SET 2, (HL) SET 2, A SET 3, B SET 3, C SET 3, D SET 3, E SET 3, H SET 3, L SET 3, (HL) SET 3, A SET 4, B SET 4, C SET 4, D SET 4, E SET 4, H SET 4, L SET 4, (HL) SET 4, A SET 5, B SET 5, C SET 5, D SET 5, E SET 5, H SET 5, L SET 5, (HL) SET 5, A SET 6, B SET 6, C SET 6, D SET 6, E SET 6, H SET 6, L SET 6, (HL) SET 6, A SET 7, B SET 7, C SET 7, D SET 7, E SET 7, H SET 7, L SET 7, (HL) SET 7, A

CC n n CD n n CE n CF D0 D1 D2 n n D3 n D4 n n D5 D6 n D7 D8 D9 DA n n DB n DC n n DD09 DD19 DD21 n n DD22 n n DD23 DD24 DD25 DD26 n DD29 DD2A n n DD2B DD2C DD2D DD2E n DD34 d DD35 d DD36 d n DD39 DD44 DD45 DD46 d DD4C DD4D DD4E d DD54 DD55 DD56 d DD5C DD5D DD5E d DD60 DD61 DD62 DD63 DD64 DD65 DD66 d DD67 DD68 DD69 DD6A DD6B DD6C DD6D DD6E d DD6F DD70 d DD71 d DD72 d DD73 d DD74 d DD75 d DD77 d DD7C DD7D DD7E d DD84 DD85 DD86 d DD8C DD8D DD8E d DD94 DD95 DD96 d DD9C

CALL Z, nn CALL nn ADC A, n RST 8h RET NC POP DE JP NC, nn OUT (n), A CALL NC, nn PUSH DE SUB n RST 10h RETC EXX JP C, nn IN A, (n) CALL C, nn ADD IX, BC ADD IX, DE LD IX, nn LD (nn), IX INC IX INC IXH* DEC IXH* LD IXH, n* ADD IX, IX LD IX, (nn) DEC IX INC IXL* DEC IXL* LD IXL, n* INC (IX + d) DEC (IX + d) LD (IX + d), n ADD IX, SP LD B, IXH* LD B, IXL* LD B, (IX + d) LD C, IXH* LD C, IXL* LD C, (IX + d) LD D, IXH* LD D, IXL* LD D, (IX + d) LD E, IXH* LD E, IXL* LD E, (IX + d) LD IXH, B* LD IXH, C* LD IXH, D* LD IXH, E* LD IXH, IXH* LD IXH, IXL* LD H, (IX + d) LD IXH, A* LD IXL, B* LD IXL, C* LD IXL, D* LD IXL, E* LD IXL, IXH* LD IXL, IXL* LD L, (IX + d) LD IXL, A* LD (IX + d), B LD (IX + d), C LD (IX + d), D LD (IX + d), E LD (IX + d), H LD (IX + d), L LD (IX + d), A LD A, IXH* LD A, IXL* LD A, (IX + d) ADD A, IXH* ADD A, IXL* ADD A, (IX + d) ADC A, IXH* ADC A, IXL* ADC A, (IX + d) SUB IXH* SUB IXL* SUB (IX + d) SBC A, IXH*

DD9D DD9E d DDA4 DDA5 DDA6 d DDAC DDAD DDAE d DDB4 DDB5 DDB6 d DDBC DDBD DDBE d DDCB d 00 DDCB d 01 DDCB d 02 DDCB d 03 DDCB d 04 DDCB d 05 DDCB d 06 DDCB d 07 DDCB d 08 DDCB d 09 DDCB d 0A DDCB d 0B DDCB d 0C DDCB d 0D DDCB d 0E DDCB d 0F DDCB d 10 DDCB d 11 DDCB d 12 DDCB d 13 DDCB d 14 DDCB d 15 DDCB d 16 DDCB d 17 DDCB d 18 DDCB d 19 DDCB d 1A DDCB d 1B DDCB d 1C DDCB d 1D DDCB d 1E DDCB d 1F DDCB d 20 DDCB d 21 DDCB d 22 DDCB d 23 DDCB d 24 DDCB d 25 DDCB d 26 DDCB d 27 DDCB d 28 DDCB d 29 DDCB d 2A DDCB d 2B DDCB d 2C DDCB d 2D DDCB d 2E DDCB d 2F DDCB d 30 DDCB d 31 DDCB d 32 DDCB d 33 DDCB d 34 DDCB d 35 DDCB d 36 DDCB d 37 DDCB d 38 DDCB d 39 DDCB d 3A DDCB d 3B DDCB d 3C DDCB d 3D DDCB d 3E DDCB d 3F DDCB d 40 DDCB d 41 DDCB d 42 DDCB d 43 DDCB d 44

SBC A, IXL* SBC A, (IX + d) AND IXH* AND IXL* AND (IX + d) XOR IXH* XOR IXL* XOR (IX + d) OR IXH* OR IXL* OR (IX + d) CP IXH* CP IXL* CP (IX + d) LD B, RLC (IX + d)* LD C, RLC (IX + d)* LD D, RLC (IX + d)* LD E, RLC (IX + d)* LD H, RLC (IX + d)* LD L, RLC (IX + d)* RLC (IX + d) LD A, RLC (IX + d)* LD B, RRC (IX + d)* LD C, RRC (IX + d)* LD D, RRC (IX + d)* LD E, RRC (IX + d)* LD H, RRC (IX + d)* LD L, RRC (IX + d)* RRC (IX + d) LD A, RRC (IX + d)* LD B, RL (IX + d)* LD C, RL (IX + d)* LD D, RL (IX + d)* LD E, RL (IX + d)* LD H, RL (IX + d)* LD L, RL (IX + d)* RL (IX + d) LD A, RL (IX + d)* LD B, RR (IX + d)* LD C, RR (IX + d)* LD D, RR (IX + d)* LD E, RR (IX + d)* LD H, RR (IX + d)* LD L, RR (IX + d)* RR (IX + d) LD A, RR (IX + d)* LD B, SLA (IX + d)* LD C, SLA (IX + d)* LD D, SLA (IX + d)* LD E, SLA (IX + d)* LD H, SLA (IX + d)* LD L, SLA (IX + d)* SLA (IX + d) LD A, SLA (IX + d)* LD B, SRA (IX + d)* LD C, SRA (IX + d)* LD D, SRA (IX + d)* LD E, SRA (IX + d)* LD H, SRA (IX + d)* LD L, SRA (IX + d)* SRA (IX + d) LD A, SRA (IX + d)* LD B, SLL (IX + d)* LD C, SLL (IX + d)* LD D, SLL (IX + d)* LD E, SLL (IX + d)* LD H, SLL (IX + d)* LD L, SLL (IX + d)* SLL (IX + d)* LD A, SLL (IX + d)* LD B, SRL (IX + d)* LD C, SRL (IX + d)* LD D, SRL (IX + d)* LD E, SRL (IX + d)* LD H, SRL (IX + d)* LD L, SRL (IX + d)* SRL (IX + d) LD A, SRL (IX + d)* BIT 0, (IX + d)* BIT 0, (IX + d)* BIT 0, (IX + d)* BIT 0, (IX + d)* BIT 0, (IX + d)*

DDCB d 45 DDCB d 46 DDCB d 47 DDCB d 48 DDCB d 49 DDCB d 4A DDCB d 4B DDCB d 4C DDCB d 4D DDCB d 4E DDCB d 4F DDCB d 50 DDCB d 51 DDCB d 52 DDCB d 53 DDCB d 54 DDCB d 55 DDCB d 56 DDCB d 57 DDCB d 58 DDCB d 59 DDCB d 5A DDCB d 5B DDCB d 5C DDCB d 5D DDCB d 5E DDCB d 5F DDCB d 60 DDCB d 61 DDCB d 62 DDCB d 63 DDCB d 64 DDCB d 65 DDCB d 66 DDCB d 67 DDCB d 68 DDCB d 69 DDCB d 6A DDCB d 6B DDCB d 6C DDCB d 6D DDCB d 6E DDCB d 6F DDCB d 70 DDCB d 71 DDCB d 72 DDCB d 73 DDCB d 74 DDCB d 75 DDCB d 76 DDCB d 77 DDCB d 78 DDCB d 79 DDCB d 7A DDCB d 7B DDCB d 7C DDCB d 7D DDCB d 7E DDCB d 7F DDCB d 80 DDCB d 81 DDCB d 82 DDCB d 83 DDCB d 84 DDCB d 85 DDCB d 86 DDCB d 87 DDCB d 88 DDCB d 89 DDCB d 8A DDCB d 8B DDCB d 8C DDCB d 8D DDCB d 8E DDCB d 8F DDCB d 90 DDCB d 91 DDCB d 92 DDCB d 93 DDCB d 94 DDCB d 95 DDCB d 96 DDCB d 97

BIT 0, (IX + d)* BIT 0, (IX + d) BIT 0, (IX + d)* BIT 1, (IX + d)* BIT 1, (IX + d)* BIT 1, (IX + d)* BIT 1, (IX + d)* BIT 1, (IX + d)* BIT 1, (IX + d)* BIT 1, (IX + d) BIT 1, (IX + d)* BIT 2, (IX + d)* BIT 2, (IX + d)* BIT 2, (IX + d)* BIT 2, (IX + d)* BIT 2, (IX + d)* BIT 2, (IX + d)* BIT 2, (IX + d) BIT 2, (IX + d)* BIT 3, (IX + d)* BIT 3, (IX + d)* BIT 3, (IX + d)* BIT 3, (IX + d)* BIT 3, (IX + d)* BIT 3, (IX + d)* BIT 3, (IX + d) BIT 3, (IX + d)* BIT 4, (IX + d)* BIT 4, (IX + d)* BIT 4, (IX + d)* BIT 4, (IX + d)* BIT 4, (IX + d)* BIT 4, (IX + d)* BIT 4, (IX + d) BIT 4, (IX + d)* BIT 5, (IX + d)* BIT 5, (IX + d)* BIT 5, (IX + d)* BIT 5, (IX + d)* BIT 5, (IX + d)* BIT 5, (IX + d)* BIT 5, (IX + d) BIT 5, (IX + d)* BIT 6, (IX + d)* BIT 6, (IX + d)* BIT 6, (IX + d)* BIT 6, (IX + d)* BIT 6, (IX + d)* BIT 6, (IX + d)* BIT 6, (IX + d) BIT 6, (IX + d)* BIT 7, (IX + d)* BIT 7, (IX + d)* BIT 7, (IX + d)* BIT 7, (IX + d)* BIT 7, (IX + d)* BIT 7, (IX + d)* BIT 7, (IX + d) BIT 7, (IX + d)* LD B, RES 0, (IX + d)* LD C, RES 0, (IX + d)* LD D, RES 0, (IX + d)* LD E, RES 0, (IX + d)* LD H, RES 0, (IX + d)* LD L, RES 0, (IX + d)* RES 0, (IX + d) LD A, RES 0, (IX + d)* LD B, RES 1, (IX + d)* LD C, RES 1, (IX + d)* LD D, RES 1, (IX + d)* LD E, RES 1, (IX + d)* LD H, RES 1, (IX + d)* LD L, RES 1, (IX + d)* RES 1, (IX + d) LD A, RES 1, (IX + d)* LD B, RES 2, (IX + d)* LD C, RES 2, (IX + d)* LD D, RES 2, (IX + d)* LD E, RES 2, (IX + d)* LD H, RES 2, (IX + d)* LD L, RES 2, (IX + d)* RES 2, (IX + d) LD A, RES 2, (IX + d)*

DDCB d 98 DDCB d 99 DDCB d 9A DDCB d 9B DDCB d 9C DDCB d 9D DDCB d 9E DDCB d 9F DDCB d A0 DDCB d A1 DDCB d A2 DDCB d A3 DDCB d A4 DDCB d A5 DDCB d A6 DDCB d A7 DDCB d A8 DDCB d A9 DDCB d AA DDCB d AB DDCB d AC DDCB d AD DDCB d AE DDCB d AF DDCB d B0 DDCB d B1 DDCB d B2 DDCB d B3 DDCB d B4 DDCB d B5 DDCB d B6 DDCB d B7 DDCB d B8 DDCB d B9 DDCB d BA DDCB d BB DDCB d BC DDCB d BD DDCB d BE DDCB d BF DDCB d C0 DDCB d C1 DDCB d C2 DDCB d C3 DDCB d C4 DDCB d C5 DDCB d C6 DDCB d C7 DDCB d C8 DDCB d C9 DDCB d CA DDCB d CB DDCB d CC DDCB d CD DDCB d CE DDCB d CF DDCB d D0 DDCB d D1 DDCB d D2 DDCB d D3 DDCB d D4 DDCB d D5 DDCB d D6 DDCB d D7 DDCB d D8 DDCB d D9 DDCB d DA DDCB d DB DDCB d DC DDCB d DD DDCB d DE DDCB d DF DDCB d E0 DDCB d E1 DDCB d E2 DDCB d E3 DDCB d E4 DDCB d E5 DDCB d E6 DDCB d E7 DDCB d E8 DDCB d E9 DDCB d EA

LD B, RES 3, (IX + d)* LD C, RES 3, (IX + d)* LD D, RES 3, (IX + d)* LD E, RES 3, (IX + d)* LD H, RES 3, (IX + d)* LD L, RES 3, (IX + d)* RES 3, (IX + d) LD A, RES 3, (IX + d)* LD B, RES 4, (IX + d)* LD C, RES 4, (IX + d)* LD D, RES 4, (IX + d)* LD E, RES 4, (IX + d)* LD H, RES 4, (IX + d)* LD L, RES 4, (IX + d)* RES 4, (IX + d) LD A, RES 4, (IX + d)* LD B, RES 5, (IX + d)* LD C, RES 5, (IX + d)* LD D, RES 5, (IX + d)* LD E, RES 5, (IX + d)* LD H, RES 5, (IX + d)* LD L, RES 5, (IX + d)* RES 5, (IX + d) LD A, RES 5, (IX + d)* LD B, RES 6, (IX + d)* LD C, RES 6, (IX + d)* LD D, RES 6, (IX + d)* LD E, RES 6, (IX + d)* LD H, RES 6, (IX + d)* LD L, RES 6, (IX + d)* RES 6, (IX + d) LD A, RES 6, (IX + d)* LD B, RES 7, (IX + d)* LD C, RES 7, (IX + d)* LD D, RES 7, (IX + d)* LD E, RES 7, (IX + d)* LD H, RES 7, (IX + d)* LD L, RES 7, (IX + d)* RES 7, (IX + d) LD A, RES 7, (IX + d)* LD B, SET 0, (IX + d)* LD C, SET 0, (IX + d)* LD D, SET 0, (IX + d)* LD E, SET 0, (IX + d)* LD H, SET 0, (IX + d)* LD L, SET 0, (IX + d)* SET 0, (IX + d) LD A, SET 0, (IX + d)* LD B, SET 1, (IX + d)* LD C, SET 1, (IX + d)* LD D, SET 1, (IX + d)* LD E, SET 1, (IX + d)* LD H, SET 1, (IX + d)* LD L, SET 1, (IX + d)* SET 1, (IX + d) LD A, SET 1, (IX + d)* LD B, SET 2, (IX + d)* LD C, SET 2, (IX + d)* LD D, SET 2, (IX + d)* LD E, SET 2, (IX + d)* LD H, SET 2, (IX + d)* LD L, SET 2, (IX + d)* SET 2, (IX + d) LD A, SET 2, (IX + d)* LD B, SET 3, (IX + d)* LD C, SET 3, (IX + d)* LD D, SET 3, (IX + d)* LD E, SET 3, (IX + d)* LD H, SET 3, (IX + d)* LD L, SET 3, (IX + d)* SET 3, (IX + d) LD A, SET 3, (IX + d)* LD B, SET 4, (IX + d)* LD C, SET 4, (IX + d)* LD D, SET 4, (IX + d)* LD E, SET 4, (IX + d)* LD H, SET 4, (IX + d)* LD L, SET 4, (IX + d)* SET 4, (IX + d) LD A, SET 4, (IX + d)* LD B, SET 5, (IX + d)* LD C, SET 5, (IX + d)* LD D, SET 5, (IX + d)*

DDCB d EB DDCB d EC DDCB d ED DDCB d EE DDCB d EF DDCB d F0 DDCB d F1 DDCB d F2 DDCB d F3 DDCB d F4 DDCB d F5 DDCB d F6 DDCB d F7 DDCB d F8 DDCB d F9 DDCB d FA DDCB d FB DDCB d FC DDCB d FD DDCB d FE DDCB d FF DDE1 DDE3 DDE5 DDE9 DDF9 DE n DF E0 E1 E2 n n E3 E4 n n E5 E6 n E7 E8 E9 EA n n EB EC n n ED40 ED41 ED42 ED43 n n ED44 ED45 ED46 ED47 ED48 ED49 ED4A ED4B n n ED4C ED4D ED4E ED4F ED50 ED51 ED52 ED53 n n ED54 ED55 ED56 ED57 ED58 ED59 ED5A ED5B n n ED5C ED5D ED5E ED5F ED60 ED61 ED62 ED63 n n ED64 ED65 ED66 ED67 ED68 ED69

LD E, SET 5, (IX + d)* LD H, SET 5, (IX + d)* LD L, SET 5, (IX + d)* SET 5, (IX + d) LD A, SET 5, (IX + d)* LD B, SET 6, (IX + d)* LD C, SET 6, (IX + d)* LD D, SET 6, (IX + d)* LD E, SET 6, (IX + d)* LD H, SET 6, (IX + d)* LD L, SET 6, (IX + d)* SET 6, (IX + d) LD A, SET 6, (IX + d)* LD B, SET 7, (IX + d)* LD C, SET 7, (IX + d)* LD D, SET 7, (IX + d)* LD E, SET 7, (IX + d)* LD H, SET 7, (IX + d)* LD L, SET 7, (IX + d)* SET 7, (IX + d) LD A, SET 7, (IX + d)* POP IX EX (SP), IX PUSH IX JP (IX) LD SP, IX SBC A, n RST 18h RET PO POP HL JP PO, nn EX (SP), HL CALL PO, nn PUSH HL AND n RST 20h RET PE JP (HL) JP PE, (nn) EX DE, HL CALL PE, nn IN B, (C) OUT (C), B SBC HL, BC LD (nn), BC NEG RETN IM 0 LD I, A IN C, (C) OUT (C), C ADC HL, BC LD BC, (nn) NEG* RETI IM 0/1* LD R, A IN D, (C) OUT (C), D SBC HL, DE LD (nn), DE NEG* RETN* IM 1 LD A, I IN E, (C) OUT (C), E ADC HL, DE LD DE, (nn) NEG* RETN* IM 2 LD A, R IN H, (C) OUT (C), H SBC HL, HL LD (nn), HL NEG* RETN* IM 0* RRD IN L, (C) OUT (C), L

ED6A ED6B n n ED6C ED6D ED6E ED6F ED70 ED71 ED72 ED73 n n ED74 ED75 ED76 ED78 ED79 ED7A ED7B n n ED7C ED7D ED7E EDA0 EDA1 EDA2 EDA3 EDA8 EDA9 EDAA EDAB EDB0 EDB1 EDB2 EDB3 EDB8 EDB9 EDBA EDBB EE n EF F0 F1 F2 n n F3 F4 n n F5 F6 n F7 F8 F9 FA n n FB FC n n FD09 FD19 FD21 n n FD22 n n FD23 FD24 FD25 FD26 n FD29 FD2A n n FD2B FD2C FD2D FD2E n FD34 d FD35 d FD36 d n FD39 FD44 FD45 FD46 d FD4C FD4D FD4E d FD54 FD55 FD56 d FD5C FD5D FD5E d FD60 FD61

ADC HL, HL LD HL, (nn) NEG* RETN* IM 0/1* RLD IN (C)* / IN F, (C)* OUT (C), 0* SBC HL, SP LD (nn), SP NEG* RETN* IM 1* IN A, (C) OUT (C), A ADC HL, SP LD SP, (nn) NEG* RETN* IM 2* LDI CPI INI OUTI LDD CPD IND OUTD LDIR CPIR INIR OTIR LDDR CPDR INDR OTDR XOR n RST 28h RET P POP AF JP P, nn DI CALL P, nn PUSH AF OR n RST 30h RET M LD SP, HL JP M, nn EI CALL M, nn ADD IY, BC ADD IY, DE LD IY, nn LD (nn), IY INC IY INC IYH* DEC IYH* LD IYH, n* ADD IY, IY LD IY, (nn) DEC IY INC IYL* DEC IYL* LD IYL, n* INC (IY + d) DEC (IY + d) LD (IY + d), n ADD IY, SP LD B, IYH* LD B, IYL* LD B, (IY + d) LD C, IYH* LD C, IYL* LD C, (IY + d) LD D, IYH* LD D, IYL* LD D, (IY + d) LD E, IYH* LD E, IYL* LD E, (IY + d) LD IYH, B* LD IYH, C*

FD62 FD63 FD64 FD65 FD66 d FD67 FD68 FD69 FD6A FD6B FD6C FD6D FD6E d FD6F FD70 d FD71 d FD72 d FD73 d FD74 d FD75 d FD77 d FD7C FD7D FD7E d FD84 FD85 FD86 d FD8C FD8D FD8E d FD94 FD95 FD96 d FD9C FD9D FD9E d FDA4 FDA5 FDA6 d FDAC FDAD FDAE d FDB4 FDB5 FDB6 d FDBC FDBD FDBE d FDCB d 00 FDCB d 01 FDCB d 02 FDCB d 03 FDCB d 04 FDCB d 05 FDCB d 06 FDCB d 07 FDCB d 08 FDCB d 09 FDCB d 0A FDCB d 0B FDCB d 0C FDCB d 0D FDCB d 0E FDCB d 0F FDCB d 10 FDCB d 11 FDCB d 12 FDCB d 13 FDCB d 14 FDCB d 15 FDCB d 16 FDCB d 17 FDCB d 18 FDCB d 19 FDCB d 1A FDCB d 1B FDCB d 1C FDCB d 1D FDCB d 1E FDCB d 1F FDCB d 20 FDCB d 21 FDCB d 22

LD IYH, D* LD IYH, E* LD IYH, IYH* LD IYH, IYL* LD H, (IY + d) LD IYH, A* LD IYL, B* LD IYL, C* LD IYL, D* LD IYL, E* LD IYL, IYH* LD IYL, IYL* LD L, (IY + d) LD IYL, A* LD (IY + d), B LD (IY + d), C LD (IY + d), D LD (IY + d), E LD (IY + d), H LD (IY + d), L LD (IY + d), A LD A, IYH* LD A, IYL* LD A, (IY + d) ADD A, IYH* ADD A, IYL* ADD A, (IY + d) ADC A, IYH* ADC A, IYL* ADC A, (IY + d) SUB IYH* SUB IYL* SUB (IY + d) SBC A, IYH* SBC A, IYL* SBC A, (IY + d) AND IYH* AND IYL* AND (IY + d) XOR IYH* XOR IYL* XOR (IY + d) OR IYH* OR IYL* OR (IY + d) CP IYH* CP IYL* CP (IY + d) LD B, RLC (IY + d)* LD C, RLC (IY + d)* LD D, RLC (IY + d)* LD E, RLC (IY + d)* LD H, RLC (IY + d)* LD L, RLC (IY + d)* RLC (IY + d) LD A, RLC (IY + d)* LD B, RRC (IY + d)* LD C, RRC (IY + d)* LD D, RRC (IY + d)* LD E, RRC (IY + d)* LD H, RRC (IY + d)* LD L, RRC (IY + d)* RRC (IY + d) LD A, RRC (IY + d)* LD B, RL (IY + d)* LD C, RL (IY + d)* LD D, RL (IY + d)* LD E, RL (IY + d)* LD H, RL (IY + d)* LD L, RL (IY + d)* RL (IY + d) LD A, RL (IY + d)* LD B, RR (IY + d)* LD C, RR (IY + d)* LD D, RR (IY + d)* LD E, RR (IY + d)* LD H, RR (IY + d)* LD L, RR (IY + d)* RR (IY + d) LD A, RR (IY + d)* LD B, SLA (IY + d)* LD C, SLA (IY + d)* LD D, SLA (IY + d)*

FDCB d 23 FDCB d 24 FDCB d 25 FDCB d 26 FDCB d 27 FDCB d 28 FDCB d 29 FDCB d 2A FDCB d 2B FDCB d 2C FDCB d 2D FDCB d 2E FDCB d 2F FDCB d 30 FDCB d 31 FDCB d 32 FDCB d 33 FDCB d 34 FDCB d 35 FDCB d 36 FDCB d 37 FDCB d 38 FDCB d 39 FDCB d 3A FDCB d 3B FDCB d 3C FDCB d 3D FDCB d 3E FDCB d 3F FDCB d 40 FDCB d 41 FDCB d 42 FDCB d 43 FDCB d 44 FDCB d 45 FDCB d 46 FDCB d 47 FDCB d 48 FDCB d 49 FDCB d 4A FDCB d 4B FDCB d 4C FDCB d 4D FDCB d 4E FDCB d 4F FDCB d 50 FDCB d 51 FDCB d 52 FDCB d 53 FDCB d 54 FDCB d 55 FDCB d 56 FDCB d 57 FDCB d 58 FDCB d 59 FDCB d 5A FDCB d 5B FDCB d 5C FDCB d 5D FDCB d 5E FDCB d 5F FDCB d 60 FDCB d 61 FDCB d 62 FDCB d 63 FDCB d 64 FDCB d 65 FDCB d 66 FDCB d 67 FDCB d 68 FDCB d 69 FDCB d 6A FDCB d 6B FDCB d 6C FDCB d 6D FDCB d 6E FDCB d 6F FDCB d 70 FDCB d 71 FDCB d 72 FDCB d 73 FDCB d 74 FDCB d 75

LD E, SLA (IY + d)* LD H, SLA (IY + d)* LD L, SLA (IY + d)* SLA (IY + d) LD A, SLA (IY + d)* LD B, SRA (IY + d)* LD C, SRA (IY + d)* LD D, SRA (IY + d)* LD E, SRA (IY + d)* LD H, SRA (IY + d)* LD L, SRA (IY + d)* SRA (IY + d) LD A, SRA (IY + d)* LD B, SLL (IY + d)* LD C, SLL (IY + d)* LD D, SLL (IY + d)* LD E, SLL (IY + d)* LD H, SLL (IY + d)* LD L, SLL (IY + d)* SLL (IY + d)* LD A, SLL (IY + d)* LD B, SRL (IY + d)* LD C, SRL (IY + d)* LD D, SRL (IY + d)* LD E, SRL (IY + d)* LD H, SRL (IY + d)* LD L, SRL (IY + d)* SRL (IY + d) LD A, SRL (IY + d)* BIT 0, (IY + d)* BIT 0, (IY + d)* BIT 0, (IY + d)* BIT 0, (IY + d)* BIT 0, (IY + d)* BIT 0, (IY + d)* BIT 0, (IY + d) BIT 0, (IY + d)* BIT 1, (IY + d)* BIT 1, (IY + d)* BIT 1, (IY + d)* BIT 1, (IY + d)* BIT 1, (IY + d)* BIT 1, (IY + d)* BIT 1, (IY + d) BIT 1, (IY + d)* BIT 2, (IY + d)* BIT 2, (IY + d)* BIT 2, (IY + d)* BIT 2, (IY + d)* BIT 2, (IY + d)* BIT 2, (IY + d)* BIT 2, (IY + d) BIT 2, (IY + d)* BIT 3, (IY + d)* BIT 3, (IY + d)* BIT 3, (IY + d)* BIT 3, (IY + d)* BIT 3, (IY + d)* BIT 3, (IY + d)* BIT 3, (IY + d) BIT 3, (IY + d)* BIT 4, (IY + d)* BIT 4, (IY + d)* BIT 4, (IY + d)* BIT 4, (IY + d)* BIT 4, (IY + d)* BIT 4, (IY + d)* BIT 4, (IY + d) BIT 4, (IY + d)* BIT 5, (IY + d)* BIT 5, (IY + d)* BIT 5, (IY + d)* BIT 5, (IY + d)* BIT 5, (IY + d)* BIT 5, (IY + d)* BIT 5, (IY + d) BIT 5, (IY + d)* BIT 6, (IY + d)* BIT 6, (IY + d)* BIT 6, (IY + d)* BIT 6, (IY + d)* BIT 6, (IY + d)* BIT 6, (IY + d)*

FDCB d 76 FDCB d 77 FDCB d 78 FDCB d 79 FDCB d 7A FDCB d 7B FDCB d 7C FDCB d 7D FDCB d 7E FDCB d 7F FDCB d 80 FDCB d 81 FDCB d 82 FDCB d 83 FDCB d 84 FDCB d 85 FDCB d 86 FDCB d 87 FDCB d 88 FDCB d 89 FDCB d 8A FDCB d 8B FDCB d 8C FDCB d 8D FDCB d 8E FDCB d 8F FDCB d 90 FDCB d 91 FDCB d 92 FDCB d 93 FDCB d 94 FDCB d 95 FDCB d 96 FDCB d 97 FDCB d 98 FDCB d 99 FDCB d 9A FDCB d 9B FDCB d 9C FDCB d 9D FDCB d 9E FDCB d 9F FDCB d A0 FDCB d A1 FDCB d A2 FDCB d A3 FDCB d A4 FDCB d A5 FDCB d A6 FDCB d A7 FDCB d A8 FDCB d A9 FDCB d AA FDCB d AB FDCB d AC FDCB d AD FDCB d AE FDCB d AF FDCB d B0 FDCB d B1 FDCB d B2 FDCB d B3 FDCB d B4 FDCB d B5 FDCB d B6 FDCB d B7 FDCB d B8 FDCB d B9 FDCB d BA FDCB d BB FDCB d BC FDCB d BD FDCB d BE FDCB d BF FDCB d C0 FDCB d C1 FDCB d C2 FDCB d C3 FDCB d C4 FDCB d C5 FDCB d C6 FDCB d C7 FDCB d C8

BIT 6, (IY + d) BIT 6, (IY + d)* BIT 7, (IY + d)* BIT 7, (IY + d)* BIT 7, (IY + d)* BIT 7, (IY + d)* BIT 7, (IY + d)* BIT 7, (IY + d)* BIT 7, (IY + d) BIT 7, (IY + d)* LD B, RES 0, (IY + d)* LD C, RES 0, (IY + d)* LD D, RES 0, (IY + d)* LD E, RES 0, (IY + d)* LD H, RES 0, (IY + d)* LD L, RES 0, (IY + d)* RES 0, (IY + d) LD A, RES 0, (IY + d)* LD B, RES 1, (IY + d)* LD C, RES 1, (IY + d)* LD D, RES 1, (IY + d)* LD E, RES 1, (IY + d)* LD H, RES 1, (IY + d)* LD L, RES 1, (IY + d)* RES 1, (IY + d) LD A, RES 1, (IY + d)* LD B, RES 2, (IY + d)* LD C, RES 2, (IY + d)* LD D, RES 2, (IY + d)* LD E, RES 2, (IY + d)* LD H, RES 2, (IY + d)* LD L, RES 2, (IY + d)* RES 2, (IY + d) LD A, RES 2, (IY + d)* LD B, RES 3, (IY + d)* LD C, RES 3, (IY + d)* LD D, RES 3, (IY + d)* LD E, RES 3, (IY + d)* LD H, RES 3, (IY + d)* LD L, RES 3, (IY + d)* RES 3, (IY + d) LD A, RES 3, (IY + d)* LD B, RES 4, (IY + d)* LD C, RES 4, (IY + d)* LD D, RES 4, (IY + d)* LD E, RES 4, (IY + d)* LD H, RES 4, (IY + d)* LD L, RES 4, (IY + d)* RES 4, (IY + d) LD A, RES 4, (IY + d)* LD B, RES 5, (IY + d)* LD C, RES 5, (IY + d)* LD D, RES 5, (IY + d)* LD E, RES 5, (IY + d)* LD H, RES 5, (IY + d)* LD L, RES 5, (IY + d)* RES 5, (IY + d) LD A, RES 5, (IY + d)* LD B, RES 6, (IY + d)* LD C, RES 6, (IY + d)* LD D, RES 6, (IY + d)* LD E, RES 6, (IY + d)* LD H, RES 6, (IY + d)* LD L, RES 6, (IY + d)* RES 6, (IY + d) LD A, RES 6, (IY + d)* LD B, RES 7, (IY + d)* LD C, RES 7, (IY + d)* LD D, RES 7, (IY + d)* LD E, RES 7, (IY + d)* LD H, RES 7, (IY + d)* LD L, RES 7, (IY + d)* RES 7, (IY + d) LD A, RES 7, (IY + d)* LD B, SET 0, (IY + d)* LD C, SET 0, (IY + d)* LD D, SET 0, (IY + d)* LD E, SET 0, (IY + d)* LD H, SET 0, (IY + d)* LD L, SET 0, (IY + d)* SET 0, (IY + d) LD A, SET 0, (IY + d)* LD B, SET 1, (IY + d)*

FDCB d C9 FDCB d CA FDCB d CB FDCB d CC FDCB d CD FDCB d CE FDCB d CF FDCB d D0 FDCB d D1 FDCB d D2 FDCB d D3 FDCB d D4 FDCB d D5 FDCB d D6 FDCB d D7 FDCB d D8 FDCB d D9 FDCB d DA FDCB d DB FDCB d DC FDCB d DD FDCB d DE FDCB d DF FDCB d E0 FDCB d E1 FDCB d E2 FDCB d E3 FDCB d E4 FDCB d E5 FDCB d E6 FDCB d E7 FDCB d E8 FDCB d E9 FDCB d EA FDCB d EB FDCB d EC FDCB d ED FDCB d EE FDCB d EF FDCB d F0 FDCB d F1 FDCB d F2 FDCB d F3 FDCB d F4 FDCB d F5 FDCB d F6 FDCB d F7 FDCB d F8 FDCB d F9 FDCB d FA FDCB d FB FDCB d FC FDCB d FD FDCB d FE FDCB d FF FDE1 FDE3 FDE5 FDE9 FDF9 FE n FF

LD C, SET 1, (IY + d)* LD D, SET 1, (IY + d)* LD E, SET 1, (IY + d)* LD H, SET 1, (IY + d)* LD L, SET 1, (IY + d)* SET 1, (IY + d) LD A, SET 1, (IY + d)* LD B, SET 2, (IY + d)* LD C, SET 2, (IY + d)* LD D, SET 2, (IY + d)* LD E, SET 2, (IY + d)* LD H, SET 2, (IY + d)* LD L, SET 2, (IY + d)* SET 2, (IY + d) LD A, SET 2, (IY + d)* LD B, SET 3, (IY + d)* LD C, SET 3, (IY + d)* LD D, SET 3, (IY + d)* LD E, SET 3, (IY + d)* LD H, SET 3, (IY + d)* LD L, SET 3, (IY + d)* SET 3, (IY + d) LD A, SET 3, (IY + d)* LD B, SET 4, (IY + d)* LD C, SET 4, (IY + d)* LD D, SET 4, (IY + d)* LD E, SET 4, (IY + d)* LD H, SET 4, (IY + d)* LD L, SET 4, (IY + d)* SET 4, (IY + d) LD A, SET 4, (IY + d)* LD B, SET 5, (IY + d)* LD C, SET 5, (IY + d)* LD D, SET 5, (IY + d)* LD E, SET 5, (IY + d)* LD H, SET 5, (IY + d)* LD L, SET 5, (IY + d)* SET 5, (IY + d) LD A, SET 5, (IY + d)* LD B, SET 6, (IY + d)* LD C, SET 6, (IY + d)* LD D, SET 6, (IY + d)* LD E, SET 6, (IY + d)* LD H, SET 6, (IY + d)* LD L, SET 6, (IY + d)* SET 6, (IY + d) LD A, SET 6, (IY + d)* LD B, SET 7, (IY + d)* LD C, SET 7, (IY + d)* LD D, SET 7, (IY + d)* LD E, SET 7, (IY + d)* LD H, SET 7, (IY + d)* LD L, SET 7, (IY + d)* SET 7, (IY + d) LD A, SET 7, (IY + d)* POP IY EX (SP), IY PUSH IY JP (IY) LD SP, IY CP n RST 38h