`timescale 1ns/1ns

module Mux(a,b,c,d,e,Clk,Sel,Out);
input [7:0] a; input [7:0] b; input [7:0] c; input [7:0] d; input [7:0] e;
input [2:0] Sel;
input Clk;
output reg [7:0] Out;
initial
begin
Out = 0;
end
Control Controller(Clk,Sel);
always@(Clk)
begin
case ({Sel[2],Sel[1],Sel[0]})
3'b000:
3'b001:
3'b010:
3'b011:
3'b100:

Out
Out
Out
Out
Out

=
=
=
=
=

a;
b;
c;
d;
e;

default:Out = 8'bxxxxxxxx;
endcase
end
endmodule