CMOS Differential Amplifier

1. Current Equations of Differential Amplifier

V
DD
V
SS
V
C
V
SS
V
SS
I
SS
V
G1
V
G2
V
GS2
V
GS1
I
D1
I
D2
(a)
+
+
+
+
E+=V
ID
/2
E-=-V
ID
/2
(1)
(10)
(2)
V
G1
V
G2
VIC
V
ID
(7)
(b)


Figure 1. General MOS Differential Amplifier: (a) Schematic Diagram, (b) Input Gate Voltages
Implementation.

Figure 1(a) shows the schematic diagram of a typical differential amplifier. The differential input
is given by:


) V V ( ) V V ( V V V
C GS2 C GS1 G2 G1 ID
+ + = = --(1)

2
D2
1
D1
TN GS2 TN GS1 GS2 GS1 ID
I 2 I 2
) V V ( ) V V ( V V V

= = = --(2)

The common-mode input signal is given by:

2
V V
V
G2 G1
IC
+
= --(3)


The input voltages in term of V
ID
and V
IC
are given by


2 / V V V
ID IC G1
+ = --(4)


2 / V V V
ID IC G2
= --(5)
1


Figure 1(b) shows the implementation of the 2 gate voltages in terms of the differential and common mode
voltages. Its PSpice implementation using voltage controlled voltage source is given below:

VID 7 0 DC 0V
E+ 1 10 7 0 0.5
E- 2 10 7 0 -0.5
VIC 10 0 DC 0V

Two special cases of input gate signals are of interests : pure differential and pure common mode input
signals. Pure differential input signals mean V
IC
=0, from equation (4) and (5);

2 / V V
2 / V V
ID G2
ID G1
=
=

This case is of interest when studying the differential gain of differential amplifier, see Figure 2(a). Pure
common-mode input signals mean V
ID
=0, from equation (4) and (5);

IC G2
IC G1
V V
V V
=
=

This case is of interest when studying the common-mode gain of differential amplifier, see Figure 5(a).


Assume both transistor drivers are matched, that is:

= =
2 1



D2 D1
ID
I 2 I 2
V = --(6)

D2 D1 ID
I I V 2 / = --(7)

The transistor currents satisfy the following equations:

D2 D1 SS
I I I + = --(8)

D2 D1 OD
I I I = --(9)

2 / ) I I ( I
OD SS D1
+ = --(10)

2 / ) I I ( I
OD SS D2
= --(11)


Substituting Eq(10) and Eq(11) to Eq(7)

2 / ) I I ( 2 / ) I I ( V 2 /
OD SS OD SS ID
+ = --(12)

2
Normalizing by I
SS


)
I
I
1
I
I
1 ( V
I
SS
OD
SS
OD
ID
SS
+ =

--(13)

To simplify the equation, let

SS
OD
ID
SS
I
I
= y and , V
I
= x

--(14)

The equation reduces to:

y - 1 y + 1 = x

Solve for y,

2 2
y - 1 2 - 2 = y) 1 ( y) 1 ( y) 1 ( 2 - y) 1 ( x + + + =

2
x
1 y 1
2
2
=
4
x
x 1 y 1
4
2 2
+ =
)
4
x
1 ( x y
2
2 2
=

The result is:


1 |
2
x
| provided ,
4
x
- 1 x = y
2
--(15)

Substituting for x and y, one obtains


4 I
V
1 V
I I
I
SS
2
ID
ID
SS SS
OD

= --(16)

2
SS
4
ID
SS
2
ID
SS OD
4I
V
I
V
I I

= --(17)

2
SS
4
ID
SS
2
ID
SS SS D1
4I
V
I
V
I
2
1
I
2
1
I

+ = --(18)

3

2
SS
4
ID
SS
2
ID
SS SS D2
4I
V
I
V
I
2
1
I
2
1
I

= , provided

SS
ID
I 2
| V | --(19)

2. Low Frequency Small Signal Equivalent Circuit With Pure Differential Input
Signal


V
G1
V
GS1
V
SS
V
G2
V
GS2
V
DD
V
SS
V
C
V
SS
I
SS
S3
D3
D1
S1
S4
D4
D2
S2
g
m
3
g
ds1
g
ds2
g
m4
v
gs4
g
m2
(-v
id
/2) g
m1
(v
id
/2)
g
d
s
3
g
d
s
4
V
C
+
V
O
-
I
D2
I
D4
I
O
I
D3
I
D1
M1
w=9.6u
l=5.4u
M2
w=9.6u
l=5.4u
M3
w=25.8u
l=5.4u
M4
w=25.8u
l=5.4u
(6)
(3)
(4)
(1) (2)
(5)
(b)
(a)
+
V
ID
/2
+
V
ID
/2
+2I
+I
+I
+I
I


4
Figure 2. Differential Amplifier Implementation: (a) Differential Amplifier with PMOS current
mirror load, (b) Small Signal Equivalent Circuit for Purely Differential Input Signal.

An active load acts as a current source. Thus it must be biased such that their currents add up
exactly to I
SS
. In practice this is quite difficult. Thus a feedback circuit is required to ensure this equality.
This is achieved by using a current mirror circuit as load, as in Figure 2. The current mirror consists of
transistor M3 and M4. One transistor (M3) is always connected as diode and drives the other transistor
(M4). Since V
GS3
=V
GS4
, if both transistors have the same , then the current I
D3
is mirrored to I
D4
, i.e.,
I
D3
=I
D4
.

The advantage of this configuration is that the differential output signal is converted to a single
ended output signal with no extra components required. In this circuit, the output voltage or current is
taken from the drains of M2 and M4. The operation of this circuit is as follows. If a differential voltage,
V
ID
=V
G1
-V
G2
, is applied between the gates, then half is applied to the gate-source of M1 and half to the
gate-source of M2. The result is to increase I
D1
and decrease I
D2
by equal increment, I. The I increase I
D1

is mirrored through M3-M4 as an increase in I
D4
of I. As a consequence of the I increase in I
D4
and the
I decrease in I
D2
, the output must sink a current of 2I. The sum of the changes in I
D1
and I
D2
at the
common node V
C
is zero. That is, the node V
C
is at an ac ground, see Figure 2(b). From Eq(4) and Eq(5)
for pure differential input signal means the common-mode signal V
IC
is zero. That is, the input signals are
V
G1
=V
ID
/2 and V
G2
=-V
ID
/2. This is shown in Figure 2(a). The transconductance of the differential amplifier
is given by:

m1
gs1 ID ID ID
O
mD
g
V
I
2 / V
I
V
I 2
V
I
g =

=

That is, the differential amplifier has the same transconductance as a single stage common source
amplifier.

5

g
m2
(v
id
/2) g
m4
v
gs4
g
ds2
g
ds4
G1
D1
S1 S3
D2
S2
D4
S4
D3=G3=G4
v
gs3
=
v
gs4
+
-
+
-
+
-
V
2
=v
o
V
1
=v
id
/2
2g
m1
(v
id
/2)
g
ds2
g
ds4
G1
V
1
=v
id
/2
+
-
S1
D2
S2
D4
S4
+
-
V
2
=v
o
g
m1
v
id
g
ds2
g
ds4
D2
S2
D4
S4
+
-
G1
+
-
S1
V
2
=v
o
V
1
=v
id
(b)
(c)
g
d
s
3
(a)
g
m
1
(
v
i
d
/
2
)
g
d
s
1
g
m
3


Figure 3. Differential Amplifier Operating in Purely Differential Input Signal: (a) Original Equivalent
Circuit, (b) Reduction to Two-port Network, and (c) Changing Input Port Variable to V
1
=V
id
.

The derivation of the small signal equivalent circuit is shown in Figure 2. The simplification is
based on the symmetry of the circuit. In Figure 2(b), each transistor equivalent circuit is drawn. Figure 3(a)
redraws the equivalent circuit in Figure 2(b) in a form suitable for two-port analysis. The further reduction
is obtained after the two-port parameters are obtained.

From Figure 3(a), the following two-port variables and load are obtained.


O 2
ID 1
L
V V
and
/2 V V
0 Y
=
=
=


The port current equations are derived to obtain the Y parameters:


0 I
1
= --(20)

2 ds4 ds2 gs4 m4 1 m2 2
)V g (g V g V -g I + + + = --(21)

6

V
g g g
g
- V
1
m3 ds3 ds1
m1
gs4
+ +
= --(22)

Substitute eq(22) to eq(21)



2 ds4 ds2 1 m1
2 ds4 ds2 1
m3 ds3 ds1
m4 m1
m2
2 ds4 ds2 1
m3 ds3 ds1
m4 m1
1 m2 2
)V g (g V -2g
)V g (g V )
g g g
g g
(g -
)V g (g V
g g g
g g
- V -g I
+ + =
+ +
+ +
+ =
+ +
+ +
=
--(23)


ds3 ds1 m3 m4 m3 m2 m1
g g g g g g g assuming + >> = =

The resulting Y-parameter matrix is:

(

+
=
ds4 ds2 m1
g g 2g -
0 0
Y

The dc voltage gain is,

ds4 ds2
m1
L 22
21
id
O
1
2
VD02
g g
g 2
Y y
y
2 / V
V
V
V
A
+
=
+
= = =

Instead of half differential input, dc gain with respect to full differential input is desired. That is,

ds4 ds2
m2
ds4 ds2
m1
id
O
1
2
VDO
g g
g
g g
g
V
V
V
V
A
+
=
+
= = = --(24)


7

V
G1
V
GS1
V
SS
V
G2
V
GS2
V
DD
V
SS
V
C
V
SS
V
o
+
-
M6
w=21.6u
l=1.2u
M1
w=9.6u
l=5.4u
M2
w=9.6u
l=5.4u
M4
w=25.8u
l=5.4u
M3
w=25.8u
l=5.4u
M5
w=21.6u
l=1.2u
I
SS
=220uA
I
D2
I
D4
I
O
I
D1
I
D3
(1) (2)
(8)
(9)
(4)
(3)
(6)
(5)
IB=220uA


Figure 4. The Complete Differential Amplifier Schematic Diagram

Figure 3(c) is the resulting two-port equivalent circuit. Except for the polarity this gain equation is identical
to that of the single NMOS inverter with PMOS current load. Figure 4 shows the complete differential
amplifier implemented using a pair of inverter amplifier with PMOS current load, and 200uA current
souce. The PSpice netlist is given below:

* Filename="diffvid.cir"
* MOS Diff Amp with Current Mirror Load
*DC Transfer Characteristics vs VID
VID 7 0 DC 0V AC 1V
E+ 1 10 7 0 0.5
E- 2 10 7 0 -0.5
VIC 10 0 DC 0.65V
VDD 3 0 DC 2.5VOLT
VSS 4 0 DC -2.5VOLT
M1 5 1 8 8 NMOS1 W=9.6U L=5.4U
M2 6 2 8 8 NMOS1 W=9.6U L=5.4U
M3 5 5 3 3 PMOS1 W=25.8U L=5.4U
M4 6 5 3 3 PMOS1 W=25.8U L=5.4U
M5 8 9 4 4 NMOS1 W=21.6U L=1.2U
M6 9 9 4 4 NMOS1 W=21.6U L=1.2U
IB 3 9 220UA
.MODEL NMOS1 NMOS VTO=1 KP=40U
+ GAMMA=1.0 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.MODEL PMOS1 PMOS VTO=-1 KP=15U
+ GAMMA=0.6 LAMBDA=0.02 PHI=0.6
8
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.DC VID -2.5 2.5 0.05V
.TF V(6) VID
.PROBE
.END




The operating point current is determined by the source current I
SS
, which is split between the two PMOS
current loaded inverters. I
DSQ1
=I
DSQ2
=I
SS
/2, and similarly I
DSQ3
=I
DSQ4
=I
SS
/2. For the given differential
amplifier I
SS
=220uA. The voltage gain is computed as follows:

87.95uA/V = 0.5u)) * 2 - 5.4u 6)(25.8u/( - E 15 ( ) L / W ( K
87.3uA/V = 0.5u)) * 2 - .4u 6)(9.6u/(5 - E 40 ( ) L / W ( K
2
P3 P3 P3 P4 P3
2
N1 N1 N1 N2 N1
= = =
= = =




umho 1 . 139 6) - 6)(110E - E 95 . 87 ( 2 I 2 g g
umho 59 . 138 6) - 6)(110E - E 3 . 87 ( 2 I 2 g g
DSQ3 P3 m4 m3
DSQ1 N1 m2 m1
= = = =
= = = =

umho 4.4 = 6) - E 220 ( 02 . I I g
umho 2.2 = 6) - E 110 ( 02 . I I g
umho 2.2 = 6) - E 110 ( 02 . I I g
DSQ5 P DSQ DS5 ds5
DSQ1 P DSQ4 DS4 ds4
DSQ1 N DSQ2 DS2 ds2
= = =
= = =
= = =





5 . 31
6 - 2.2E + 6 - 2.2E
6 - E 59 . 138
g g
g
A
ds4 ds2
m1
VD
= =
+


9
The low frequency input resistance Rin = . The output resistance Rout = 1/(g
ds2
+g
ds4
)= 1/(2.2E-6+2.2E-6)
=.2272M, see Figure 3(d), and the computation above. These calculations agree well with Pspice
simulation results of:

**** SMALL-SIGNAL CHARACTERISTICS


V(6)/VID = 3.347E+01

INPUT RESISTANCE AT VID = 1.000E+20

OUTPUT RESISTANCE AT V(6) = 2.423E+05


3. Determination of the input common-mode range

10

V
G1
V
GS1
V
SS
V
G2
V
GS2
V
DD
V
SS
V
C
V
SS
I
SS
M3
M4
M1 M2
S3
D3
D1
S1
S4
D4
D2
S2
g
ds1
g
ds2
g
m4
v
gs4
g
m2
v
gs2
g
m1
v
gs1
M5
V
GG
+
V
IC
+
V
IC
g
ds5
V
o
+
-
V
o
+
-
g
m
3
g
d
s
4
g
d
s
3
V
C
V
DS5
V
DG1
V
SD3
V
SD4
V
gs3
V
gs4


Figure 5. Differential Amplifier with Purely Common-mode Input Signal: (a) Schematic Diagram,
and (b) Small Signal Equivalent Circuit.

The input common-mode range is the range of common-mode voltage Vic=V
G1
=V
G2
in which all
the transistors are operating in saturation region. To determine this a purely common-mode input is applied
at both inputs, see Figure 5.

3.1 Maximum V
G1
or V
G2
Determination

As VG1 approaches VDD transistor M1 and M2 go into the triode region. V
G1
(max) is the value
of the input when it occurs. This can be determined from Figure 5 by writing the KVL equation from V
DD

toward V
G1
.
11


G = D since , V V V =
V V V V
DG1 SG3 DD
DG1 SD3 DD G1

=


| V |
| I | 2
| V | |) V | | V (| V
TP3
P3
DS3
TP3 TP3 GS3 SG3
+ = + =

DG1 TP3
P3
DS3
DD G1
V | V |
| I | 2
V V =

From Figure 5(a), V
DG1
can be determined in term of the commonly known transistor voltages of M1.




DG1 GS1 DS1
GS1 DS1 DG1
V V V
or
V - V V
+ =
=


Transistor M1 is on saturation when the following condition holds.

DG1 GS1 DS1 TN1 GS1
V V V V V + =

That is,

DG1 TN1
V V

The minimum value of V
DG1
is achieved when transistor M1 is on the threshold of saturation. That is,


DG1 TN1
V V =

The maximum input voltage is obtained when
DG1 TN1
V V = . That is,

P3
SS
DD
P3
DS3
DD
TN1 TP3
P3
DS3
DD G1
I
V
| I | 2
V
V | V |
| I | 2
V (max) V

= =
+ =
--(25)


Assuming |V
TP3
| V
TN1.


3.2 Minimum V
G1
or V
G2
Determination
12

As V
G1
approaches V
SS
, M1 becomes cutoff. The minimum input voltage V
G1
is determined when
M5 is no longer in saturation. This is obtained by writing the KVL equation from V
SS
to V
G1
.

GS1 DS5 SS G1
V V V V + + =

Transistor M5 is on saturation when,

DS5 TN5 GS5
V V V
M5 is at verge of saturation when,
DS5(SAT) DS5 TN5 GS5
V V V V = =
That is, the minimum input voltage occurs when,
DS5(SAT) TN5 GS5
V V V = .

GS1 DS5(SAT) SS G1
V V V (min) V + + = --(26)


GS1 TN5 GS5 SS G1
V ) V (V V (min) V + + =

N1
SS
GG
N1
DS1
GG
TN1
N1
DS1
TN5 GG
TN1 TN1 GS1 TN5 SS GG SS G1
I
V
2I
V
V
2I
V V
V ) V - V ( ) V V V ( V (min) V

+ = + =
+ + =
+ + + =
--(27)

Ignoring the bulk bias effect.

Using the SPICE parameters for the differential amplifier implemented in Figure 4.
From Eq(25),
P3
SS
DD G1
I
V (max) V

=
2
3 3 P P3
uA/V 87.95 = 0.5u)) * 2 - 5.4u 6)(25.8u/( - E 15 ( ) L / W ( K = =
V 92 . 0 58 . 1 5 . 2
6 - 87.95E
6 - E 220
5 . 2 (max) V
G1
= = =
and from Eq(27),

V 38 . 0 2 . 1 58 . 1 2 . 1
87.3
6 - E 220
V
I
(min) V
GG
N1
SS
G1
= = = + =

To guarantee that the differential amplifier stays on the linear region of operation, set common-mode signal
at half way the common-mode range. That is, V
IC
=[V
G1
(max)+V
G1
(min)]/2=[0.92+.38]/2=0.65.
4. Low Frequency Small Signal Equivalent Circuit With Pure Common-Mode Input
Signal

13

2g
m1
v
gs1
D1
S1
D3
S3
+
-
G1
+
-
V
2
=v
o
V
1
=V
ic
g
ds5
g
d
s
1
+
g
d
s
2
g
d
s
3
+
g
d
s
4
+
g
m
3
+
g
m
4
V
gs1
D5
S5
V
C
Y
L
(c)
g
m1
v
gs1
g
m2
v
gs2
g
ds2
g
ds4
G1
D1
S1
S3
D2
S2
D4
S4
D3=G3=G4
+
-
v
o
+
-
v
gs1
+
-
g
ds5
+
-
V
ic
V
c
v
gs3
g
d
s
1
D5
g
m
4
v
g
s
4
S5
+
-
v
gs4
g
d
s
3
+
g
m
3
g
d
s
4
+
g
m
4
g
m1
v
gs1
g
m2
v
gs2
g
ds2
G1
D1
S1
S3
D2
S2
D4
S4
D3=G3=G4
+
-
v
o
+
-
v
gs1
+
-
g
ds5
+
-
V
ic
V
c
v
gs3
g
d
s
1
g
d
s
3
+
g
m
3
D5
S5
(b)
(a)
I2
I2


Figure 6. Small Signal Equivalent Circuit: (a) Original Small Signal Equivalent Circuit, (b) Accounting for
Source Values and Polarities, and (c) Two-port Conversions.

Figure 5(a) shows the schematic when a purely common-mode input is applied at both inputs that
is, V
G1
=V
G2
=V
IC
. If V
IC
increases both I
D1
and I
D2
increases. Their sum at the common node V
C
also
increases. Figure 5(b) shows that V
C
is not at ac ground, unlike the pure differential input signal case
shown in Figure 2(b). Due to signal symmetry when both inputs are the same, V
DS3
=V
DS4
. Since both G
and S of M3 and M4 are connected to each other, means V
GS3
=V
GS4
. M3 is diode connected with G and D
connected, means V
GS3
=V
DS3
. From these expressions, V
DS4
=V
GS4
can be deduced. That is the voltage
14
across D and S of M4 can be labelled as V
GS4
, see Figure 6(a). The current source of M4 is therefore
reduced to conductance g
m4
, see Figure 6(b). Since V
DS3
=V
DS4
, the D3 and D4 can be connected together.
Figure 6(c) shows the final equivalent circuit after combining all components that are in parallel.

From Figure 6(c), the following two-port variables and load are obtained.

O 2
IC 1
m3 ds4 ds3
m3 ds3 m4 m3 ds4 ds3 L
V V
and
V V
g g g g assuming
g 2 g 2 g g g g Y
=
=
= =
+ = + + + =
m4

The two-port current equations are derived to obtain the Y parameters.

2
m1 ds5 ds2 ds1
ds5 ds2 ds1
1
m1 ds5 ds2 ds1
ds5 m1
2
2
ds5
m1 ds2 ds1 2 ds2 ds1 1 m1 2
2
ds5
C
C m1 ds2 ds1 2 ds2 ds1 1 m1
C 1 m1 C 2 ds2 ds1 2
1
V
2g g g g
)g g g (
V
2g g g g
g g 2
I
I
g
1
) 2g g (g - )V g (g V 2g I
I
g
1
V
)V 2g g (g - )V g (g V 2g
) V - (V 2g ) V - )(V g (g I
0 I
+ + +
+
+
+ + +
=
+ + + + =
=
+ + + + =
+ + =
=


The Y-parameter matrix is:

m4 m3 ds2 ds1
m1 ds5 ds1
ds5 ds1
m1 ds5 ds1
ds5 m1
m1 ds5 ds2 ds1
ds5 ds2 ds1
m1 ds5 ds2 ds1
ds5 m1
g g g g assuming
2g g 2g
g g 2
2g g 2g
g g 2
0 0

2g g g g
)g g g (
2g g g g
g g 2
0 0
Y
= =
(
(

+ + + +
=
(
(

+ + +
+
+ + +
=


The dc common-mode voltage gain is,

15
. g g assuming
r g 2
1
r g 2
g
g
r g 2 1
g
g
g
2g 2g
1
g
g
g
g

) 2g g 2g )( g g ( 2 g g 2
g g 2

) g g ( 2
2g g 2g
g g 2
2g g 2g
g g 2
Y y
y
A
ds3 m3
ds5 m3 ds5 m1
m3
m1
ds5 m1
m3
m1
ds5
m1 ds1
m3
ds1
m3
m1
m1 ds5 ds1 m3 ds3 ds5 ds1
ds5 m1
m3 ds3
m1 ds5 ds1
ds5 ds1
m1 ds5 ds1
ds5 m1
L 22
21
VC0
>>

+
+ +

=
+ + + +

=
+ +
+ +
+ +

=
+

=


* Filename="diffvic.cir"
* MOS Diff Amp with Current Mirror Load
*DC Transfer Characteristics vs VIC
VID 7 0 DC 0V
E+ 1 10 7 0 0.5
E- 2 10 7 0 -0.5
VIC 10 0 DC 0V
VDD 3 0 DC 2.5VOLT
VSS 4 0 DC -2.5VOLT
M1 5 1 8 8 NMOS1 W=9.6U L=5.4U
M2 6 2 8 8 NMOS1 W=9.6U L=5.4U
M3 5 5 3 3 PMOS1 W=25.8U L=5.4U
M4 6 5 3 3 PMOS1 W=25.8U L=5.4U
M5 8 9 4 4 NMOS1 W=21.6U L=1.2U
M6 9 9 4 4 NMOS1 W=100.8U L=3.6U
M7 9 9 3 3 PMOS1 W=3.6U L=3.6U
.MODEL NMOS1 NMOS VTO=1 KP=40U
+ GAMMA=1.0 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.MODEL PMOS1 PMOS VTO=-1 KP=15U
+ GAMMA=0.6 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.OP
.DC VIC -2.5 2.5 0.05V
.TF V(6) VIC
.PROBE
.END

16






01582 . 0
) 6)(.2272E6 - E 1 . 139 ( 2
1
r g 2
1
A
ds5 m3
VCO
= = =

This is very closed to the PSpice simulation result.

**** SMALL-SIGNAL CHARACTERISTICS

17

V(6)/VIC = -1.459E-02

INPUT RESISTANCE AT VIC = 1.000E+20

OUTPUT RESISTANCE AT V(6) = 2.386E+05

The goal of differential amplifier is to amplify the difference signal and to reject common-mode signal. A
figure of merit called common-mode rejection ration (CMRR) is defined as:

15 . 1991
0.01582 -
5 . 31
A
A
CMRR
VC
VD
= = =

5. Differential Gain Frequency Response


18

V
G1
+
V
GS1
V
SS
V
G2
+
V
GS2
V
DD
V
SS
V
C
V
SS
I
SS
M3 M4
M1 M2
C
L
C
gd2
C
db4
C
db2
C
gs4
C
gs3
C
gd4
C
db3
C
gd1
(a)
C
db1
V
GS1
V
SS
V
GS2
V
SS
V
C
V
SS
I
SS
M3 M4
M1 M2
C
2
C
3
C
1
(b)
V
DD
V
G2
+
V
G1
+
C1=C
gd1
+C
db1
+C
db3
+C
gs3
+C
gs4
C2=C
gd2
+C
db2
+C
db4
+C
L
C3=Cgd4
(1)
(2)
(5) (6)
(8)


Figure 7. Parasitic Capacitances of Differential Amplifier Operating in Purely Differential Input Signal: (a)
Parasitic Capacitances of each Transistor, (b) Lumped Parasitic Capacitances.

Figure 7(a) shows all the parasitic capacitances of the differential amplifier with purely
differential input signals. Since both inputs are voltage sources, they are at ac ground when considering the
effects of gate capacitances. Figure 7(b) shows that there are basically three capacitances. These are:

gd4 3
L db4 db2 gd2 2
gs4 gs3 db3 db1 gd1 1
C C
C C C C C
C C C C C C
=
+ + + =
+ + + + =


19

g
m1
(v
id
/2)
g
d
s
1
+
g
d
s
3
+
g
m
3
C1
C3
g
m2
(v
id
/2)
g
m4
v
gs4
g
d
s
2
+
g
d
s
4
C2
G1 D1
S1
D3=G3=G4
S3
D2 D4
S2 S4
+
v
o
-
+
v
id
/2
-
g
m1
(v
id
/2) g
m1
(v
id
/2)
g
m4
v
gs4
G1 D1
S1
D3=G3=G4
S3
D2 D4
S2 S4
+
-
+
-
I
3
+
-
V
gs4
C1=C
gd1
+C
db1
+C
db3
+C
gs3
+C
gs4
C2=C
gd2
+C
db2
+C
db4
+C
L
C3=Cgd4
(a)
(b)
Y3
Y1 Y2 V
1
=V
id
/2
V
2
=V
O
=
g
m1
=g
m2


Figure 8. High Frequency Small Signal Equivalent Circuit: (a) Small Signal Equivalent Circuit Showing
Lumped Capacitances, (b) Small Signal Equivalent Circuit Combining Capacitance and Resistance to
Admittance.

NOTE C
3
is not a miller capacitance, it is connected between the outputs of the two inverter amplifiers,
and not between an output and an input terminals of an amplifier. C
3
in this case is normally small and can
be ignored. Figure 8(b) shows that the three admittances are given by:

gd4 3 3
2 ds4 ds2 2
1 m3 ds3 ds1 1
C C Y
C g g Y
C g g g Y
s s
s
s
= =
+ + =
+ + + =

The two-port Y parameters are to be determined. Figure 8(b) shows that the two-port variables are:

O 2
id 1
L
V V
and
2 / V V
0 Y
=
=
=


20
2
3 1
3 m1 3 2 3 1 2 1
1
3 1
m4 m1 1 m1
2
3 1
3
1
3 1
m1
m4 3 2 3 2 1 m1 2
2
3 1
3
1
3 1
m1
gs4
gs4
gs4 2 3 1 m1 gs4 1
gs4 1 3
gs4 2 3 1 m1 3
gs4 m4 3 2 3 2 1 m1
2 2 gs4 m4 1 m1 gs4 2 3 2
1
V
Y Y
Y g Y Y Y Y Y Y
V
Y Y
g g - Y g -

) V
Y Y
Y
V
Y Y
g
)( g Y ( )V Y Y ( V -g I
V
Y Y
Y
V
Y Y
g
V
V for Solve
0 ) V - (V Y - V g V Y
V Y I
0 ) V - (V Y - V g I
D3 node At
)V g Y ( )V Y Y ( V -g
V Y V g V g - ) V - (V Y I
0 I
+
+ + +
+
+
=
+
+
+

+ + + + =
+
+
+

=
= +
=
= +
+ + + + =
+ + =
=

The Y-parameter matrix is:

(
(

+
+ + +
+
=
3 1
3 m1 3 2 3 1 2 1
3 1
m4 m1 1 m1
Y Y
Y g Y Y Y Y Y Y
Y Y
g g - Y g -
0 0
Y

For differential amplifier the assumption that Y3 or C3 is approximately 0 is valid. That is,

(
(

=
2
1
m4 m1
m1
Y
Y
g g
- g
0 0
Y

The differential gain is given by:

21
|
|
.
|

\
|
+
+
|
|
.
|

\
|
+ +
+
|
|
.
|

\
|
+ + +
+
|
|
.
|

\
|
+
=
|
|
.
|

\
|
+
+
|
|
.
|

\
|
+ +
+ + +
|
|
.
|

\
|
+ + +
+ + + +
|
|
.
|

\
|
+
=
+ + + + +
+ + + +
=
+ +
+ + +
+
=
+
=
+
=
+

= =
ds4 ds2
2
m3 ds3 ds1
1
m4 m3 ds3 ds1
1
ds4 ds2
m1
ds4 ds2
2
m3 ds3 ds1
1
m3 ds3 ds1
m4 m3 ds3 ds1
1
m4 m3 ds3 ds1
ds4 ds2
m1
2 ds4 ds2 1 m3 ds3 ds1
1 m4 m3 ds3 ds1 m1
2 ds4 ds2
1 m3 ds3 ds1
m4
m1
2
1
m4
m1
2
1
m4 m1
m1
L 22
21
1
2
VD2
g g
C
1
g g g
C
1
g g g g
C
1
g g
g
2
g g
C
1
g g g
C
1 ) g g g (
g g g g
C
1 ) g g g g (
g g
g

) C g )(g C g g (g
) C g g g (g g
) C g (g
)
C g g g
g
(1 g

Y
)
Y
g
(1 g
Y
Y
g g
g
Y y
y
V
V
A
s s
s
s s
s
s s
s
s
s


The differential gain when the input voltage V
1
is changed to V
ID
is:

1
m3
1
m4 m3 ds3 ds1
1
m3
1
m3 ds3 ds1
2
2
ds4 ds2
1
1 2
VDO
ds4 ds2
2
m3 ds3 ds1
1
m4 m3 ds3 ds1
1
ds4 ds2
m1
id
O
VD
C
2g
C
g g g g
z
C
g
C
g g g
p
C
g g
p
: where
)
p
1 )(
p
1 (
)
z
1 (
A
g g
C
1
g g g
C
1
g g g g
C
1
g g
g
V
V
A

+ + +
=

+ +
=
+
=

=
|
|
.
|

\
|
+
+
|
|
.
|

\
|
+ +
+
|
|
.
|

\
|
+ + +
+
|
|
.
|

\
|
+
= =
s s
s
s s
s

p
1
<< p
2
<< z


NOTE the differential voltage gain has pole-zero doublets. That is, the zero z is double that of the non-
dominant pole p
2
. The dominant (lowest frequency) pole p
1
occurs at the output node. The above transfer
function can also be obtained by noting that each pole correspond to a node in the differential amplifier.
22
Each node is at a finite impedance with respect to ground. That is, each node there is a resistance R
n
(or
conductance) and capacitance C
n
to ground. To determine which poles are dominant (or more significant),
the impedance levels must be monitored. The parasitic capacitances C
n
are of approximately the same
magnitude, but R
n
usually vary considerably. When the resistance (conductance) is high (low), a dominant
pole is generated. The impedance levels are summarized in the follwing table:

Node(From Netlist) Resistance Capacitance Pole
1 0 (ac ground) X
2 0 (ac ground) X
5 R
5
=1/(g
ds1
+g
ds3
+g
m3)
C
1
p
2
=1/(R
5
C
1
)*
6 R
6
=1/(g
ds2
+g
ds4)
C
2
p
1
=1/(R
6
C
2
)
8 0 (ac ground) X

The derivation shows that the pole p
2
create a zero doublet.

* Filename="diffreq.cir"
* MOS Diff Amp with Current Mirror Load
*DC Transfer Characteristics vs VID
VID 7 0 DC 0V AC 1V
E+ 1 10 7 0 0.5
E- 2 10 7 0 -0.5
VIC 10 0 DC 0.65V
VDD 3 0 DC 2.5VOLT
VSS 4 0 DC -2.5VOLT
M1 5 1 8 8 NMOS1 W=9.6U L=5.4U
M2 6 2 8 8 NMOS1 W=9.6U L=5.4U
M3 5 5 3 3 PMOS1 W=25.8U L=5.4U
M4 6 5 3 3 PMOS1 W=25.8U L=5.4U
M5 8 9 4 4 NMOS1 W=21.6U L=1.2U
M6 9 9 4 4 NMOS1 W=100.8U L=3.6U
M7 9 9 3 3 PMOS1 W=3.6U L=3.6U
.MODEL NMOS1 NMOS VTO=1 KP=40U
+ GAMMA=1.0 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.MODEL PMOS1 PMOS VTO=-1 KP=15U
+ GAMMA=0.6 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.AC DEC 100 1HZ 100000GHZ
.PROBE
.END

23



6. Common-Mode Frequency Response

24

V
G1
V
GS1
V
SS
V
G2
V
GS2
V
DD
V
SS
V
C
V
SS
M3
M4
M1 M2
M5
V
GG
+
V
IC
+
V
IC
V
o
+
-
C
db5
C
sb2
C
sb1
C
gd5
V
G1
V
GS1
V
SS
V
G2
V
GS2
V
DD
V
SS
V
C
V
SS
M3
M4
M1 M2
M5
V
GG
+
V
IC
+
V
IC
V
o
+
-
C
S
C
S
=C
sb1
+C
sb2
+C
db5
+C
gd5


Figure 9. Differential Amplifier Operating in Pure Common-Mode Input Signal: (a) All Parasitic
Capacitances at Common Node Vc, (b) Total Capacitances Across the Drain and Source of M5.

From the expression of the dc common-mode gain, it is primarily a function of g
m3
and r
ds5
. The
first order frequency response analysis can be simplified by ignoring all parasitic capacitances except the
capacitance C
S
across r
ds5
, see Figure 9. That is r
ds5
is replaced by z
ds5
in the the common-mode gain
expression to account for frequency dependency.

25
gd5 db5 sb2 sb1 S
ds5 m3
S ds5
S ds5
ds5
m3
ds5 m3
VC
S ds5
ds5
S ds5 ds5
C C C C C
: where
r g 2
) C r 1 (
C r 1
r
g 2
1
z g 2
1
A
C r 1
r
) //C r ( z
+ + + =
+
=
+

=
+
= =
s
s
s



* Filename="diffreqc.cir"
* MOS Diff Amp with Current Mirror Load
*DC Transfer Characteristics vs VIC
VID 7 0 DC 0V
E+ 1 10 7 0 0.5
E- 2 10 7 0 -0.5
VIC 10 0 DC 0.65V AC 1V
VDD 3 0 DC 2.5VOLT
VSS 4 0 DC -2.5VOLT
M1 5 1 8 8 NMOS1 W=9.6U L=5.4U
M2 6 2 8 8 NMOS1 W=9.6U L=5.4U
M3 5 5 3 3 PMOS1 W=25.8U L=5.4U
M4 6 5 3 3 PMOS1 W=25.8U L=5.4U
M5 8 9 4 4 NMOS1 W=21.6U L=1.2U
M6 9 9 4 4 NMOS1 W=100.8U L=3.6U
M7 9 9 3 3 PMOS1 W=3.6U L=3.6U
.MODEL NMOS1 NMOS VTO=1 KP=40U
+ GAMMA=1.0 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.MODEL PMOS1 PMOS VTO=-1 KP=15U
+ GAMMA=0.6 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.AC DEC 100 1HZ 100000GHZ
.PROBE
.END




26



The differential-mode voltage gain decreases with increasing frequency but common-mode voltage
increases. Therefore, CMRR decreases with increasing frequency.

7. Designing Differential Amplifier With Specified CMR
Given a common-mode range of 0.75 <= V
IC
<=0.75 , V
GG
=-1, I
SS
=I
DS5
=100uA, L
min
=5.4u,
. Determine the size of each transistor in the differential amplifier circuit, see
Figure 4.
5 . 0 V V V
TN GS
= =

1. Determine the (W/L)
5
to sink 100uA.

|
.
|

\
|
= = =
= =
|
.
|

\
|
|
.
|

\
|
= =
u 4 . 5
u 108
20
1] - (-2.5) - 6)[-1 - (40E
6) - E 100 ( 2

) V - V - V ( K
I 2
) V - V ( K
I 2
L
W
) V - V (
L
W
2
K
) V - V (
2
I
2
2
TN5 SS GG N
DS5
2
TN5 GS5 N
DS5
5
2
TN5 GS5
5
N 2
TN5 GS5
N5
DS5



2. Determine (W/L)
1
=(W/L)
2
from V
IC
(min)=V
G1
(min) specification

From Eq(26),

27
|
.
|

\
|
= = = = |
.
|

\
|
= |
.
|

\
|
= =
+ + = =
u 4 . 5
u 216
40
1) - 6)(1.25 - E 40 (
6) - E 50 ( 2
) V - (V K
I 2
L
W
L
W
25 . 1 5 . 0 ) 5 . 2 ( 75 . 0 V V 75 . 0 V
75 . 0 V V V min) ( V V
2 2
TN GS1 N
DS1
2 1
DS5(SAT) SS GS1
GS1 DS5(SAT) SS G1 IC


3. Determine (W/L)3=(W/L)4 from V
IC
(max)=V
G1
(max) specification

From Eq(25),

|
.
|

\
|
= = = = |
.
|

\
|
|
.
|

\
|
= =
= =
u 4 . 5
u 75 . 11
177 . 2
0.75) - 6)(2.5 - E 15 (
6) - E 50 ( 2
(max)) V - (V K
| I | 2
L
W
(max)) V - V (
L
W
2
K
(max)) V - V (
2
| I |
| I | 2
V (max) V (max) V
2 2
G1 DD P
DS3
3
2
G1 DD
3
P 2
G1 DD
P3
DS3
P3
DS3
DD G1 IC

The above is simulated using PSpice. The results agree well with the calculations.

* Filename="diffcmr.cir"
* MOS Diff Amp with Current Mirror Load
*DC Transfer Characteristics vs VIC
VID 7 0 DC 0V
E+ 1 10 7 0 0.5
E- 2 10 7 0 -0.5
VIC 10 0 DC 0V
VDD 3 0 DC 2.5VOLT
VSS 4 0 DC -2.5VOLT
M1 5 1 8 8 NMOS1 W=216U L=5.4U
M2 6 2 8 8 NMOS1 W=216U L=5.4U
M3 5 5 3 3 PMOS1 W=11.75U L=5.4U
M4 6 5 3 3 PMOS1 W=11.75U L=5.4U
M5 8 9 4 4 NMOS1 W=108U L=5.4U
VGG 9 0 DC -1V
.MODEL NMOS1 NMOS VTO=1 KP=40U
+ GAMMA=1.0 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.MODEL PMOS1 PMOS VTO=-1 KP=15U
+ GAMMA=0.6 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.DC VIC -2.5 2.5 0.05V
.TF V(6) VIC
.PROBE
.END



28




29