SPLD112A

LCD DRIVER WITH 112-CHANNEL OUTPUTS

GENERAL DESCRIPTION SPLD112A, a versatile dot matrix LCD driver with low power CMOS technology from Sunplus, is capable of providing varieties of common/segment combinations for application development. Ease of use, high

performance and low cost make SPLD112A ideal for most LCD related products. This LSI includes four primary blocks: 112-bit Shift Register, 112-bit Data Latch, 112-bit Level Driver and a Charge Pump. The 112-bit Shift Register allows users to select different common/segment types as well as data shifting. The 112-bit Data Latch is basically responsible for loading data from the Shift Register and the 112-bit Level Driver is to generate corresponding voltage level. The block of Charge Pump is capable of raising the voltage level to double or triple (negative voltage level) of original voltage level. Moreover, the SPLD112A also converts serial data to parallel data and outputs LCD waveform to LCD.

FEATURES Operating voltage: 2.4V 6.0V LCD driver voltage: < 12V

BLOCK DIAGRAM

D[112:1] V5 - 1 ....... 4-level Driver X112(seg/com) CUP2 charge DF Level shift and selector pump CUP1 VSS2 VEE LD CKV 112-bit Latch MEN

Bias voltage can be supplied externally Built-in voltage converter( double or triple) Serial LCD data input Chain function (only for segment) 1/48, 1/32 or 1/16 duty
DIN

DO112 112-bit shift register MODE0 MODE1

Segment / common driver, 4 combinations are provided : Mode A B C D Mode0 1 1 0 0 Mode1 Common Segment 0 1 1 0 48 32 16 0 64 80 96 112

CP

Sunplus Technology Co., Ltd.

Rev.: 1.1

2000.02.15

SPLD112A
BLOCK FUNCTION DESCRIPTION (1) 112-bit Shift Register Basically, this block is a data shift register. It needs to cooperate with Mode0 and Mode1 to select A, B, C or D mode that defines various segment and common ranges. For example, when Mode0=1 and Mode1=1, the mode is defined as ModeB. In ModeB, its D80 - 1 are segments and its D112 - 81 are commons. The data of segment enters from DIN and the data of common enters from DO112. Furthermore, according to the CP signal, the data of segment will enter into the 1 bit of Shift Register and continuously shifting one after another until the 80 bit of Shift Register. On the other hand, the data of common will enter into the 81th bit of Shift Register and continuously shifting until the 112 bit of the Shift Register.
th th st

(2) 112-bit-latch will load the data to the Register from Shift Register when LD=1 or hold data when LD=0.

(3) The Level Shift and Selector Block uses DF(Frame Signal) and the data of 112-bit-latch to decode 4 types of voltage level control signals.

(4) The functionality of 4 level Driver *112 block is to process the control signal from Level Shift and turns on a certain MOS in order to get a corresponding voltage level.

(5) The purpose of Charge Pump Block is to generate a double and triple voltage level. MEN signal is the control signal. When MEN=1, the Charge Pump will be enabled and generate a double/triple voltage. When MEN=0, the Charge Pump will be disabled and the voltage level of VEE & VSS2 are grounded. CKV is the clock signal of Charge Pump whose frequency is suggested from 50KHz to 300KHz.

FUNCTION DESCRIPTION Four combinations can be provided to fit different applications Mode A Mode0 1 Mode1 0 Segment 64 Common 48 D[112:65] = COM[48:1] D[80:1] = SEG[80:1] B 1 1 80 32 D[112:81] = COM[32:1] D[96:1] = SEG[96:1] C D 0 0 1 0 96 112 16 D[112:97] = COM[16:1] 0 D[112:1] = SEG[112:1] Note D[64:1] = SEG[64:1]

Sunplus Technology Co., Ltd.

Rev.: 1.1

2000.02.15

SPLD112A

COM/SEG

Data H

DF H L H L H L H L

Display Output Level VDD V5 V4 V1 V5 VDD V3 V2

COMMON

H L L H

SEGMENT

H L L

Mode A B C D

Mode0 1 1 0 0

Mode1 0 1 1 0

D[64:1] SEG SEG SEG SEG

D[80:65] COM SEG SEG SEG

D[96:81] COM COM SEG SEG

D[112:97] COM COM COM SEG

Mode A
D1 D2 D3 D4 D64 D65 D66 D112

BIT1

BIT2

BIT3

BIT4

BIT64

BIT65

BIT66

BIT112

DIN

CP

LD

DO112

Mode B
D1 D2 D3 D4 D80 D81 D82 D112

BIT1

BIT2

BIT3

BIT4

BIT80

BIT81

BIT82

BIT112

DIN

CP

LD

DO112

Sunplus Technology Co., Ltd.

Rev.: 1.1

2000.02.15

SPLD112A
Mode C
D1 D2 D3 D4 D96 D97 D98 D112

BIT1

BIT2

BIT3

BIT4

BIT96

BIT97

BIT98

BIT112

DIN

CP

LD DO112

Mode D
D1 D2 D3 D4 D80 D81 D82 D112 DO112

BIT1

BIT2

BIT3

BIT4

BIT80

BIT81

BIT82

BIT112

DIN

CP

PIN DESCRIPTION Mnemonic D112 - 46 D45 - 1 CP PIN No. 67 - 1 132 - 88 84 I LCD data shift clock; also used as the clock of double/triple voltage generator. The data is shifted to 112-bit latch at the falling edge of CP. A data setup time and a data hold time are required between DIN and CP. DF LD 73 75 I I LCD alternate signal LCD data load. When LOAD is set to HIGH, the shift register contents are transferred to driver through level shifter. When LOAD is set to LOW, the last display data which was transferred when LOAD was high, is held. DIN 82 I Segment data input. transferred to driver. DO112 77 I/O When Mode-D is selected, the content of 112th bit of Shift Register is output from DO112. When Mode-A, Mode-B or Mode-C is selected, The data applied in this pin is shifted and Type O Segment/Common output Description

the bit data applied to DO112 will be shifted to bit -65, bit-81 and bit- 97. MODE0 MODE1 VDD, VSS CUP1, CUP2 85, 74 81, 80 I I/O Power input Coupling capacitor for change pump 71, 76 I Mode-A, Mode-B, Mode-C and Mode-D selector

Sunplus Technology Co., Ltd.

Rev.: 1.1

2000.02.15

SPLD112A
Mnemonic V5, V4, V3, V2, V1 MEN PIN No. 69, 70 72, 79, 86 78 I Master enable: 1 - generate VEE 0 - voltage tripler disable This pin should be controlled by CPU. Before entering standby mode, MEN must be programmed LOW to turn off the double/triple voltage generator. VSS2 VEE 83 87 I I Double voltage output Triple voltage output, if MEM is assigned to LOW, VSS2 and VEE will keep on the same voltage as ground. CKV 68 I This clock is needed for double/triple voltage generator. The frequency is suggested between 50kHz - 300kHz depending on the loading between VDD and VEE. Type I Description LCD reference voltage input; highest : V1-----lowest : V5

ABSOLUTE MAXIMUM RATINGS Characteristics DC supply Voltage 1 DC supply Voltage 2 input Voltage Range Symbol VDD VDD + |VEE| VIN Ratings 7V 12V -0.5V to VDD+0.5V

Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics.

Sunplus Technology Co., Ltd.

Rev.: 1.1

2000.02.15

SPLD112A
ELECTRICAL CHARACTERISTICS Limit Characteristics Operating voltage Standby current Consumption current Input high level (CP, LD, DF, DIN, MODE0, MODE1, MEN, CKV) Input low level Output high level Output low level Vi - Dj on resister Note 1: The resister is 100K VIL VOH VOL RON VDD-0.5 0.7 0.5 1.5 V V V K VDD -VEE = 12V VDD = 3V VIH 1.3 V VDD = 3V Symbol Min. VDD ISTYB IGND 2.4 Typ. 0.3 Max. 6.0 1.0 V A mA VDD = 3V VDD = 3V, Note 1 CP = 100KHz Unit Test Condition

between VDD and VEE

Sunplus Technology Co., Ltd.

Rev.: 1.1

2000.02.15

SPLD112A

R1
0.1

R1
0.1

R2
0.1

R1
0.1 0.1

R1

VR VBB

VSS2 VEE

1. Doubler - VBB short to VSS2 2. Tripler - VBB short to VEE V1 LCDEN MEN VEE FP DF DO112 DF LD CP DIN CKV D[80:1] RESBP = R OSC / 32 SEG[80:1] COM[32:1] MODE0 VDD RESBP D[112:1] MODE1 D[112:81] 0.1 V2 V3 V4 V5

SPL512A
LP CP IO

CUP2 VSS2 0.1

SPLD112A

CUP1

0.1

APPLICATION NOTES

Application Circuit

LCD PANEL

Figure 1: SPLD112A, 1/32 duty, 80 segments APPLICATION CIRCUIT

Sunplus Technology Co., Ltd.

Rev.: 1.1

0.1

2000.02.15

SPLD112A

R1 0.1

R1 0.1

R2 0.1

R1 0.1 0.1

R1

VR 0.1 VBB

VSS2

VEE

1. Doubler - VBB short to VSS2 2. Tripler - VBB short to VEE

LCDEN

V1

V2 V3 V4

FP

V5 MEN VEE VSS2 CUP1 0.1 CUP2

V1

V2

V3 V4

V5 MEN VEE VSS2

VEE VSS2 0.2 0.2

LP CP IO RESBP

LD CP DIN CKV

LD CP DIN CKV O[64:1]

CUP2 MODE0 MODE1 DO112 O[112:1]

MODE0 MODE1 DO112 O[112:1]

O[112:65]
Sunplus Technology Co., Ltd.

RESBP = ROSC / 32

SEG[112:1]

SEG[176:113] COM[48:1]

LCD PANEL
Figure 2: SPLD112A, 1/48 duty, 176 segments, APPLICATION CIRCUIT

SPL512A

DF

DF

SPLD112A

DF

SPLD112A CUP1

0.1

VDD

Rev.: 1.1

2000.02.15

SPLD112A

R1

R1

R2

R1

R1

VR VBB

VSS2

1. Doubler - VBB short to VSS2 2. Tripler - VBB short to VEE

LCDEN

V1

V2

V3

V4

V5 MEN

V1

V2

V3

V4

V5 MEN VEE VSS2 0.1

FP DF DF

VSS2 0.1

VSS2 DF

LP CP IO RESBP

LD CP DIN

CUP2 CS MODE DO80

LD CP

CUP2 MODE0 MODE1 DO112 CKV D[112:1]

SPL512A

SPLD80A

CUP1

0.1

SPLD112A

CUP1 0.1 VDD

DIN

CKV

O[80:1]

D[80:1]

D[112:81] COM[32:1]

RESBP = ROSC / 32

SEG[80:1]

SEG[160:81]

LCD PANEL

Figure 3: Application circuit use SPLD80A and SPLD112A to driver LCD panel

Sunplus Technology Co., Ltd.

VEE

0.1

VEE

Rev.: 1.1

0.1

0.1

VEE

0.1

0.1

0.1

0.1

2000.02.15

SPLD112A

R1

R1

R2

R1

R1

VR VBB 0.1

VSS2

0.1

0.1

0.1

0.1

0.1

VEE

1. Doubler - VBB short to VSS2 2. Tripler - VBB short to VEE

LCDEN

V1

V2

V3

V4

V5 MEN VEE 0.1

V1

V2

V3

V4

V5 MEN VEE VSS2 0.1 0.1

V1

V2

V3

V4

V5 MEN VEE 0.1 VSS2

FP DF SPL512A LP LD DF

0.1

VSS2 DF

SPLD80A

CUP1 CUP2 CS MODE 0.1

SPLD80A

LD

DF CUP1 0.1 CUP2 CS MODE

SPLD112A

0.1 CUP1 0.1 CUP2

LD

CP IO RESBP

CP DIN

CP DIN

CP

MODE1 MODE0

DO80 CKV O[80:1] CKV O[80:1]

DO80

DIN CKV D[112:1]

DO112

V DD

RESBP = ROSC /32

SEG[80:1] SEG[160:81] SEG[256:161] COM[16:1]

LCD PANEL

Figure 4: Application circuit use SPLD80A and SPLD112A to driver LCD panel

Sunplus Technology Co., Ltd.

10

Rev.: 1.1

2000.02.15

SPLD112A
The application circuit in Figure (1) uses SPL512A to control SPLD112A. (1) Connect substrate to VDD or floating (2) R1 and R2 are depending on the type of LCD panel used. For example, a LCD panel with a 1/7 bias, R1 and R2 must be 7K adjustment (3) The pin LCDEN of SPLD512A is connected to MEN of SPLD112A for enabling or disabling the LCD display and to avoid DC path current at sleep mode. (4) CP is the shift register clock for data shifting. (5) CKV is the CLK source for supplying the Charge Pump to generate a double/triple voltage level (The range of CKV is between 50KHz and 300KHZ; the value is depended on the loading between VDD and VEE). If CP frequency range is closed to CKV, it is possible to short CP and CKV together. and 21K respectively. That is,R1/(4R1+R2) should be 1/7; VR is contrast

80 CP DIN LD D1 ... D80

80

Figure 5: Timing Charts for Application Example in segment Driver Operation

1 LD DO112

32

DF VDD D81 V1 V4 V5

Figure 6: Timing Charts for Application Example in Common Driver Operation

Sunplus Technology Co., Ltd.

11

Rev.: 1.1

2000.02.15

SPLD112A
Followed is the recommended CKV frequency range. Rload Range(Depend on LCD Panel Size) 120K < Rload < 300K 80K < Rload < 120K 30K < Rload < 80K Note: Rload = 4R1 + R2 + VR CKV Better Range(Hz) 50K - 150K 100K - 200K 200K - 300K CKV Available Range 50K - 200K 100K - 300K 200K - 400K

Timing For LCD Panel Dimension (80 Segments * 32 Commons) IO Assignments: FP = DO112 Mode[1,0] = [High, High] LCD SEGMENTS[80..1] = O[80..1] LCD COMMONS[32..1] = O[112..81]

Voltage Define: DF=1 COMMON-Selection Alternative Voltage COMMON-NonSelection Alternative Voltage SEGMENTS Turn ON Voltage SEGMENTS Turn OFF Voltage So, LCD Pixel Turn ON Differential Voltage = (VDD - V5) VDD V4 V5 V3 DF=0 V5 V1 VDD V2

Note: Data of COM1 Should be shifted to SPLD112 before the FP Change to High (which indicate the Start of Frame).

Sunplus Technology Co., Ltd.

12

Rev.: 1.1

2000.02.15

SPLD112A
FP

DF

1 Frame 1 Duty 1 2 3 30 31 32 1 2 3 30 31 32 1

LD COM1 Selected Period VDD V1 V2 V3 V4 V5 COM2 Selected Period VDD V1 V2 V3 V4 V5

COM1

COM2

LD 1 CP 2 3 ... 78 79 80 1

DIN

...

SEG

Sunplus Technology Co., Ltd.

13

Rev.: 1.1

2000.02.15

SPLD112A
Timing Characteristic for Operation (Operation Condition: Voltage = 5V, CP Frequency = 5MHz ) Parameter Data Latch In Setup Time Data Latch In Hold Time CP Low to LD High LD High Width LD Low to Common-Outputs LD High to Segment-Outputs DF transition to FP High LD Low to FP Low (Hold Time) Symbol TSD TDH TCL TWLD TLCOM TLSEG TDFFP TLDFP Min. 40 40 20 100 Max. 500 Unit Ns Ns Ns Ns Ns Ns Ns Ns

Depend On Load Depend On Load 100 100 -

Note that the Signal of CP and FP must be NonOverlap

TWCP CP80 TSD TDH CP1

CP

DI

TCL LD

TWLD

TLC

TLSEG

TLCOM

SEGMENTS

COMMONS

LD

LD1 TLDFP

LD2

FP

TDFFP

DF

Sunplus Technology Co., Ltd.

14

Rev.: 1.1

2000.02.15

SPLD112A
PAD ASSIGNMENT AND LOCATIONS PAD Assignment

Chip Size: 6480 m x 3889 m This IC substrate should be connected to VDD

Note: To ensure that the IC functions properly, please bond all of VDD, VSS, AVDD and AVSS pins.

Ordering Information Product Number SPLD112A-nnnnV-C Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (V = A - Z). Package Type Chip form

NOTE: SUNPLUS TECHNOLOGY CO., LTD reserves the right to make changes at any time without notice in order to improve the design and performance to supply the best possible product.

Sunplus Technology Co., Ltd.

15

Rev.: 1.1

2000.02.15

SPLD112A
PAD Locations Pad No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pad Name D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 D72 D73 D74 D75 D76 D77 X -3076 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -2913 -2751 -2607 -2463 -2323 -2188 -2047 -1912 Y 1786 1417 1272 1127 992 857 722 587 452 317 181 46 -94 -229 -369 -510 -651 -786 -926 -1070 -1214 -1376 -1538 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 Pad No 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pad Name D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 X -1772 -1631 -1490 -1355 -1215 -1080 -940 -805 -664 -529 -389 -254 -113 21 161 296 436 571 712 847 987 1122 1263 1398 1538 1673 1808 1943 2078 2213 2354 2502 Y -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787

Sunplus Technology Co., Ltd.

16

Rev.: 1.1

2000.02.15

SPLD112A
Pad No 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 Pad Name D110 D111 D112 CKV V5 V4 MODE0 V3 DF VSS LD MODE1 DO112 MEN V2 CUP2 CUP1 DIN VSS2 CP VDD V1 VEE D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 X 2649 2795 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 2810 2654 2503 2348 2213 2078 1943 1808 Y -1787 -1787 -1671 -1510 -1349 -1192 -1041 -889 -754 -615 -480 -340 -205 -66 68 208 343 482 617 757 892 1029 1174 1318 1471 1645 1786 1786 1786 1786 1786 1786 1786 1786 Pad No 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Pad Name D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 X 1673 1538 1398 1263 1122 987 847 712 571 436 296 161 21 -113 -254 -389 -529 -664 -805 -940 -1080 -1215 -1355 -1490 -1631 -1772 -1912 -2047 -2188 -2323 -2463 -2607 -2751 -2913 Y 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786

Sunplus Technology Co., Ltd.

17

Rev.: 1.1

2000.02.15

SPLD112A
DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. reference purposes only. Please note that application circuits illustrated in this document are for

Sunplus Technology Co., Ltd.

18

Rev.: 1.1

2000.02.15