Professional Documents
Culture Documents
p dng cho ngnh K thut My tnh Ti liu tham kho: - ASIC lp trnh c, Tng Vn On, NXB Thng K, 2004 - Thit k h thng VLSI, inh S Hin, NXB HQG TPHCM
Slide 2
Trn mch ch c th cha c t 1 n 10 cng logic (NAND, NOR, .v.v.) Ch yu p dng cho cc bi ton nh nh thit k cc my tnh in t cm tay.
Slide 3
VD My tnh cm tay Hnh 1.1 Kch thc chip ln nhng chc nng nh
Slide 4
Ngoi vic tch hp cc cng logic, cc mch cn c m rng tch hp thm cc b m v cc chc nng logic tng ng .
Slide 5
c tch hp vi nhiu chc nng logic hn, thm ch c c b vi x l hon chnh trong mt chip.
Slide 6
V d chip iu khin mn hnh LCD Hnh 1.2 Kch thc IC gim nhng chc nng ln
Slide 7
Mi th u c trong mt chp. c cc b x l 64 bt, cc b s hc du phy ng. Trn mt triu transistor ch trn mt ming Silic
Slide 8
Slide 9
Slide 10
Slide 11
Slide 12
Slide 13
Slide 14
1.3. ASIC l g?
ASIC vit tt ca: Application-Specific Integrated Circuit L mt IC c thit cho mt mc ch hoc mt h thng c th (Full custom IC ) Thc cht l mt di cc transistor MOS cha c kt ni. Vic kt ni to thnh mch c th phc thuc vo ngi s dng
Thi nguyn 08/2008 Thit k vi mch VLSI - ASIC - FPGA
Slide 15
1.4. FPGA l g?
FPGA l tp hp cc cell logic lp trnh c ni vi nhau bng ma trn chuyn mch lp trnh c. tr thnh mt mch c th, ma trn chuyn mch s c lp trnh nh tuyn cc tn hiu gia cc khi logic
Slide 16
1.4. FPGA l g?
Cu trc ca FPGA
Cc khi logic c bn lp trnh c (logic block) H thng mch lin kt lp trnh c Khi vo/ra (IO Pads) Phn t thit k sn khc nh DSP slice, RAM, ROM, nhn vi x l...
Slide 17
Slide 18
Slide 19
Slide 20
1.4. FPGA l g?
So snh FPGA vi ASIC
Xt cng mt ng dng th thit k trn ASIC t c mc ti u hn thit k trn FPGA FPGA hn ch trong cc tc v c bit FPGA c kh nng ti lp trnh n gin, thit k ng dng d dng nn chi ph v thi gian sn xut gim.
Slide 21
1.4. FPGA l g?
Cc chip FPGA v ASIC cng vi cc gi phn mm thit k mch thng c cc cng ty thit k sn cho ngi s dng nh Xilinx, Altera. Cc gi phn mm ny tch hp y quy trnh t bt u n ra sn phm, mi thao tc hon ton trong sut vi ngi s dng
Thi nguyn 08/2008 Thit k vi mch VLSI - ASIC - FPGA
Slide 22
tng
Thit k
M phng Chy th
Lp trnh ln mch
Slide 23
1.4. FPGA l g?
ng dng:
X l tn hiu s, hng khng, v tr, quc phng, tin thit k mu ASIC (ASIC prototyping), nhn dng nh, nhn dng ting ni, mt m hc, m hnh phn cng my tnh...
Slide 24
1.4. FPGA l g?
ng dng:
Do tnh linh ng cao trong qu trnh thit k cho php FPGA gii quyt lp nhng bi ton phc tp m trc kia ch thc hin nh phn mm my tnh Ngoi ra nh mt cng logic ln FPGA c ng dng cho nhng bi ton i hi khi lng tnh ton ln v dng trong cc h thng lm vic theo thi gian thc.
Thit k vi mch VLSI - ASIC - FPGA
Slide 25
Slide 26
1 l tt cc cell hoc transistor c lin kt y vi nhau, khi c lp trnh h thng s ph b cc mi lin kt ch gi li cc lin kt thuc v mch. 2 l tt c cc cell hoc transistor cha c lin kt, h thng lp trnh s to lin kt gia cc cell to thnh mch.
Slide 27
Slide 28
Slide 29
Slide 30
Slide 31
Slide 32
Slide 33
Nguyn tc mc song song cho logic OR Nguyn tc mc ni tip cho logic AND
Vit hm cho F (dng ba cacno nhm phn t 1) Vit hm cho F (dng ba cacno nhm phn t 0, hoc ly o ca F)
Thit k vi mch VLSI - ASIC - FPGA
Slide 34
f
F = a.b {dng mch ni tip} F = a + b {dng mch song song}
0 0
1 0
1
Thi nguyn 08/2008 Thit k vi mch VLSI - ASIC - FPGA
1
Slide 35
F = a.b b VSS
Slide 36
F = a.b
b
Slide 37
a
b
F= a+b
Slide 38
F= a+b
Slide 39
Thit k mch thc hin hm logic sau s dng phn t c bn CMOS F = a.b.c // phn t and 3 u vo F = a + b + c // phn t or 3 u vo F = a.b.c + a.d + e
Slide 40
Slide 41
Slide 42
Slide 43
Slide 44
MUX l phn t c bn to ra cc khi logic trong thit k cho ASIC MUX cn c dng thit k ra cc phn t logic c bn v cc mch logic. (s c chi tit chng 4)
Slide 45
Slide 46
Lin kt lp trnh c
ASIC/FPGA c cu to t cc phn t hoc cc khi logic c bn. Cc khi ny c lin kt vi nhau mt cch ton din, tc l mi tip im u c lin kt vi nhau Cc lin kt ny s tr nn dn khi khi c lp trnh, gi l antifuse phn cu tr
Thi nguyn 08/2008 Thit k vi mch VLSI - ASIC - FPGA
Slide 47
Slide 48
Slide 49
Slide 50
Slide 51
Source
Drain
electrons
Slide 52
Source
Drain
No channel
Slide 53
Source
Drain
No channel
Slide 54
Source
Drain
Slide 55
EEPROM cng tng t EPROM ch khc l thay v dng nh sng cc tm xa chip( tc y cc in cc v v tr nn) th loi ny cng c th dng in xa.
Slide 56
Slide 57
Dn nhp
Cc ASIC hoc cc FPGA u cu to t cc cell logic c bn, c b tr lin tip trn chip. C 3 loi cell c s dng:
Cell da trn b ghp knh Cell da vo bng tm kim Cell da vo mch logic di lp trnh c
Slide 58
Slide 59
Slide 60
Slide 61
Slide 62
Slide 63
Slide 64
Slide 65
Slide 66
Slide 67
4.1.3. To hm t ACT1
S dng ACT1 to ra cc phn t logic c bn v cc hm logic thng dng
Slide 68
4.1.3. To hm t ACT1
Bi tp:
1. Thit mch cho cc hm sau s dng ACT1 F1 = a.b.c.d F2 = a+b+c+d F3 = F3 2. Thit k b cng 4 bit s dng ACT1 3. p dng nh l shannon vo MUX gii bi 1 4. Thit mch thc hin hm sau:
F = a + b + a.d + b.d
Slide 69
Slide 70
Slide 71
Slide 72
F
c
00 01 10 11 0 0 0 1
0
GM
1
Thi nguyn 08/2008
Slide 73
b
c
GM
111
Slide 74
Slide 75
Slide 76
Slide 77
Slide 78
Slide 79