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  • The Basic Adder in Verilog

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    rx10
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    VERILOG(VHDL) BASIC ADDER CODE BEAUTIFUL EXECUTION OF CARRY LOOK AHEAD ADDER CODE WITH LOW DELAY

    Original Title

    THE BASIC ADDER IN VERILOG

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    VERILOG(VHDL) BASIC ADDER CODE BEAUTIFUL EXECUTION OF CARRY LOOK AHEAD ADDER CODE WITH LOW DELAY

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    14 views1 page

    The Basic Adder in Verilog

    Uploaded by

    rx10
    VERILOG(VHDL) BASIC ADDER CODE BEAUTIFUL EXECUTION OF CARRY LOOK AHEAD ADDER CODE WITH LOW DELAY

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 1

    module v1(a,b,p,g);

    integer i;
    input [0:7] a;
    input [0:7] b;
    output [0:7] p ;
    output [0:7] g;
    initial
    begin
    //for (i=0;i<8;i=i+1)
    p[i] = a[i] ^ b[i];
    g[i] = a[i] | b[i];
    end
    endmodule

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