I HC QUC GIA TP.

HCM TRNG I HC BCH KHOA

KHOA KHOA HC V K THUT MY TNH

TH NGHIM VI X L - VI IU KHIN

BM K thut My tnh
2011

Mc Lc
Mc Lc .............................................................................................................................. 1 Bi 1 : Gii thiu MPLAB IDE v KIT PIC .................................................................. 1 1.1 Mi trng pht trin MPLAB ................................................................................. 1 1.2 Np file hex vo vi iu khin PIC........................................................................... 6 1.3 Debug dng MpLab SIM ........................................................................................ 10 1.4 Debug onchip dng Mplab ICD2............................................................................ 12 1.5 Bi tp ..................................................................................................................... 12 Bi 2 : Kho st cng xut nhp ................................................................................... 13 2.1 Kin thc lin quan................................................................................................. 13 2.1.1 Cc thanh ghi iu khin cng xut nhp ........................................................ 13 2.1.2 Kt ni mch .................................................................................................... 13 2.2 Cc bc hin thc yu cu 1 ................................................................................. 14 2.3 Chng trnh mu yu cu 1................................................................................... 16 2.4 Cc bc hin thc yu cu 2 ................................................................................. 17 2.5 Chng trnh mu yu cu 2................................................................................... 18 2.6 Bi tp ..................................................................................................................... 19 Bi 3 : Kho st c ch ngt qung, giao tip LCD k t ............................................ 21 3.1 Kin thc lin quan................................................................................................. 21 3.1.1 Tm tt cc thanh ghi iu khin ngt ............................................................. 21 3.2 Cc bc hin thc yu cu 1 ................................................................................. 22 3.3 Chng trnh mu yu cu 1................................................................................... 24 3.4 LCD k t 2x16 ...................................................................................................... 26 3.4.1 Hnh dng v ngha cc chn: ....................................................................... 26 3.4.2 T chc vng nh ca LCD............................................................................. 27 3.4.3 Cc lnh giao tip vi LCD ............................................................................. 30 3.4.4 Khi to LCD................................................................................................... 30 3.5 Cc bc hin thc yu cu 2 ................................................................................. 32 3.6 Bi tp ..................................................................................................................... 37 Bi 4 : Kho st b nh thi ........................................................................................ 37 4.1 Cc bc hin thc yu cu 1 ................................................................................. 38 4.2 Chng trnh mu ................................................................................................... 39 4.3 Bi tp ..................................................................................................................... 41 Bi 5 : K thut qut ma trn phm .............................................................................. 42 5.1 Kt ni mch ma trn phm..................................................................................... 42 5.2 Cc bc hin thc ................................................................................................. 43 5.3 Bi tp ..................................................................................................................... 47 Bi 6 : K thut qut LED ............................................................................................ 48 6.1 Cu to LED 7 on v LED ma trn ..................................................................... 48 6.2 Kt ni mch ........................................................................................................... 50 6.3 Cc thanh ghi lin quan v cch iu khin............................................................ 51 6.4 Cc bc hin thc. ................................................................................................ 54 6.5 Bi tp ..................................................................................................................... 57 Bi 7 : Kho st b truyn nhn ni tip ...................................................................... 58 7.1 Cc bc hin thc. ................................................................................................ 58

7.2 Chng trnh mu ................................................................................................... 60 7.3 Bi tp ..................................................................................................................... 62 Bi 8 : Kho st khi chuyn i A-D.......................................................................... 63 8.1 Cc bc hin thc ................................................................................................. 63 8.2 Bi tp ..................................................................................................................... 64 Bi 9 : Kho st cc khi chc nng c bit khc ...................................................... 65 9.1 Cc bc hin thc PWM....................................................................................... 65 9.2 Chng trnh mu ................................................................................................... 66 9.3 Bi tp ..................................................................................................................... 67

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Khoa KH & KTMT

Bi 1 :

Gii thiu MPLAB IDE v KIT PIC

Ni dung : To project trn MPLAB IDE. Vit chng trnh ASM. Dch v np chng trnh vo vi iu khin PIC. Chy v g ri chng trnh. 1.1 Phn cng th nghim ICD2 v PICDEM 2 PLUS. B h tr lp trnh dng vi my tnh ICD2 (In-Circuit Debugger).
Cng ni tip ICD2 USB Ni vi card PICDEM Ni vi my tnh S kt ni ICD2

Kit th nghim PICDEM 2 Plus c cc c im nh hnh sau :

1. 2. 3. 4. 5. 6. 7. 8. 9.

cm DIP 18, 28 v 40 chn (c th cm 3 linh kin nhng ch dng 1 mi ln). n p +5V dng cho ngun 9V, 100 mA AC/DC hay pin 9V. u cm DB-9 theo chun giao tip RS-232. u cm qua b lp trnh In-Circuit Debugger (ICD). Bin tr 5K dng cho tn hiu nhp tng t. Ba nt nhn dng to tn hiu kch t bn ngoi v reset. LED ngun. Bn LED ch th cho PORTB. Jumper J6 ngt LED ch th RB0 (khi nhp tn hiu t nt nhn RB0). 1 Thc hnh Vi x l

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Trng H. Bch Khoa TP.HCM 10. B dao ng (OSC) 4 MHz. 11. Ni lp thm thch anh dao ng nu cn. 12. Thch anh dao ng 32.768 kHz to xung clock cho Timer1. 13. Jumper J7 ngt dao ng RC c sn (khong 2 MHz). 14. EEPROM ni tip 32K x 8 bit. 15. Mn hnh LCD. 16. Kn Piezo. 17. Vng lp thm linh kin. 18. Cm bin nhit TC74.

Khoa KH & KTMT

1.2 Mi trng pht trin MPLAB Bc 1. Chy phn mm MPLAB: Start_|All Programs_|Microchip_|MPLAB IDE v8.00_|MPLAB IDE. Bc 2. Chn Menu : Project_|Project Wirazd

Chn Next ca s Welcome

Bc 3. Chn s hiu PIC cn s dng (PIC18F4520) ri bm Next:

Bc 4. Chn tool Microchip MPASM Toolsuite ti Active Toolsuite.

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Chn MPASM Assembler (mpasmwin.exe) ti Tollsuite Contents.

Click Next qua ca s k. Bc 5. Nhn Browse chn th mc v nh tn project.

Chn th vin thng qua file .INC v .LKR thm vo project B mn K Thut My Tnh 3 Thc hnh Vi x l

Trng H. Bch Khoa TP.HCM C:\Program Files\Microchip\MPASM Suite\LKR\18f4520.lkr C:\Program Files\Microchip\MPASM Suite\P18F4520.INC

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Click Next s thy nh sau :

Click Finish. Ta s c mt project nh hnh sau:

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Bc 6. Thm file vo d n theo cc bc sau : Mt project n gin nht phi gm c 2 thnh phn Source files v Hearder Files. Th mc Source files cha file text *.asm hoc file *.c cha code lp trnh. Th mc Hearder Files cha file *.h hoc *.INC: file c sn ca microchip. Nu bn qun khng thm cc file cn c vo th lm theo hng dn sau : ADD header file: ( Copy header file vo th mc cha project tin cho vic s dng sau ny).

ca s la chn

Chn header file ph hp vi PIC mnh chn. Open. ADD source file: Click chn New trn toolbar: Ca s hin ln nh sau: T Menu bar chn File_|Save lu.

Thc hin Save, t tn vi ui .asm vo th mc cha d n. Nhp phi vo Source Files chn Add file >>> chn file chng ta va to xong. Chng ta hon tt vic thm file vo cc th mc Source files v Header files.

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Cng vic tip theo l vit code (trong ca s text editor ca source file). i vi project ln dng nhiu source file v header file, ta lm li qu trnh thm file vo d n nhiu ln. 1.3 Np file hex vo vi iu khin PIC Sau khi to c mt project, ta tin hnh build n to ra *.hex. C th m t cng vic nh sau: V d, ta c mt chng trnh cho PIC nh sau: ;=================================================== ; Name: BaiTN1.asm ; Project: Nhap du lieu tu nut nhan RA4. ; Khi nut RA4 duoc nhan thi led don RB0 sang, ; Khi khong nhan RA4 thi led don RB0 tat ; Author: BKIT HARDWARE CLUB ; Homepage: http://www.bkit4u.com/forum ; Creation Date: 7 - 31 - 2009 ;=================================================== list p=18f4520 #include p18f4520.inc code 0 goto start ;vung dinh nghia du lieu udata ;vung dinh nghia cac chuong trinh con PRG code start call init ;chuong trinh chinh main ;cho nhan nut RA4 btfsc PORTA,RA4 bra main bsf LATB,RB0 ;Bat LED RB0 swoff btfss PORTA,RA4 ;cho nhan nut RA4 bra swoff bcf LATB,RB0 ;tat LED RB0 bra main ;Lap lai cong viec ;chuong trinh khoi dong ban dau init bcf TRISB,RB0 ;khoi dong RB0 la cong xuat bsf TRISA,RA4 ;khoi dong RA4 la cong nhap return end By gi chng ta lu chng trnh va vit thnh BaiTN1.asm vo mt th mc to project pha trn. compile chng trnh ta vo menu Project_|Build All nh hnh bn di. B mn K Thut My Tnh 6 Thc hnh Vi x l

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Nu vic build tht bi, nhng vic ny th khng mong mun, ta c thy kt qu nh hnh sau:

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Trng H. Bch Khoa TP.HCM Nu thnh cng, ta s thy hnh sau:

Khoa KH & KTMT

Nu vic build thnh cng, chng trnh s dch BaiTN1.asm thnh BaiTN1.hex trong cng th mc chng trnh BaiTN1.asm. Sau khi c c file hex, cng vic tip theo l lm th no np c file Hex xung board. u tin, chn mch np bng cch vo menu Programmer_|Select Programmer_|Mplab ICD2 nh hnh sau :

Sau khi chn Mplab ICD2 xong th ta s thy giao din nh sau:

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Mt thao tc cn lm gip ta c th dch chng trnh, np v chy t ng l vo menu Programmer_|Settings_|Program chn mc Automatically nh hnh sau :

By gi ta c th dch, np v chy d n vi thao tc menu Project_|Build All (hoc nhn Ctrl-F10).

Nu thnh cng th chng trnh s c dch, np ra card PICDEM v chy ngay.

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Nu tht bi, xem thng tin bo li trong ca s Output khc phc v lm li t bc Build All. Trng hp thnh cng m chng trnh chy khng ng, ta phi s dng cng c Debugger tm li theo mt trong hai cch sau. 1.4 Debug dng MpLab SIM Bc 1. Chn Debugger bng menu Debugger_|Select Debugger_|Mplab SIM

Bc 2. Tham kho menu Debugger. Xut hin nhiu chc nng h tr debug.

T y ta c th m phng c chng trnh ca mnh mt cch d dng. Cc chc nng thng dng : Run (F9): chy chng trnh, chng trnh s chy lin tc n khi no c breakpoint th dng. Breakpoints (F2): to ra breakpoint ti v tr hin ti ca con tr (cng c th "double click" vo hng code mnh mong mun t Breakpoint). Step Into (F7): chy tng bc, vo trong chng trnh con (nu gp). Step Over (F8): chy tng bc, gi chng trnh con cng xem nh 1 bc. Reset: tr v u chng trnh. B mn K Thut My Tnh 10 Thc hnh Vi x l

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Bc 3. Khi debug th ta cng cn phi bit gi tr ca cc thanh ghi cng nh b nh ca chip nh th no, xem c cc gi tr ny th chng ta qua menu View. xem c gi tr ca cc thanh ghi trong PIC ta chn menu View_|File registers s xut hin ca s nh hnh sau:

xem c gi tr ca cc thanh ghi SFR th ta chn View_|Special Function Registers s xut hin ca s nh hnh sau:

Hay xem mt v thanh ghi m ta quan tm th c th dng Watch xem bng cch vo menu View_|Watch th hnh sau s xut hin:

Mun xem thanh ghi no, ta ch vic chn thanh ghi tng ng trong combobox bn trn, sau nhn Add SFR.

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1.5 Debug onchip dng Mplab ICD2.

Cng ging nh debug trn Mplab SIM, Mplab ICD2 cng c nhng tnh nng tng t, nhng khi s dng Mplab ICD2 th cn phi c mch debug, v cc hin tng xy ra ging nh khi chy thc t.

1.6 Bi tp
Ci tin chng trnh BaiTN1.asm khi nhn RA4 s thy 4 LED t RB3 n RB0 sng nh u ra mt b m 4 bit nh phn tng dn (mi ln nhn tng 1).

1.7 Bo co
Cc iu kin cn c tin hnh th nghim gm nhng g ? Cc bc cn lm np chng trnh ra card c chip vi iu khin. Cc bc cn lm tin hnh debug gi lp trn my hoc trn mch.

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Bi 2 :

Kho st cng xut nhp

Ni dung: Kho st hot ng ca nt nhn, LED. Kho st cc thanh iu khin cng xut nhp. Tnh ton thi gian thc thi lnh, vit chng trnh con lm nhim v delay. Vit chng trnh kim tra nt nhn v hin th kt qu kim tra ra LED. Yu cu: Vit chng trnh xut d liu ra 4 led n m t 0 -> 15 -> 0. Thi gian gia cc ln m ln 1 n v l 1s. Nhp d liu t nt nhn RA4. Khi nt RA4 c nhn th led n RB0 sng, khi khng nhn RA4 th led n RB0 tt.

2.1 Kin thc lin quan

2.1.1 Cc thanh ghi iu khin cng xut nhp Mi Port c ba thanh ghi iu khin hot ng chnh: Cc bit trong thanh ghi TRIS: thit lp chn tng ng l ng vo (logic 1) hoc ng ra (logic 0). Cc bit trong thanh ghi PORT: c mc logic t chn tng ng. Cc bit trong thanh ghi LAT: ghi mc logic ra chn tng ng. 2.1.2 Kt ni mch V tr LED hin th v nt nhn trn board nh hnh di y:

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Trng H. Bch Khoa TP.HCM LED hin th c kt ni nh sau:

Khoa KH & KTMT

Mun cc LED sng, cc chn RBi tng ng phi ln mc 1. Ring LED D2 cn phi ni jumper J6 li mi sng c khi RB0=1. L do c jumper JP6 l do chn RB0 cn c dng lm ng nhp nt nhn RB0. Nh vy, lc no mun dng chn RB0 l ng xut LED th ng jumper JP6 li. Ngc li, h JP6 s dng RB0 lm ng nhp nt nhn. Cc nt nhn c kt ni nh sau:

Nt nhn RA4, RB0 khi c nhn s lm cho chn tng ng mc logic 0. Cn thit lp cc chn RA4 v RB0 l ng vo. B dao ng chnh l b dao ng ngoi tn s 4 MHz c kt ni nh sau:

Trn kit th nghim, thch anh Y2 c s dng cho tt c cc bi th nghim.

2.2 Cc bc hin thc yu cu 1

Bc 1. To project mi ging nh hng dn chng 1 ly tn project l Led_don, to file led_don.asm v chn chip 18f4520. Ta c hnh sau:

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Bc 2. Include file p18f4520.inc vo file led_don.asm. Bc 3. Khi to PORTB l cng xut cc bit RB0-RB3. init clrf PORTB ; bcf TRISB,RB0 ; RB0 xut bcf TRISB,RB1 ; RB1 xut bcf TRISB,RB2 ; RB2 xut bcf TRISB,RB3 ; RB3 xut return Bc 4. To hm delay1ms c s dng bin delay (nh ngha trong udata) nh sau : udata delay res 1 ; nh ngha bin delay ... delay1ms ; Gn ng 1 ms vi xung clock 4 MHz clrf delay ; xa bin delay (vng lp 256 ln) dl_1 nop decfsz delay bra dl_1 return Bc 5. T y ta c th to ra c hm delay1s bng cch gi hm delay1ms 1000 ln delay1s movlw .4 movwf delay_1sa dl_2 movlw .250 ; bt u vng lp ngoi B mn K Thut My Tnh 15 Thc hnh Vi x l

Trng H. Bch Khoa TP.HCM movwf call decfsz bra decfsz bra return delay_1sb delay1ms delay_1sb dl_3 delay_1sa dl_2

Khoa KH & KTMT

dl_3

; bt u vng lp trong ; kt thc vng lp trong (250 lan) ; kt thc vng lp ngoi (4 ln)

Bc 6. Vit chng trnh cho hm begin thc hin cc yu cu ca bi : begin incf LATB call delay1s bra begin ; lp li sau mi giy

2.3 Chng trnh mu yu cu 1

;=====================================; ; Name: led_don.asm ; Project: Xut d liu ra 4 led n m t 0 15 0. ; Thi gian gia cc ln m ln 1 n v l 1s. ; Author: BKIT HARDWARE CLUB ; Homepage: http://www.bkit4u.com/forum ; Creation Date: 7 - 31 - 2009 ;======================================; list p=18f4520 #include p18f4520.inc code 0 goto start ; Vung du lieu udata delay res 1 delay_1sa res 1 delay_1sb res 1 ; Vung bat dau code PRG code start call init ; chuong trinh chinh begin incf LATB call delay1s bra begin ; Ham khoi dong ban dau init clrf PORTB bcf TRISB,RB0 bcf TRISB,RB1 bcf TRISB,RB2 bcf TRISB,RB3 return

; lap lai sau moi giay ; ; cau hinh RB0 xuat ; cau hinh RB1 xuat ; cau hinh RB2 xuat ; cau hinh RB3 xuat

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; Ham lam tre 1ms voi tan so dao dong 4MHz delay1ms ; Gan dung voi xung clock 4 MHz clrf delay ; xoa bien delay (vong lap 256 lan) dl_1 nop decfsz delay bra dl_1 return ; Ham lam tre 1s = 1000 x 1ms delay1s movlw .4 movwf delay_1sa dl_2 movlw .250 ; bat dau vong lap ngoai (4 lan) movwf delay_1sb dl_3 call delay1ms ; bat dau vong lap trong (250 lan) decfsz delay_1sb bra dl_3 ; ket thuc vong lap trong decfsz delay_1sa bra dl_2 ; ket thuc vong lap ngoai return end Sau khi c chng trnh mu ta thc hin vic compile chng trnh v np xung mch chy chng trnh nh hng dn chng 1.

2.4 Cc bc hin thc yu cu 2

Bc 1. To project mi ging nh hng dn chng 1 ly tn project l Nut_nhan v chn chip 18f4520. Ta c hnh sau:

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Bc 2. Include file p18f4520.inc vo file nut_nhan.asm. Bc 3. Khi to PORTB bit RB0 l cng xut (jumper JP6 ng) v PORTA bit RA4 l cng nhp. init clrf PORTB bcf TRISB,RB0 ; RB0 xut bsf TRISA,RA4 ; RA4 nhp return Bc 4. Vit chng trnh cho hm main thc hin yu cu ca bi main btfsc PORTA,RA4 ; ch n khi RA4 c nhn bra main bsf LATB,RB0 ; bt sng LED RB0 swoff btfss PORTA,RA4 ; ch n khi RA4 c nh bra swoff bcf LATB,RB0 ; tt LED RB0 bra main ; lp li qu trnh

2.5 Chng trnh mu yu cu 2

;=====================================; ; Name: nut_nhan.asm ; Project: Nhp d liu t nt nhn RA4. ; Khi nt RA4 c nhn th led n RB0 sng, ; Khi khng nhn RA4 th led n RB0 tt ; Author: BKIT HARDWARE CLUB ; Homepage: http://www.bkit4u.com/forum ; Creation Date: 7 - 31 - 2009 ;======================================; list p=18f4520 #include p18f4520.inc code 0 goto start ; Vung du lieu udata ; Chuong trinh nay khong su dung bien ; Vung bat dau code PRG code start call init ; chuong trinh chinh main btfsc PORTA,RA4 ; cho den khi RA4 duoc nhan bra main bsf LATB,RB0 ; bat sang LED RB0 swoff btfss PORTA,RA4 ; cho den khi RA4 duoc nha bra swoff bcf PORTB,RB0 ; tat LED RB0 goto main ; lap lai qua trinh ; Ham khoi dong ban dau init clrf PORTB bcf TRISB,RB0 ; RB0 xuat B mn K Thut My Tnh 18 Thc hnh Vi x l

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bsf TRISA,RA4 ; RA4 nhap return end Sau khi c chng trnh mu ta thc hin vic compile chng trnh v np xung mch chy chng trnh nh hng dn chng 1.

2.6 Bi tp
a) Vit chng trnh khi nhn RA4 th cc led s sng m ln, mi ln nhn m ln 1 n v. b) Vit chng trnh sao cho mi ln nhn RA4 th 2 led tri v 2 led phi thay nhau sng. c) To hiu ng light river trn 4 led ca board mch starter kit. Nhn RA4 thay i chiu ca light river.

2.7 Bo co
Cn lm nhng g c th s dng cng giao tip song song? Gii thch ti sao dng LATB v PORTB lc ging nhau, lc khc nhau. Hy tnh thi gian chnh xc ca vng lp delay.

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Bi 3 : Kho st c ch ngt qung, giao tip LCD k t

Ni dung: Kho st cc nguyn nhn gy ngt qung, cch x l ngt qung, tnh u tin gia cc ngt ca vi iu khin PIC 18F4520. Kho st ngt ngoi ca vi iu khin PIC 18F4520. iu khin LCD k t 2 x 16. Yu cu: 1. Vit chng trnh khi to 2 ngt: Ngt ngoi INT0 (nhn ngt qua nt nhn RB0, Jumper JP6 h) vi u tin cao. Ngt timer 0 vi u tin thp. Trong chng trnh ngt ngoi INT0 bt 3 led n RB1, RB2, RB3 sng cng lc. Trong chng trnh timer 0 sau 1s khi 3 led c bt trong ngt ngoi th tt 3 led n RB1, RB2, RB3 cng lc. 2. Vit chng trnh hin th k t ln LCD.

3.1 Kin thc lin quan

3.1.1 Tm tt cc thanh ghi iu khin ngt Thanh ghi INTCON:

Thanh ghi PIE1:

Thanh ghi PIE2:

Thanh ghi PIR1:

Thanh ghi PIR2:

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Trng H. Bch Khoa TP.HCM S iu khin ngt:

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3.2 Cc bc hin thc yu cu 1

Bc 1. To project mi ging nh hng dn chng 1 ly tn project l Interrupt, to file interrupt.asm v chn chip 18f4520. Ta c hnh sau:

Bc 2. Include file p18f4520.inc vo file interrupt.asm Bc 3. Khi to PortB l output s dng cc lnh clrf, bcf init clrf LATB ; RB1-RB3 la cong xuat movlw 0x0F

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movwf ADCON1 bsf TRISB,RB0 bcf TRISB,RB1 bcf TRISB,RB2 bcf TRISB,RB3 movlw .10 ; khoi dong bien delay=10 movwf delay return Bc 4. Khi to timer 0 to ngt 100 ms (vi xung clock 4 MHz, chn prescaler 2:1, s m 50000), cho ngt timer 0 c u tin thp. init_timer0 bsf RCON,IPEN ; cho phep uu tien ngat. bcf INTCON2,TMR0IP ; timer0 uu tien thap bcf INTCON,TMR0IF ; xoa co ngat timer0 bsf INTCON,TMR0IE ; cho phep ngat timer0 bsf INTCON,GIEH ; cho phep ngat uu tien cao bsf INTCON,GIEL ; cho phep ngat uu tien thap clrf T0CON ; prescaler 2:1 movlw HIGH (-50000) ; nap so dem 50000 cho timer0 movwf TMR0H movlw LOW (-50000) movwf TMR0L bsf T0CON,TMR0ON ; cho phep timer0 dem return Bc 5. Khi to ngt ngoi 0 tch cc cnh xung. i vi ngt ngoi INT1 v INT2, u tin ph thuc vo 2 bit INT1IP v INT2IP trong thanh ghi INTCON3. Cn vi ngt ngoi INT0 th u tin lun l cao. init_int0 bcf INTCON2,INTEDG0 ; tac dong canh xuong bcf INTCON,INT0IF ; xoa co ngat bsf INTCON,INT0IE ; cho phep ngat ngoai INT0 return Bc 6. Vit chng trnh cho ngt ngoi 0, bt 3 n led n cng sng v khi to li gi tr cho bin delay 1s sau th ngt timer s tt 3 n . int0_isr bcf INTCON,INT0IF bsf LATB,RB1 bsf LATB,RB2 bsf LATB,RB3 movlw .10 movwf delay return Bc 7. Vit chng trnh cho ngt timer0, sau 1s sau khi led c bt sng th n s lm cho led tt. Thi gian timer m ln 1 n v c tnh bng cng thc : t = (1/(Focs/4))*prescaler = (1/(4Mhz/4))*2) =2s

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Nh vy, mun c thi khong 100 ms (100000s), ta cn m 50000 ln. timer0_isr bcf INTCON,TMR0IF decfsz delay,1 bra timer0_isr_1 bcf LATB,RB1 bcf LATB,RB2 bcf LATB,RB3 movlw .10 movwf delay timer0_isr_1 bcf T0CON,TMR0ON movlw HIGH (-50000) ; nap lai so dem 50000 cho timer0 movwf TMR0H movlw LOW (-50000) movwf TMR0L bsf T0CON,TMR0ON ; cho phep timer0 dem lai return

3.3 Chng trnh mu yu cu 1

;=====================================; ; Name: led_don.asm ; Project: Vit chng trnh khi to 2 ngt: ; -Ngt ngoi 0 vi u tin cao. ; -Ngt timer 0 vi u tin thp. ; -Ngt INT0 : bt 3 led n RB1, RB2, RB3 sng cng ;lc ; -Ngt timer0 : tt 3 led n RB1, RB2, RB3 sau 1s ; Author: BKIT HARDWARE CLUB ; Homepage: http://www.bkit4u.com/forum ; Creation Date: 7 - 31 - 2009 ;======================================; list p = 18f4520 #include P18f4520.inc code 0 goto main org 08H goto isr_high org 18H goto isr_low ; Vung du lieu udata delay res 1 ; Vung bat dau code PRG code main call init B mn K Thut My Tnh 24 Thc hnh Vi x l

Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

call init_timer0 call init_int0 goto $ ; Ham khoi dong ban dau init clrf LATB ; RB1-RB3 la cong xuat movlw 0x0F movwf ADCON1 bsf TRISB,RB0 bcf TRISB,RB1 bcf TRISB,RB2 bcf TRISB,RB3 movlw .10 ; khoi dong bien delay=10 movwf delay return ; Ham khoi dong timer0 init_timer0 bsf RCON,IPEN ; cho phep uu tien ngat. bcf INTCON2,TMR0IP ; timer0 uu tien thap bcf INTCON,TMR0IF ; xoa co ngat timer0 bsf INTCON,TMR0IE ; cho phep ngat timer0 bsf INTCON,GIEH ; cho phep ngat uu tien cao bsf INTCON,GIEL ; cho phep ngat uu tien thap clrf T0CON ; prescaler 2:1 movlw HIGH (-50000) ; nap so dem 50000 cho timer0 movwf TMR0H movlw LOW (-50000) movwf TMR0L bsf T0CON,TMR0ON ; cho phep timer0 dem return ; Ham khoi dong int0 init_int0 bcf INTCON2,INTEDG0 ; tac dong canh xuong bcf INTCON,INT0IF ; xoa co ngat bsf INTCON,INT0IE ; cho phep ngat ngoai INT0 return ; Ham xu ly ngat timer0 timer0_isr bcf INTCON,TMR0IF decfsz delay,1 bra timer0_isr_1 bcf LATB,RB1 bcf LATB,RB2 bcf LATB,RB3 movlw .10 movwf delay timer0_isr_1

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Trng H. Bch Khoa TP.HCM bcf T0CON,TMR0ON movlw HIGH (-50000) movwf TMR0H movlw LOW (-50000) movwf TMR0L bsf T0CON,TMR0ON return ; Ham xu ly ngat int0 int0_isr bcf INTCON,INT0IF bsf LATB,RB1 bsf LATB,RB2 bsf LATB,RB3 movlw .10 movwf delay return ; Ham xu ly ngat uu tien cao isr_high call int0_isr retfie ; Ham xu ly ngat uu tien thap isr_low call timer0_isr retfie end

Khoa KH & KTMT

; nap lai so dem 50000 cho timer0

; cho phep timer0 dem lai

Sau khi c chng trnh mu ta thc hin vic compile chng trnh v np xung mch chy chng trnh nh hng dn chng 1.

3.4 LCD k t 2x16

3.4.1 Hnh dng v ngha cc chn:

Tn chn GND

Mc logic -

M t t (0V)

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Trng H. Bch Khoa TP.HCM VCC VEE RS

Khoa KH & KTMT

Ngun (+5V) Chnh contrast (0 VCC) 0 D0-D7 l gi tr lnh 1 D0-D7 l gi tr d liu 0 Ghi gi tr vo LCD R/W 1 c gi tr ra t LCD 0 Cm truy xut LCD E 1 LCD hot ng trao i d liu T 1 xung 0 D liu/Lnh a vo LCD 0/1 Bit 0/LSB D0 0/1 Bit1 D1 0/1 Bit2 D2 0/1 Bit3 D3 0/1 Bit4 D4 0/1 Bit5 D5 0/1 Bit6 D6 0/1 Bit7/MSB D7 Chn Anode ca n nn A Chn Cathode ca n nn K 3.4.2 T chc vng nh ca LCD Display Data Ram (DDRAM): lu tr m k t hin th ra mn hnh. M ny ging vi m ASCII. C tt c 80 nh DDRAM. Vng hin th tng ng vi ca s gm 16 nh hng u tin v 16 nh hng th hai. Chng ta c th to hiu ng dch ch bng cch s dng lnh dch (m t sau), khi ca s hin th s dch em li hiu ng dch ch.

Character Generator Ram (CGRAM): lu tr tm mu k t do ngi dng nh ngha. Tm mu k t ny tng ng vi cc m k t D7-D0 = 0000*D2D1D0 (* mang gi tr ty nh 0 hay 1).

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Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

Character Generator Rom (CGROM): lu tr cng cc mu k t tng ng vi m ASCII. Di y l bng nh x gia m k t v mu k t.

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Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

Chng ta mun hin th ch CE gia hng u tin, gi s ca s hin th ang bt u t v tr u tin (hng th nht hin th d liu ca nh t 0x00 n 0x0f, hng th hai hin th d liu ca nh t 0x40 n 0x4f, y l v tr home). Gi tr ca nh 0x07 l 0x43 (k t C), ca nh 0x08 l 0x45 (k t E). Chng ta mun hin th ch gi hng th hai, gi s c s hin th ang v tr home. Trong bng mu k t chng ta thy khng c mu . Lc ny chng ta phi nh ngha mu 5x8 im, gm c 8 byte, sau lu vo v tr ca mu k t CGRAM th nht. Lc ny gi tr ca nh 0x47 l 0x00 hoc 0x08 (v tr ca mu k t CGRAM th nht ).

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Trng H. Bch Khoa TP.HCM 3.4.3 Cc lnh giao tip vi LCD Lnh Clear display Return home Entry mode set Display on/off control Cursor/Display shift Function set RS 0 0 0 0 0 0 RW 0 0 0 0 0 0 D7 0 0 0 0 0 0 D6 0 0 0 0 0 0 D5 0 0 0 0 0 1 D4 0 0 0 0 1 DL D3 0 0 0 1 S/ C N D2 0 0 1 D R/ L F

Khoa KH & KTMT

D1 0 1

D0 1 *

Thi gian thc thi 1.52ms 1.52ms 37s 37s 37s 37s

I/D SH C * * B * *

Set CGRAM 0 0 0 1 CGRAM address 37s address Set DDRAM 0 0 1 DDRAM address 37s address Read BUSY flag 0 1 BF DDRAM address 0s (BF) Write to DDRAM or 1 0 D7 D6 D5 D4 D3 D2 D1 D0 43s CGRAM Read from DDRAM or 1 1 D7 D6 D5 D4 D3 D2 D1 D0 43s CGRAM Cc bit trn bng tm tt cc lnh c ngha nh sau: 1 Increment 0 Decrement I/D 1 Entire shift on 0 Entire shift off SH 1 Display shift 0 Cursor move S/C 1 Shift to the Right 0 Shift to the Left R/L 1 8 bits 0 4 bits DL 1 2 Lines 0 1 Lines N 1 5x10 dots Font 0 5x8 dots Font F 1 Internally operating 0 Can accept instruction BF Trn kit th nghim LCD k t 2x16 c kt ni vo Port D ch 4 bit. ch 4 bit, c hay ghi mt byte phi tin hnh ci d liu hai ln, ln u l 4 bit cao, ln th hai l 4 bit thp. 3.4.4 Khi to LCD S kt ni LCD:

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Trng H. Bch Khoa TP.HCM

VCC RD7 R20 2.2K Q2 MMBT2222A LCD1 Vss Vdd Vee RS R/W E D0 D1 D2 D3 D4 D5 D6 D7 A K

Khoa KH & KTMT

RD4 RD5 RD6

RD0 RD1 RD2 RD3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

LCD k t 2x16

Trc khi xut k t ra mn hnh LCD, LCD controller phi c khi to khi mi c cp ngun. Trnh t khi to nh lc sau. Trn lc , lnh Display clear c gi tr 0x01 c gi hai ln, ln u l 4 bit cao c gi tr 0x0, ln th hai l bn bit thp c gi tr 0x01. Lnh Function set gi hai ln gi tr 0x2.

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Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

Bt ngun (chn PD7 out ra mc logic 1)

Ch ti thiu 30ms (i VDD > 4.5V)

Ch ti thiu 39s

Gi lnh Function set RS RW D7 0 0 0 0 0 0 0 0 N D6 0 0 F D5 1 1 * D4 0 0 *

Gi lnh Display clear RS RW D7 0 0 0 0 0 0 D6 0 0 D5 0 0 D4 0 1

Gi lnh Entry mode set Ch ti thiu 39s RS RW D7 0 Gi lnh Display on/off control RS RW D7 0 0 0 0 0 1 D6 0 D D5 0 C D4 0 B Kt thc khi to 0 0 0 0 0 D6 0 1 D5 0 I/D D4 0 SH

3.5 Cc bc hin thc yu cu 2

Bc 1. To project mi ging nh hng dn chng 1 ly tn project l LCD, to file lcd.asm v chn chip 18f4520. Ta c hnh sau:

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Bc 2. Include file p18f4520.inc vo file lcd.asm Bc 3. Da vo s nguyn l kt ni vi iu khin vi LCD k t ta define li d dng s dng hn. #define LCD_D4 LATD, RD0 ; LCD data bits #define LCD_D5 LATD, RD1 #define LCD_D6 LATD, RD2 #define LCD_D7 LATD, RD3 #define LCD_D4_DIR TRISD, RD0 ; LCD data bits #define LCD_D5_DIR TRISD, RD1 #define LCD_D6_DIR TRISD, RD2 #define LCD_D7_DIR TRISD, RD3 #define #define #define #define #define #define LCD_E LCD_RW LCD_RS LATD, RD6 LATD, RD5 LATD, RD4 ; LCD E clock ; LCD read/write line ; LCD register select line

LCD_E_DIR TRISD, RD6 LCD_RW_DIR TRISD, RD5 LCD_RS_DIR TRISD, RD4

#define LCD_INS 0 #define LCD_DATA 1 Bc 4. Vit hm xut d liu 4 bit ra cho LCD k t : LCDWriteNibble btfss STATUS, C bcf LCD_RS btfsc STATUS, C bsf LCD_RS B mn K Thut My Tnh 33

; Set the register select

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Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

bcf LCD_RW ; Set write mode bcf LCD_D4_DIR ; Set data bits to outputs bcf LCD_D5_DIR bcf LCD_D6_DIR bcf LCD_D7_DIR nop ; Small delay nop bsf LCD_E ; Setup to clock data nop nop btfss temp_wr, 7 ; Set high nibble bcf LCD_D7 btfsc temp_wr, 7 bsf LCD_D7 btfss temp_wr, 6 bcf LCD_D6 btfsc temp_wr, 6 bsf LCD_D6 btfss temp_wr, 5 bcf LCD_D5 btfsc temp_wr, 5 bsf LCD_D5 btfss temp_wr, 4 bcf LCD_D4 btfsc temp_wr, 4 bsf LCD_D4 nop ; Small delay nop bcf LCD_E ; Send the data return Bc 5. Tip tc ta vit hm truyn lnh (command) cho lcd k t. Macro LCDWrite_command c mt i s l data, ta dng i s ny truyn lnh cho lcd. y, LCD ta thit lp ch 4 bt nn khi truyn lnh n cng ch cn 4 bit iu khin. Trong macro ny data1 ch s dng 4 bit cao m thi. LCDWrite_command macro data1 bcf LCD_RS ;write command movlw data1 movwf temp_wr call LCDWriteNibble movlw 0xF movwf delay rcall DelayXCycles endm Bc 6. Sau vit thm hm truyn d liu hin th ra LCD k t. Macro LCDWrite_data c mt i s l data1, ta dng macro vi i s tng ng truyn data hin th ln mn hnh LCD. Nh trn ta cp, trong ng dng ny ta s

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Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

dng LCD ch 4 bt, nn data y c truyn theo th t l 4 bit cao truyn trc sau 4 bt thp c truyn sau. LCDWrite_data macro data1 bsf LCD_RS ;write data movff data1,temp_wr rcall LCDBusy bsf STATUS, C rcall LCDWrite movlw 0x0F ;Wait ~100s @ 20 MHz movwf delay rcall DelayXCycles endm Bc 7. Hm quan trng nht ca LCD k t chnh l hm khi to LCD. Trc khi s dng c lcd ta phi khi to cho n theo nh gin khi to lcd trn phn hng dn l thuyt. Ngoi ra do thit k mch, LCD c th hin th bnh thng trc tin ta phi bt ngun ca LCD ln, chn ngun ca LCD c iu khin bi PortD.7 tch cc mc cao, nn trc khi mun s dng LCD ta phi bt PortD.7 ln 1. LCDInit1 call init_variable bsf LATD, RD7 bcf TRISD, RD7 bcf LCD_E_DIR ;configure control lines bcf LCD_RW_DIR bcf LCD_RS_DIR movlw b'00001110' movwf ADCON1 movlw 0xff ; Wait ~15ms @ 20 MHz movwf COUNTER lil11 movlw 0xFF movwf delay rcall DelayXCycles decfsz COUNTER,F bra lil11 LCDWrite_command 0x20 LCDWrite_command 0x20 LCDWrite_command 0x80 LCDWrite_command 0x00 LCDWrite_command 0xf0 LCDWrite_command 0x00 LCDWrite_command 0x10 call LongDelay ;2ms call LongDelay ;2ms LCDWrite_command 0x00 LCDWrite_command 0x20

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Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

call Lcd_clear return Bc 8. n y ta c th vit chng trnh hin th k t ln lcd k t. tng thc hin y l lc u ta khai bo mt vng nh gm 32 nh tng ng vi 32 v tr trn lcd k t. Hm lcd_display ca chng ta s thc hin mt vic n gin l ly d liu cha trong vng nh ny ra hin th ln lcd k t. Cn ngi dng mun hin th ln lcd th ch cn update gi tr vo vng nh ny l xong. Lcd_display movff INDF0,temp_wr1 movlw .0 cpfseq temp_wr1 goto Lcd_display1 movlw 0x20 movwf temp_wr1 Lcd_display1 LCDWrite_data temp_wr1 incf FSR0L clrf WREG addwfc FSR0H, F movlw .0 cpfseq flag_line goto Lcd_display_line2 ;display line1 incf index_of_lcd molw MAX_INDEX cpfseq index_of_lcd goto Exit_Lcd_display clrf Index_of_lcd movlw .1 movwf flag_line Set_cursor .0,.1 goto Exit_Lcd_display ;display line2 Lcd_display_line2 incf index_of_lcd movlw MAX_INDEX cpfseq index_of_lcd goto Exit_Lcd_display clrf Index_of_lcd movlw .0 movwf flag_line movlw HIGH Lcd_buffer movwf FSR0H movlw LOW Lcd_buffer movwf FSR0L

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Trng H. Bch Khoa TP.HCM Set_cursor .0, .0 Exit_Lcd_display return

Khoa KH & KTMT

3.6 Bi tp
a) Vit chng trnh kim tra pht hin rung phm RA4. b) Vit chng trnh chy ch qua LCD. c) Vit chng trnh thay i ch hin th trn LCD khi nhn nt.

3.7 Bo co
a) B cc ca chng trnh c s dng ngt qung. b) Dng ngt ngoi c trng thi nt nhn RA4 c b rung khng ? Lm sao bit chng rung ?

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Bi 4 :

Kho st b nh thi

Ni dung: Kho st cc ch hot ng ca cc b nh thi. Kho st cc thanh ghi iu khin b nh thi. S dng b nh thi trong chng trnh. Yu cu: S dng b timer0 c sau 1s m ln 1 n v ri xut gi tr ra led n. Vit chng trnh s dng b nh thi lm ng h iu khin n giao thng.

4.1 Cc bc hin thc yu cu 1

Bc 1. To project mi tn timer. Bc 2. To tp tin ngun timer.asm. Bc 3. Khi to PORTB l cng xut. init clrf PORTB ; ton b PORTB l cng xut clrf TRISB return Bc 4. Khi to cc vector ngt. a ch 0x00 bt u chng trnh chnh. a ch 0x08 a ch ca vector ngt c u tin cao. a ch 0x18 a ch ca vector ngt c u tin thp. code 0 goto main org 0x000008 ; vector ngt u tin cao goto isr_high org 0x000018 ; vector ngt u tin thp goto isr_low ; Vng nh ngha d liu udata bien res 1 ; Vng bt u code PRG code main call init ... ; chng trnh phc v ngt u tin cao isr_high ... retfie ; chng trnh phc v ngt u tin thp isr_low ... retfie Bc 5. Khi to ngt timer0 pht ra ngt 100ms (vi xung clock 4 MHz, chn prescaler 2:1, s m 50000). ;=====================; B mn K Thut My Tnh 38 Thc hnh Vi x l

Trng H. Bch Khoa TP.HCM ; Initializing timer 0: 16BIT ;=====================; init_timer0 bsf RCON,IPEN bcf INTCON2,TMR0IP bcf INTCON,TMR0IF bsf INTCON,TMR0IE bsf INTCON,GIEH bsf INTCON,GIEL clrf T0CON movlw HIGH (-50000) movwf TMR0H movlw LOW (-50000) movwf TMR0L bsf T0CON,TMR0ON return

Khoa KH & KTMT

; cho php dng u tin ngt. ; ngt timer0 u tin thp ; xa c bo ngt timer0 ; cho php ngt timer0 ; cho php ngt u tin cao ; cho php ngt u tin thp ; prescaler 2:1 ; np s m 50000 cho timer0

; cho php timer0 m

Bc 6. Vit chng trnh con chy trong timer, sau 1s tng gi tr hin th ra ngoi led n. V c 100ms th c ngt mt ln, do sau 1s ta tng ln mt gi tr th cn 10 ln ngt nh vy, nn ban u ta phi khi to cho bin delay = 10. V y l hm chnh thc hin chc nng ca bi tp 1. timer0_isr bcf INTCON,TMR0IF decfsz delay ; m s ln xy ra ngt bra timer0_isr_1 ; cha , chuyn i incf LATB ; tng PORTB ln 1 movlw .10 ; np li bin m s ln ngt xy ra movwf delay ; 10 x 100 ms = 1s timer0_isr_1 bcf T0CON,TMR0ON movlw HIGH (-50000) ; np li s m 50000 cho timer0 movwf TMR0H movlw LOW (-50000) movwf TMR0L bsf T0CON,TMR0ON ; cho php timer0 m li return

4.2 Chng trnh mu

;================================================== ; Name: timer.asm ; Project: Su dung bo Timer0, cu sau 1s em len 1 on vi roi xuat gia tri ra led don. ; Author: BKIT HARDWARE CLUB ; Homepage: http://www.bkit4u.com/forum ; Creation Date: 8 - 6 - 2009 ;================================================== list p = 18f4520 B mn K Thut My Tnh 39 Thc hnh Vi x l

Trng H. Bch Khoa TP.HCM #include p18f4520.inc code 0 goto main org 0x000008 goto isr_high org 0x000018 goto isr_low ; Vung du lieu udata delay res 1 ; Vung bat dau code PRG code main call init call init_timer0 goto $ ; Ham khoi dong ban dau init clrf PORTB clrf TRISB return

Khoa KH & KTMT

; vector ngat uu tien cao ; vector ngat uu tien thap

; toan bo PORTB la cong xuat

;===========================================; ; Khoi dong Timer0 dem 16 bit. ; De tinh thoi khoan tao ra boi Timer0, ta can biet mot so diem ; 1. Tan so xung clock ngoi: 4Mhz ; 2. Thong so dem truoc Timer0 : 1:2 ; thoi gian tao ra ngat tu Timer0 = 1/((FOSC /4)*2) = 2s ;===========================================; init_timer0 bsf RCON,IPEN ; cho phep uu tien ngat. bcf INTCON2,TMR0IP ; timer0 uu tien thap bcf INTCON,TMR0IF ; xoa co ngat timer0 bsf INTCON,TMR0IE ; cho phep ngat timer0 bsf INTCON,GIEH ; cho phep ngat uu tien cao bsf INTCON,GIEL ; cho phep ngat uu tien thap clrf T0CON ; prescaler 2:1 movlw HIGH (-50000) ; nap so dem 50000 cho timer0 movwf TMR0H movlw LOW (-50000) movwf TMR0L bsf T0CON,TMR0ON ; cho phep timer0 dem return ;===============================================; ; chuong trinh phuc vu ngat quang uu tien cao ;===============================================;

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Trng H. Bch Khoa TP.HCM isr_high ; khong lam gi ca

Khoa KH & KTMT

retfie ;===============================================; ; Chuong trinh phuc vu ngat quang uu tien thap ;===============================================; isr_low call timer0_isr retfie ;===============================================; ; Chuong trinh phuc vu ngat quang Timer0 ;===============================================; timer0_isr bcf INTCON,TMR0IF decfsz delay,1 bra timer0_isr_1 incf LATB movlw .10 movwf delay timer0_isr_1 bcf T0CON,TMR0ON movlw HIGH (-50000) ; nap lai so dem 50000 cho timer0 movwf TMR0H movlw LOW (-50000) movwf TMR0L bsf T0CON,TMR0ON ; cho phep timer0 dem lai return end

4.3 Bi tp
a) Lm li bi th nghim nhng s dng Timer1 thay v Timer0. b) Dng b nh thi to xung vung chu k 10ms, duty cycle 30%. c) Thc hin yu cu 2 ca bi th nghim dng timer iu khin n giao thng.

4.4 Bo co
a) Gii thch ngha cng thc tnh thi gian ca Timer. Nu dng prescaler 16:1 th cn chnh cc thng s no trong bi th nghim thi gian khng i. b) Ti sao phi dng s m m (-50000)? c) Xc nh thi gian chnh xc khi dng ngt thi gian trong bi th nghim.

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Khoa KH & KTMT

Bi 5 :

K thut qut ma trn phm

Ni dung: Kho st cu to, hot ng ca ma trn phm. Tm hiu k thut ly d liu t ma trn phm, chng rung phm nhn. Yu cu: Vit chng trnh ly d liu t phm nhn sau hin th gi tr ca phm nhn ra led n.

5.1 Kt ni mch ma trn phm

ROW1

ROW2

ROW3

ROW4

COL1 COL2 COL4 ROW2 ROW4

COL2 1 3 5 7 9 11

COL3 2 4 6 8 10 12

COL4 COL1 COL3 ROW1 ROW3 VCC

RD1 RD0 RD3 RD2 RD5 RD4 RD7 RD6 RE1 RE0 GNDVCC CON12A

Ma trn phm gm 16 phm nhn kt ni chung 4 hng v 4 ct. Bn ct COL1-COL4 ni vo bn bit thp ca Port D D0-D3. Bn hng ROW1-ROW4 ni vo bn bit cao ca Port D D4-D7. Bn ct c ni vi in tr ko ln m bo mc logic 1 khi phm khng c nhn.

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Connector m rng Port D

5.2 Cc bc hin thc

Bc 1. To project mi tn l Key. Ta c hnh sau:

Bc 2. nh code vo tp tin Key.asm theo dng "Relocatable". Bc 3. Define cc port tng ng vi hng v ct ca ma trn phm d s dng sau ny. Da vo s mch ta nh ngha nh sau: B mn K Thut My Tnh 43 Thc hnh Vi x l

Trng H. Bch Khoa TP.HCM #define #define #define #define #define #define #define #define COLUMN_1 COLUMN_2 COLUMN_3 COLUMN_4 ROW_1 ROW_2 ROW_3 ROW_4 PORTD, 0 PORTD, 1 PORTD, 2 PORTD, 3 PORTD, 4 PORTD, 5 PORTD, 6 PORTD, 7

Khoa KH & KTMT

Bc 4. Khi to input v output cho cc port tng ng. y column l output, cn row l input. Portb dng hin th led n cng c cu hnh l output. INIT_IO ;assigning PORTB is a digital output MOVLW 0x0F MOVWF ADCON1 ; setup portb for outputs CLRF TRISB CLRF PORTB MOVLW 0x0F MOVWF TRISD MOVLW 0xFF MOVWF PORTD RETURN Bc 5. Khi to timer, phn ny chng ta hc t chng 4, ta c th c mt hm khi to timer n gin nh sau: INIT_TIMER0 BSF RCON,IPEN ;enable priority interrupts. BSF INTCON2,TMR0IP BSF INTCON,TMR0IF BSF INTCON,TMR0IE BSF INTCON,GIEH BSF INTCON,GIEL CLRF T0CON MOVLW 0x3c MOVWF TMR0H MOVLW 0xAF MOVWF TMR0L BSF T0CON,TMR0ON RETURN Bc 6. Vit hm Get_key vi 2 i s. i s th nht c tn l temp_wr, chnh l gi tr output tng ng vi cc ct ca ma trn phm, i s th 2 c tn l col chnh l gi tr bt u ca mi ct. V d ct 1 th gi tr bng 0, ct 2 th gi tr bng 1, ct 3 th gi tr bng 2 v ct 4 th gi tr bng 3. GET_KEY BTFSS temp_wr, 0

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Trng H. Bch Khoa TP.HCM BCF BTFSS BSF BTFSS BCF BTFSS BSF BTFSS BCF BTFSS BSF BTFSS BCF BTFSS BSF COLUMN_1 temp_wr, 0 COLUMN_1 temp_wr, 1 COLUMN_2 temp_wr, 1 COLUMN_2 temp_wr, 2 COLUMN_3 temp_wr, 2 COLUMN_3 temp_wr, 3 COLUMN_4 temp_wr, 3 COLUMN_4

Khoa KH & KTMT

BTFSC PORTD,4 ;BIT TEST F, SKIP IF SET GOTO NEXT_BUTTON_1 MOVLW .0 MOVWF KeyReg1 GOTO EXIT_GET_KEY NEXT_BUTTON_1 BTFSC GOTO MOVLW MOVWF GOTO NEXT_BUTTON_2 BTFSC GOTO MOVLW MOVWF GOTO NEXT_BUTTON_3 BTFSC GOTO MOVLW MOVWF PORTD,5 ;BIT TEST F, SKIP IF SET NEXT_BUTTON_2 .4 KeyReg1 EXIT_GET_KEY PORTD,6 ;BIT TEST F, SKIP IF SET NEXT_BUTTON_3 .8 KeyReg1 EXIT_GET_KEY PORTD,7 ;BIT TEST F, SKIP IF SET NEXT_BUTTON_2 .12 KeyReg1

EXIT_GET_KEY MOVFF COL,W ADDWF KeyReg1,d RETURN Bc 7. Da vo hm Get_key trn ta c th hon thin hm Scan_button mt cch d dng. y ta nhc li cch m s l phm nhn d liu ngc tr v l ti

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mt thi im ch cho mt ct c tch cc ( y l mc 0) sau c ngc gi tr t cc hng. Hng 1 tng ng vi ct 1 l s 0, tng t hng 2 vi ct 1 l s 4 Khi nhn phm th s c hin tng rung phm, gii quyt trng hp ny ta c mt cch gii quyt y l c d liu 3 ln lin tip mi ln cch nhau 10ms, sau so snh 3 gi tr c c. Nu 3 gi tr bng nhau th ta xem nh c mt nt nhn c nhn. Trong hm Scan_button ta dng 3 bin KeyReg1, KeyReg2 v KeyReg3 lu gi tr ca 3 ln c d liu lin tip, khi kim tra 3 bin ny c gi tr bng nhau th ta s lu vo bin KeyReg v xut d liu ra PORTB. Scan_button MOVFF KeyReg2,KeyReg3 MOVFF KeyReg1,KeyReg2 MOVLW MOVWF MOVLW MOVWF CALL MOVLW MOVWF MOVLW MOVWF CALL MOVLW MOVWF MOVLW MOVWF CALL MOVLW MOVWF MOVLW MOVWF CALL MOVFF CPFSEQ GOTO CPFSEQ GOTO MOVFF CPFSEQ GOTO 0x0E temp_wr .0 COL GET_KEY 0x0D temp_wr .1 COL GET_KEY 0x0B temp_wr .2 COL GET_KEY 0x07 temp_wr .3 COL GET_KEY KeyReg1,W KeyReg2 EXIT_SCAN_BUTTON KeyReg3 EXIT_SCAN_BUTTON KeyReg,W KeyReg1 Scan_button1

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Trng H. Bch Khoa TP.HCM GOTO Scan_button1 MOVFF CALL EXIT_SCAN_BUTTON KeyReg1,KeyReg Button_process

Khoa KH & KTMT

EXIT_SCAN_BUTTON RETURN Bc 8. Nh gii thut trn ni l c mi 10ms th ta c d liu mt ln, cho iu ny c thc hin d dng th ta phi dng n interrupt timer. Ta khi to mt interrupt timer c sau 10ms th interrupt mt ln. lm c iu ny cc bn c th xem li chng timer c th lm vic mt cch d dng. y ch gii thiu cho cc bn l hm Timer0_routine, hm ny c gi trong interrupt timer v trong hm ny ta gi hm Scan_button trn. TIMER0_ROUTINE BCF BCF MOVLW MOVWF MOVLW MOVWF BSF CALL RETURN INTCON,TMR0IF T0CON,TMR0ON 0x3c TMR0H 0xaf TMR0L T0CON,TMR0ON SCAN_BUTTON

5.3 Bi tp
a) Ci tin hm chng rung phm, khi nhn 1 phm th phi sau 1 thi gian TimeOutForKey th mi tch cc phm nhn . b) Vit ng dng ng h casio n gin (hin th gi, ngy, cho php chnh sa ngy gi) s dng ma trn phm v LCD.

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Bi 6 :

K thut qut LED

Ni dung: Kho st cu to, hot ng ca LED 7 on, LED ma trn. Tm hiu k thut qut LED 7 on v LED ma trn. Yu cu: Vit chng trnh cho php hin th gi tr ra led 7 on v led ma trn.

6.1 Cu to LED 7 on v LED ma trn

LED 7 on gm c 7 on c nh du: a, b, c, d, e, f, g v mt im dp.

LED 7 on c hai loi l Common Anode v Common Cathode, tng ng cc LED ni chung Anode hay ni chung Cathode.
Common Anode Common Cathode

LED ma trn 8x8 hai mu c b tr thnh 8 hng v 8 ct. Mi im c hai LED.

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Cc LED trn cng mt hng ni chung Anode, cc LED cng loi trn cng mt ct ni chung Cathode.

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6.2 Kt ni mch
ENABLE_LED1 3 8 3 LED1 A 7 B 6 C 4 D 2 E 1 F 9 G 10 DOT 5 LED2 A 7 B 6 C 4 D 2 E 1 F 9 G 10 DOT 5 ENABLE_LED2 8 3 LED3 A 7 B 6 C 4 D 2 E 1 F 9 G 10 DOT 5 ENABLE_LED3 8 3 Vcc LED4 A 7 B 6 C 4 D 2 E 1 F 9 G 10 DOT 5 ENABLE_LED4 8

Vcc

Vcc

Vcc

Vcc

Vcc

Vcc

a b c d e f g dot

8.
Green.1

a b c d e f g dot

8.
Green.2 Row.2 Red.2

a b c d e f g dot

8.
Green.4 Row.4 Red.4

a b c d e f g dot

8.

led7

led7 Green.3

led7

led7

Row.1

24 GR1

23 RD1

22 RW1

21 GR2

20 RD2

19 RW2

18 GR3

17 RD3

Row.3

Red.1

Red.3

16 RW3

15 GR4

14 RD4

13 RW4

LED 8x8x2

ML1

RW5

RW6

RW7

1 Green.5

3 Row.5

4 Green.6

6 Row.6

7 Green.7

9 Row.7

10 Green.8

11

12 Row.8

Red.5

Red.6

Red.7

Mch LED m rng gm c 4 LED 7 on v 1 LED ma trn hai mu xanh . Mch c ni vo mt phn ca Port PICtail. D liu c dch ni tip v c ci bi IC 74HC595, TPIC6595. Module SPI ca PIC m nhn vic dch d liu ni tip thng qua chn d liu SDO v chn clock dch SCK. Sau khi dch 4 byte, tn hiu LATCH chuyn t mc 0 ln mc 1 s y d liu ca 4 byte tm ra 4 byte ng ra QA-QH tng ng. Tn hiu CLR_DISP tch cc mc 0 khng cho php hin th.

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Red.8

RW8

GR5

GR6

GR7

GR8

RD5

RD6

RD7

RD8

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Vcc

Trng H. Bch Khoa TP.HCM

U1 SDO LATCH SCK VCC CLR_DISP 3 12 13 8 9 SDI TPIC6595 SDO 18 4 5 6 7 14 15 16 17 330 330 330 330 330 330 330 330 R1 R2 R3 R4 R5 R6 R7 R8 Red.1 Red.2 Red.3 Red.4 Red.5 Red.6 Red.7 Red.8

Khoa KH & KTMT

RCLK DRAIN0 SRCLK DRAIN1 DRAIN2 SRCLR DRAIN3 G DRAIN4 DRAIN5 DRAIN6 DRAIN7

3 LATCH SCK VCC CLR_DISP 12 13 8 9

U2 SDI

TPIC6595 SDO

18 4 5 6 7 14 15 16 17 100 100 100 100 100 100 100 100 R9 R10 R11 R12 R13 R14 R15 R16 Green.1 Green.2 Green.3 Green.4 Green.5 Green.6 Green.7 Green.8

RCLK DRAIN0 SRCLK DRAIN1 DRAIN2 SRCLR DRAIN3 G DRAIN4 DRAIN5 DRAIN6 DRAIN7

SDO SCK

3 LATCH SCK VCC CLR_DISP 12 13 8 9

U3 SDI

TPIC6595 SDO

18 4 5 6 7 14 15 16 17 330 330 330 330 330 330 330 330 R17 R18 R19 R20 R21 R22 R23 R24 A B C D E F G DOT

LATCH CLR_DISP

RCLK DRAIN0 SRCLK DRAIN1 DRAIN2 SRCLR DRAIN3 G DRAIN4 DRAIN5 DRAIN6 DRAIN7

VCC

12 11 10 9 8 7 6 5 4 3 2 1

PICtail RA3 RC5 RC4 RC3 RA0 RA1 RA2 RC0 RC1 RC2 +5V GND CON12

LATCH SCK VCC

14 12 11 10 13

U4 SDI

74HC595 SDO QA QB QC QD QE QF QG QH

9 15 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 10

U3

VCC 18 17 16 15 14 13 12 11 Row.1 Row.2 Row.3 Row.4 Row.5 Row.6 Row.7 Row.8 ENABLE_LED1 ENABLE_LED2 ENABLE_LED3 ENABLE_LED4

RCLK SRCLK CLR G

IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8

V+

OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8

COM UDN2981

6.3 Cc thanh ghi lin quan v cch iu khin

- Thanh ghi trng thi SSPSTAT:

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- Thanh ghi iu khin SSPCON1:

- S khi module Synchronous Serial Port:

Vi s mch trn, mi ln c mt hng LED LED ma trn hay mt con LED 7 on hin th d liu. Li dng hin tng lu nh ca mt, d liu ca mi hng LED ma trn hay mi con LED 7 on c xut ra tun t hng (con) ny n hng (con) khc, chng ta s thy c hnh nh ca c mn hnh ma trn LED hay ca c 4 con LED 7 on. Khi tt c cc hng LED ma trn v tc c cc con LED 7 on c hin th (qut) qua mt ln, ta ni hin th mt frame. mt khng cm thy hnh nh b rung th s ln hin th frame trong mt giy phi ln hn 24 ln (thng l 30 ln). u tin tn hiu CLR_DISP tch cc (mc 0) khng cho LED hin th, sau dch bn byte d liu, tn hiu LATCH chuyn t mc 0 ln mc 1 a d liu mong mun sn sn ng ra, cui cng a tn hiu CLR_DISP ln mc 1 cho php LED hin th d liu mong mun. C nh vy lp li chu trnh ny. B mn K Thut My Tnh 52 Thc hnh Vi x l

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Bn byte d liu c dch ra mi ln c ngha tng ng l d liu ca mt hng LED , d liu ca mt hng LED xanh, d liu ca mt con LED 7 on, iu khin hng (con) LED no hin th. Cch iu khin c minh ha thng qua hnh sau :
RED LED data 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 GREEN LED data 0 1 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7SEG 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Control 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1

RED LED data

GREEN LED data

7SEG

Control

a f 0 0 g e d a f 0 0 g e d a f 0 0 g e d a f 0 0 g e d c p e b f c p e b f c p e b f c p e b f

a b g c d a b g c d a b g c d a b g c d p e f p e f p e f p e f

a b g c d a b g c d a b g c d a b g c d p e f p e f p e f p e f

a b g c d a b g c d a b g c d a b g c d p
0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0

Gi tr ca byte control ch cha nhiu nht mt bit 1. Nh hnh v, cn 12 ln xut d liu (4 byte) cho 1 frame gm c LED ma trn v LED 7 on, 8 ln xut d liu cho 1 frame gm ch c LED ma trn (khng quan tm ni dung hin th LED 7 on), 4 ln

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xut d liu cho 1 frame gm ch c LED 7 on(khng quan tm ni dung hin th LED ma trn).

6.4 Cc bc hin thc.

Bc 1. To project mi ging nh hng dn chng 1 ly tn project l Led v chn chip 18f4520. Ta c hnh sau:

Bc 2. Include file p18f4520.inc vo file Led_matran.asm Bc 3. Khai bo cc buffer cn thit vit driver cho led. V y ta vit driver nn mi ngi khi s dng nhng module ny s khng s dng nhng hm m chng ta vit trong ny ch c th thao tc trn cc buffer m thi. GREEN_SCREEN_BUFFER RES .8 RED_SCREEN_BUFFER RES .8 SEVEN_LED_BUFFER RES .8 COLUMN_BUFFER RES .8 INDEX_OF_BUFFER RED_DATA GREEN_DATA SEVEN_LED_DATA COLUMN_DATA RES RES RES RES RES .1 .1 .1 .1 .1

Bc 4. Ngoi ra nhn vo mch ta c th d dng nhn thy c rng d liu ca chng ta c truyn theo kiu truyn ng b ni tip, chnh xc hn y ngi ta s dng chc nng SPI truyn d liu. Do ta phi cu hnh cho chip lm sao c th hot ng c ch SPI ny. INIT_SPI CLRF SSPCON1 ;SET Fspi = f/4 BSF SSPCON1,5 ;ENALBLE SPI MODE BCF TRISC,5 BCF TRISC,3 RETURN

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Trn y ta mi ch khi to module SPI n c th hot ng nhng nhn li s mch ta li thy c thm vi kt ni na t vi iu khin ra IC74595. IC ny hot ng c th ta cn thm mt chn to clock c th chuyn d liu ni tip ra song song ca IC ny. Ta define thm cho chn Latch ca IC 74595. #define LATCH_DIR TRISA,1 #define LATCH_DATA PORTA,1 ng thi khi to cc PORT lin quan: INIT MOVLW 0x0F MOVWF ADCON1 BCF LATCH_DIR BCF LATCH_DATA CLRF INDEX_OF_BUFFER RETURN Bc 5. Ngoi ra thc hin c bi ny khng th no thiu timer c, v hin th ra led ma trn ta phi qut tng ct led trn ma trn led. Khi nhn vo cu to ca ma trn led ta thy hin th c mt hnh g trn ma trn led th ta phi qut led, v ti mt thi im ch c th hin th mt ct led m thi. Nh vo hin tng lu nh mt m khi qut vi tn s cao th mt ta s thy nh l ct sng ch khng phi chp nhy na. Vy lm sao bit c ta qut led vi tn s bao nhiu l hp l. Nh trong phim nh khi xem phim thc cht ta bit l n ang chy vi tn s l 24 hnh /s. y ta cng gi s nh vy, c mn hnh ca led cng chp nhy vi tn s l 24 hnh/s, m mi hnh ta phi qut 8 ln v c 8 ct. T ta c th suy ra tn s ta cn phi qut cho mi ct l 8x24 ln/s. T y ta c th d dng tnh c timer ca chng ta cn bao nhiu c th qut led c mt cch d dng. INIT_TIMER0 BSF RCON,IPEN ;enable priority interrupts. BSF INTCON2,TMR0IP BSF INTCON,TMR0IF BSF INTCON,TMR0IE BSF INTCON,GIEH BSF INTCON,GIEL CLRF T0CON MOVLW 0x3c MOVWF TMR0H MOVLW 0xAF MOVWF TMR0L BSF T0CON,TMR0ON RETURN Bc 6. Ban u ta khi to cc buffer hin th cng nh qut ct led. d dng trong vic s l ta s khi to cho Column_Buffer cc gi tr tng ng lm sao, khi xut ra n ch tch cc mt ct ca led m thi. y gi s tch cc ti mi ct l tch cc mc cao th ta c th khi to cho Column_buffer cc gi tr sau: 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80.

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Khoa KH & KTMT

Bc 7. n y mi s chun b xong, ta c th bt u vit hm hin th d liu ra led. u tin ta s vit mt macro SPI_transmit vi i s s l gi tr byte s c truyn ni tip ra ngoi. SPI_TRANSMIT MACRO TEMP_DATA ;Has data been received (transmit complete)? BTFSS SSPSTAT, BF GOTO $-2 ;No MOVF TEMP_DATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ENDM Bc 8. Tip theo l lm sao ly d liu t cc buffer a vo cc bin tng ng xut ra led. Ta vit thm mt Macro na gm 2 i s l buffer v temp_data. Macro ny s lm nhim v l ly d liu ti v tr (c lu trong bin index_of_buffer) ca buffer lu vo temp_data. UPDATE_DATA MACRO BUFFER,TEMP_DATA MOVLW HIGH BUFFER MOVWF FSR0H MOVLW LOW BUFFER MOVWF FSR0L MOVFF INDEX_OF_BUFFER,W ADDWF FSR0L,F CLRF W ADDWFC FSR0H MOVFF INDF0,TEMP_DATA ENDM Bc 9. Nh trn gii thiu xut d liu ra led, ngoi vic dng module SPI xut d liu ta cn phi c thm mt tn hiu clock tc ng ln IC74595 th d liu ni tip ca ta mi chuyn qua song song v hin th ra led. Do ta phi vit thm mt hm to clock trn chn define khi ny l Latch_data. CLOCK_STORAGE BSF LATCH_DATA NOP NOP BCF LATCH_DATA NOP NOP BSF LATCH_DATA RETURN Bc 10. Cui cng l hm quan trng nht, hm ny c gi trong timer thc hin vic qut led. DISPLAY CALL INCREASING_INDEX UPDATE_DATA RED_SCREEN_BUFFER,RED_DATA UPDATE_DATA GREEN_SCREEN_BUFFER,GREEN_DATA

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UPDATE_DATA SEVEN_LED_BUFFER,SEVEN_LED_DATA UPDATE_DATA COLUMN_BUFFER,COLUMN_DATA SPI_TRANSMIT RED_DATA SPI_TRANSMIT GREEN_DATA SPI_TRANSMIT SEVEN_LED_DATA SPI_TRANSMIT COLUMN_DATA CALL CLOCK_STORAGE RETURN

6.5 Bi tp
a) Xy dng ng dng cho php s 1234 chy qua cc led 7 on. b) Xy dng ng dng cho php 1 dng ch chy qua led ma trn.

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Khoa KH & KTMT

Bi 7 :

Kho st b truyn nhn ni tip

Ni dung: Kho st cng COM my PC, cc thng s truyn ni tip. Kho st b truyn ni tip ca PIC. Tm hiu cch s dng chng trnh Hyper Terminal truyn nhn ni tip trn my PC. Yu cu: Vit chng trnh giao tip gia my tnh v vi iu khin PIC.

7.1 Cc bc hin thc.

Bc 1. To project mi ging nh hng dn chng 1 ly tn project l Uart v chn chip 18f4520. Ta c hnh sau:

Bc 2. Include file p18f4520.inc vo file uart.asm Bc 3. Khi to PortB l output, PORTC.6 l output, PORTC.7 l input. INIT_PORT CLRF LATB ; Clear PORTB output latches CLRF TRISB ; Config PORTB as all outputs BCF TRISC,6 ; Make RC6 an output B mn K Thut My Tnh 58 Thc hnh Vi x l

Trng H. Bch Khoa TP.HCM BSF RETURN Bc 4. Khi to cc vector ngt org goto Start org goto Start GOTO IntVector RETFIE $ IntVector TRISC,7 00000h 00008h

Khoa KH & KTMT

; Reset Vector ; Interrupt vector

Bc 5. Khi to cho ngt UART, tc 9600baud ti tn s 4Mhz. INIT_UART MOVLW 19h ; 9600 baud @4MHz MOVWF SPBRG BSF Enable transmit BSF baud rate BSF BSF continuous reception BCF Interrupt Flag BSF Interrupt Enable BSF peripheral interrupts BSF interrupts RETURN Bc 6. Vit chng trnh trong ngt thc hin nhim v nhn mt d liu t my tnh truyn xung sau gi li k t cho my tnh nhn li. IntVector btfss PIR1,RCIF ; Did USART cause interrupt? goto ISREnd ; No, some other interrupt movlw 06h ; Mask out unwanted bits andwf RCSTA,W ; Check for errors INTCON,GIE ; Enable global INTCON,PEIE ; Enable PIE1,RCIE ; Set RCIE PIR1,RCIF ; Clear RCIF RCSTA,SPEN ; Enable Serial Port RCSTA,CREN ; Enable TXSTA,BRGH ; Select high TXSTA,TXEN ;

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Trng H. Bch Khoa TP.HCM btfss set? goto movf movwf movwf goto context, return RcvError bcf bsf movlw movwf goto context, return ISREnd retfie RcvError RCREG,W LATB TXREG ISREnd STATUS,Z

Khoa KH & KTMT ; Was either error status bit ; Found error, flag it ; Get input data ; Display on LEDs ; Echo character back ; go to end of ISR, restore

RCSTA,CREN ; Clear receiver status RCSTA,CREN 0FFh ; Light all LEDs PORTB ISREnd ; go to end of ISR, restore

7.2 Chng trnh mu

;=====================================; ; Name: uart.asm ; Project: Vit chng trnh giao tip gia my tnh v vi iu khin PIC. ; Author: BKIT HARDWARE CLUB ; Homepage: http://www.bkit4u.com/forum ; Creation Date: 8 - 8 - 2009 ;======================================; list p=18F4520 ; set processor type include <P18f4520.INC> ;************************************************************ ; Reset and Interrupt Vectors org goto org goto 00000h Start 00008h IntVector ; Interrupt vector ; Reset Vector

;************************************************************ ; Program begins here

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Trng H. Bch Khoa TP.HCM org Start CALL CALL Main goto INIT_PORT clrf clrf outputs bcf bsf RETURN INIT_UART movlw movwf bsf bsf bsf bsf reception bcf bsf bsf interrupts bsf RETURN INIT_PORT INIT_UART 00020h

Khoa KH & KTMT ; Beginning of program EPROM

Main ; loop to self doing nothing LATB ; Clear PORTB output latches TRISB ; Config PORTB as all TRISC,6 ; Make RC6 an output TRISC,7 ; Make RC7 an input

19h ; 9600 baud @4MHz SPBRG TXSTA,TXEN TXSTA,BRGH ; Enable transmit ; Select high baud rate

RCSTA,SPEN ; Enable Serial Port RCSTA,CREN ; Enable continuous PIR1,RCIF ; Clear RCIF Interrupt Flag PIE1,RCIE ; Set RCIE Interrupt Enable INTCON,PEIE ; Enable peripheral INTCON,GIE ; Enable global interrupts

;************************************************************ ; Interrupt Service Routine IntVector btfss interrupt? goto movlw andwf btfss set? ISREnd 06h RCSTA,W STATUS,Z ; No, some other interrupt ; Mask out unwanted bits ; Check for errors ; Was either error status bit PIR1,RCIF ; Did USART cause

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Trng H. Bch Khoa TP.HCM goto movf movwf movwf goto context, return RcvError bcf bsf movlw movwf goto context, return ISREnd retfie end RcvError RCREG,W LATB TXREG ISREnd

Khoa KH & KTMT ; Found error, flag it ; Get input data ; Display on LEDs ; Echo character back ; go to end of ISR, restore

RCSTA,CREN ; Clear receiver status RCSTA,CREN 0FFh ; Light all LEDs PORTB ISREnd ; go to end of ISR, restore

7.3 Bi tp
a) Vit chng trnh trn PC, gi 1 chui string xung board, dng ch ny s chy qua led ma trn hoc LCD. b) Khi nhn 1 phm trn board nhn, s gi 1 chui string ln PC qua cng COM, vit chng trnh trn PC nhn chui string ny v in ra giao din.

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Bi 8 :

Kho st khi chuyn i A-D

Ni dung: Kho st hot ng khi chuyn i A-D. Kho st cc thanh ghi iu khin hot ng khi chuyn i A-D. Yu cu: Vit chng trnh c v hin th gi tr in p thay i bi bin tr.

8.1 Cc bc hin thc

Bc 1. To project mi ging nh hng dn chng 1 ly tn project l a2d v chn chip 18f4520. Ta c hnh sau:

Bc 2. Include file p18f4520.inc vo file a2d.asm Bc 3. Khi to module ADC ta c th s dng mt cch d dng. InitializeAD Movlw B'00000100' ; Make RA0,RA1,RA4 analog inputs movwf ADCON1 movlw B'11000001' ; Select RC osc, AN0 selected, movwf ADCON0 ; A/D enabled movlw 0x01 movwf ADCON2 call SetupDelay ; delay for 15 instruction cycles bsf ADCON0,GO ; Start first A/D conversion return

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khi to c module ADC ta ch cn quan tm ch yu ti cc thanh ghi ADCCON1, ADCCON0, ADCON2. Nh chng trnh khi to trn ta thy u tin phi cu hnh cho cc pin tng ng phi l chn AN0, mc nh ca cc chn ny c chc nng l Input/Output digital. Sau ta phi chn knh ADC tng ng, y ta s dng knh AD0. V mt im quan trng na chnh l bit GO trong thanh ghi ADCON0, khi bt ny c bt ln th module AD mi bt u chuyn i tn hiu. Bc 4. Tip theo l hm c gi tr ADC: Update_adc bsf ADCON0,GO ;start conversion btfsc ADCON0,GO bra $-2 movf ADRESH,W return Sau khi chuyn i tn hiu A-D, gi tr s s c lu vo thanh ghi ADRESH. n y ty vo ng dng c th m ta c th bin i gi tr ny ty theo yu cu m ta mong mun.

8.2 Bi tp
a) Tch hp module LCD, ly gi tr in th t bin tr hin th ln LCD. b) S dng module ADC ca Pic o nhit trong phng, dng LCD hin th gi tr nhit .

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Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

Bi 9 :

Kho st cc khi chc nng c bit khc

Ni dung: Kho st khi chc nng WDT. Kho st khi chc nng PWM . Kho st cc ch hot ng ca vi iu khin. Yu cu: Vit chng trnh s dng chc nng WDT. Vit chng trnh s dng chc nng PWM iu khin sng ca LED. Vit chng trnh s dng chc nng Power control.

9.1 Cc bc hin thc PWM

Bc 1. To project mi ging nh hng dn chng 1 ly tn project l pwm v chn chip 18f4520. Ta c hnh sau:

Bc 2. Include file p18f4520.inc vo file pwm.asm. Bc 3. Tch hp module LCD vo project pwm, tham kho bi tp v LCD. Bc 4. Khi to module PWM ta c th s dng mt cch d dng. Init_pwm ;configure CCP1 module for buzzer bcf TRISC,2 movlw 0x80 movwf PR2 ;initialize PWM period

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Trng H. Bch Khoa TP.HCM movlw cycle movwf bcf bcf CCPR1L CCP1CON,CCP1X CCP1CON,CCP1Y 0x80

Khoa KH & KTMT ;initialize PWM duty

;postscale 1:1, prescaler 4, Timer2 ON movlw 0x05 movwf T2CON movlw 0x0F movwf CCP1CON return

;turn buzzer on

khi to chc nng pwm, u tin ta phi cu hnh cho PORTC2 l output. Tip theo khi to chu k ca PWM thng qua vic cu hnh thanh ghi PR2. Sau ta khi to duty cycle ca xung pwm bng cch cu hnh thanh ghi CCPR1L.

9.2 Chng trnh mu

;=====================================; ; Name: pwm.asm ; Project: Su dung Pwm de xuat am thanh ra loa. ; Author: BKIT HARDWARE CLUB ; Homepage: http://www.bkit4u.com/forum ; Creation Date: 20 - 8 - 2009 ;======================================; list p=18f4520 #include "p18f4520.inc" ; vectors org bra 0x000000 START ; reset vector

;************************************************************ ; program START call Init_pwm goto $ Init_pwm bcf TRISC,2

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Trng H. Bch Khoa TP.HCM movlw movwf period movlw cycle movwf bcf bcf CCPR1L CCP1CON,CCP1X CCP1CON,CCP1Y .125 .249 PR2

Khoa KH & KTMT

;initialize PWM ;initialize PWM duty

;postscale 1:1, prescaler 4, Timer2 ON movlw 0x05 movwf T2CON movlw 0x0F movwf CCP1CON return END

;turn buzzer on

9.3 Bi tp
a) Tm hiu v hin thc chng trnh iu khin RC Servo.

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