1.

2.
3.
4.
5. Cache
6.
7. SOC
8.

()

ADA()

() ()

ABC(Atansoff-Berry Computer)
(John William Mauchly)1946
(John Presper Eckert)ENIAC

19456101
EDVAC
(storedprogram)

ENIAC1981
1988

PC

IntelMicrosoftAppleIBMHP

(Traitorous Eight)

IntelAMDLSI LogicVLSI
TechnologyIntersilAltera Xilinx


(Computer) = (Robot)

PC


2060

2070
Intel Intel

2080
207080
Intel

2090

3D

IT


1.
2.
3.
4.
5. Cache
6.
7. SOC
8.

out = in1 + in2 * in3 + in4 * in5 * in6;

in 1
in 2
in 3

in 4
in 5
in 6

*
+

*
*

out

ISA

IBMSystem/360
ISA(Instruction Set
Architecture)

ISA

ISA

MIPS

ST

Architecture()

Microarchitecture ()
20nm

ARMv7ARM7Cortex
ARMv7 ARM7ARMv4

PCHP 2010PC(personal system group)

40720Intel 2010
436156PC


1.
2.
3.
4.
5. Cache
6.
7. SOC
8.

MIPS

()

x86

x86CISCx86RISC
x86RISC(uops)

x86ARM


1.
2.
3.
4.
5. Cache
6.
7. SOC
8.

ARM73

MIPSARM9
x86

TI C6000 DSP

Port 0

Port 1

Port 2

Port 3


Superscalar

VLIW

SuperscalarVLIW

X3
op

X2
op

X1
op

X0
op

Y3

Y2

Y1

Y0

X op Y

X3 op Y3

X2 op Y2

X1 op Y1

X0 op Y0


Unused
Thread 1
Thread 2
Thread 3
Thread 4
Thread 5

Execution Time

FU1 FU2 FU3 FU4


1.
2.
3.
4.
5. Cache
6.
7. SOC
8.

CPU

Cache

Cache

(DRAM)SRAM

Cache

Cache

Cache

Cache
Core0
L1P

Core1
L1D

L1P

L2

L1D
L2

L3

Cache
Cache line 0

valid

tag

block

Cache line 1

valid

tag

block

Cache line 2

valid

tag

block

Cache line 3

valid

tag

block

Cache

Cache

Cache

CacheDMA

DMA


1.
2.
3.
4.
5. Cache
6.
7. SOC
8.


1.
2.
3.
4.
5.

4864

1+2+3++100 = ?


1.
2.
3.
4.
5. Cache
6.
7. SOC
8.

SOC


1.
2.
3.
4.
5. Cache
6.
7. SOC
8.

Jack Kilby
TI 7Jack Kilby
Jack Kilby


photoshop

FreescaleDSP
logo
logo
DSP


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etails/6744967

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