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Code: 9D06103a M.Tech - I Semester Supplementary Examinations November 2012

ADVANCED COMPUTER ARCHITECTURE

(Common to DSCE, DECS & ES) Time: 3 hours
Answer any FIVE questions All questions carry equal marks ***** 1. (a) Explain briefly about CPU performance equation. (b) What are the four implementation technologies you come across? Briefly explain. 2. (a) Explain briefly about addressing modes of control flow instruction. (b) Explain the term: (i) Encoding an instruction set. (ii) Reduced code size.

Max. Marks: 60

3. (a) What is meant by instruction level parallism? Explain data dependences and hazards. (b) Explain the importance of dynamic scheduling and how data hazards are overcome. 4. (a) What is UIIW approach? Explain. (b) Explain briefly about detecting and exhausting loop level parallism.

5. (a) What is cache memory and how do you improve cache performance? (b) Briefly explain the strategies adopted in the second miss penalty reduction technique and explain what is meant by write merging. 6. (a) Explain the Flynn method of catering computers. (b) Explain the importance of shared memory concept and distributed shared memory architecture. 7. (a) Explain the different types of storage devices you come across. (b) Explain briefly about block interleaved panity and distributed block interleaved panity 8. (a) Why do you prefer fibre optics transmission of data? Explain the different component used in the network media. (b) What is cluster? Explain the dependability and scalability advantages of clusters.

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