Microprocessors, Semester 2 2011-2012 Midterm Exam (Kim tra gia k) Duration: 90 minutes (90 pht) Open book exam

( thi m)
Questions:

H v Tn

Nhm im

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Answers: a.ADDC.W #0,dst b.SUB.W #1,dst c.SUB.W #2,dst d.ADD.W #1,dst e.ADD.W) #2,dst f.XOR.B #0FFh,dst g.ADD.W dst,dst h.ADDC.B dst,dst i.MOV.W #0,dst j.MOV #0,R3 k.MOV @SP+,PC

Bi 1. (1 im) Assembler s thay th cc gi lnh sau y bng cc lnh thc s no ca MSP430?

(What native MSP430 instruction is replaced by the assembler for each of the following emulated instruction?)

a. b. c. d. e. f. g. h. i. j. k.

ADC.W dst DEC dst DECD dst INC dst INCD dst INV.B dst RLA.W dst RLC.B dst CLR dst NOP RET

Bi 2. (1 im) Mt chng trnh cha 2 lnh sau y. Sau khi c dch v np vo b nh, hy cho bit gi tr tai cc v tr nh 0x800a v 0x800c. Ghi kt qu c hai h nh phn v hexa.
(An assembly language program contains the following two instructions. After assembly is completed, what is in memory locations 0x800a and 0x800c? (Give your answer in hexadecimal with 0x and in binary.)

0x800a:5404 (0101 0100 0000 0100) 0x800c:23FE (0010 0011 1111 1110)

label:

org 0x800a rla.w r4 jne label

Bi 3. (1 im) Cc hot ng sau y ln lt c thc hin i vi stack ca MSP430: PUSH A, PUSH B, POP, PUSH C, PUSH D, POP, PUSH E, PUSH F, POP, POP, POP, PUSH F
a. b. c.

a. b. c.

A,F Sau khi PUSH F ln th nht gm A,C,E,F A,F,M

Sau lnh PUSH F cui cng, stack cha nhng phn t no? Lc no stack cha nhiu phn t nht? Tip tc thc hin ln lt cc hot ng sau, stack s cha cc phn t no?

PUSH G, PUSH H, PUSH I, PUSH J, POP, PUSH K, POP, POP, POP, PUSH L, POP, POP, PUSH M Bi 4. (1 im) Mi mt lnh sau y c thc hin trong bao nhiu chu k? (How many cycles are used by each of the following instructions:) a. mov.w r5,r6 b. mov.b r5,r6 c. add.b @r5,r6 d. add.b 10(r5),r6 e. sub.w 10(r5),20(r6) f. mov.w #1,r5 g. mov.w #100,r5 h. jmp label i. jne label
a. 1 b. 1 c. 2 d. 3 e. 6 f. 1 g. 2 h. 2 i. 2

Bi 5. (1 im) Xt 1 on chng trnh ngun Assembly c s dng cc directive sau y. Cho bit ni dung ca vng nh lin quan c khi to bi cc directive ny. MSP430 c kin trc little-endian. Hy ghi cc gi tr vo bng bn phi.
(Consider the following assembly directives (see below). Show the content of relevant region of memory initialized by these directives. MSP430 is a little-endian architecture. Fill in the table.) ORG 0xF000 b1: DB 5 b2: DB -122 b3: DB 10110111b b4: DB 0xA0 EVEN tf EQU 25 w1: DW 32330 w2: DW -32000 s1: DB 'ABCD'

Label b1 b2 B3 B4 W1 W2 S1

Address [hex] 0xF000 0xF001 0xF002 0xF003 0xF004 0xF005 0xF006 0xF007 0xF008 0xF009 0xF00A 0xF00B

Memory[7:0] [hex] 0x05 0x86 0xB7 0xA0 0x4A 0x7E 0x00 0x83 0x41 0x42 0x43 0x44

Bi 6. (2 im) Xt cc lnh bng bn phi. Vi tng lnh hy xc nh vic thay i gi tr ca cc thanh ghi v cc c V, N, Z, C sau khi lnh c thc hin v ghi vo cc trng trong bng. Gi tr ban u ca cc thanh ghi ln lt l: R2=0x0007, R5=0xAA55, R7=0x1357. Gi s rng cc iu kin u ny l nh nhau vi tng lnh.
(Consider the following instructions given in the table below. For each instruction determine changes in registers after its execution. Fill in the empty cells in the table. Initial value of registers R2, R5, and R7 is as follows: R2=0x0007, R5=0xAA55, R7=0x1357. Assume the starting conditions are the same for each question (i.e., always start from the initial conditions in registers).)

Instruction ADD.B R5, R7 ADD R5, R7 ADDC R5, R7 SUB.B R5, R7 SUBC R5, R7 CMP.B R5, R7 CMP R5, R7 BIT R5, R7 BIC R5, R7 BIS R5, R7 AND R5, R7 XOR.B R5, R7 SWB R7 (SWPB) RRC.B R7 RRC R7 RRA.B R7 RRA R7

R7=0x???? 0x00AC 0xBDAC 0xBDAD 0x0002 0x6902 0x1357 0x1357 0x1357 0x1102 0xBB57 0x0255 0x0002 0x5713 0x00AB 0x89AB 0x002B 0x09AB

V 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0

N 1 1 1 0 0 0 0 0 1 1 0 0 1 1 1 0 0

Z 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0

C 0 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1

Bi 7. (1 im) Cho cc s hexa 16-bit ct th hai. Tng s c th c coi l mt s nh phn khng du hoc c du 16-bit (s b 2). Cho bit gi tr thp phn ca chng bng cch ghi kt qu vo cc ct tng ng v ghi vn tt qu trnh tnh nh cch lm bn di vi trng hp (a). Consider the following 16-bit hexadecimal numbers (second column). Each of these values can be interpreted as an unsigned 16-bit integer or a signed 16-bit integer represented in 2s complement. Provide the decimal value for each number and interpretation. Show your work as illustrated in (a). 16-bit hexadecimal A223 81C2 9689 A2EB 39CD Unsigned int (S khng du) 41507 33218 38537 41707 14797 Signed int (S c du) -24029 -32318 -26999 -23829 14797

(a) (b) (c) (d) (e)

(a) Unsigned (khng du): A22316 = 10*163 + 2*162 + 2*161 + 3*160 = 4150710 Signed (c du): A22316 = 1010.0010.0010.00112 => this is a negative number (y l mt s m); Its 2s complement is: 0101.1101.1101.1101 = 5DDD16 = 5*163 + 13*162 + 13*161 + 13*160 = 2402910 => A22316 = -2402910 (b)unsigned: 81C2h = 8*16^3 + 1*16^2 + 12*16 + 1 Signed: 81C2h = 1000 0001 1100 0010 b => s m 2s complement: 0111 1110 0011 1110 = 7E3Eh = 7*16^3 + 14*16^2 + 3*16 + 14 = 32318 => -32318 (c)

(d)

(e)

Bi 8. (1 im) Thc hin cc php ton s hc sau y vi cc ton hng l s c du. Cho bit kt qu h thp phn v gi tr ca cc c C,V,N v Z. Ghi vn tt qu trnh thc hin bn cnh tng t nh cu a. Consider the following arithmetic operations. Find the results in decimal and set the flags C, V, N, and Z accordingly. (a) 8-bit, twos complement 5510 = 00111111 5510 + 10510 10510 = 01101001 Kt qu: -8810 10101000 = -8810 C=0 V=1 N=1 Z=0

(b) 8-bit, twos complement -55 = 11001001 (-55)10 - 6810 -68 = 10111100 Kt qua -123 1000 0101 = -123 C=1V=0N=1Z=0

(c) 16-bit, twos complement FFBB = 1111 1111 1011 1011 FFBB16 008816 0088 = 0000 0000 1000 1000 Kt qua -205 FF33 = 1111 1111 0011 0011 C=1V=0N=1Z=0

(d) 16-bit, twos complement FF5116 + 3410 Kt qua -141 C=0V=0N=1Z=0

(e) 16-bit, twos complement 00AF16 + 9910 Kt qua 274 C=0V=0N=0Z=0

Bi 9. (1 im) Xt cc lnh trong bng di y. Vi tng lnh hy xc nh di ca n (tnh bng word), cc t lnh vit h hexa, mode a ch ca ton hng ngun v gi tr ca thanh ghi R7 sau khi lnh c thc hin ghi vo cc trng trong bng. Ni dung ban u ca b nh c cho bng di .Gi tr ban u ca cc thanh ghi ln lt l: R5=0xF000, R6=0xF008, R7=0xFFFF. Gi s rng iu kin ban u l nh nhau i vi cc lnh.
(Consider the following instructions given in the table below. For each instruction determine its length (in words), the instruction words (in hexadecimal), source operand addressing mode, and the content of register R7 after execution of each instruction. Fill in the empty cells in the table. The initial content of memory is given below. Initial value of registers R5, R6, and R7 is as follows: R5=0xF000, R6=0xF008, R7=0xFFFF. Assume the starting conditions are the same for each question (i.e., always start from initial conditions in memory) and given register values.) Instr. Address (i) (ii) (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) Label 0x1116 0x1116 0x1116 0x1116 0x1116 0x1116 0x1116 0x1116 0x1116 0x1116 0x1116 0x1116 Instruction MOV R5, R7 MOV.B R5, R7 MOV 4(R5), R7 MOV.B 3(R5), R7 MOV.B -3(R6), R7 MOV TONI, R7 MOV.B EDE, R7 MOV &EDE, R7 MOV.B @R5, R7 MOV @R5+, R7 MOV #45, R7 MOV.B #45, R7 Instr. Length [words] 1 1 2 2 2 2 2 2 1 1 2 2 Instruction Word(s) [hex] 0x4507 0x4447 0x4517 0004 0x4557 0003 0x4657 FFFD 0x4017 DEEC 0x4057 DEF4 0x4217 F00C 0x4567 0x4537 0x4037 002D 0x4077 002D Source Operand Addressing Mode Register Register Index Index Index Symbolic Symbolic Absolute Indirect Indirect auto Immediate Immediate R7=? [hex] 0xF000 0x0000 0x0203 0x00FF 0x0002 0x0203 0x00DA 0xCDDA 0x0004 0x0504 0x002D 0x002D

Address [hex] 0xF000 0xF002 TONI 0xF004 0xF006 0xF008 0xF00A EDE 0xF00C 0xF00E Tnh ton nhp ti y:

Memory[15:0] [hex] 0x0504 0xFFEE 0x0203 0x3304 0xF014 0x2244 0xCDDA 0xEFDD

Ht (The end)