R.M.D.

ENGINEERING COLLEGE
R.S.M. NAGAR, KAVARAIPETTAI 601 206.

B.E. B.TECH DEGREE MODEL EXAMINATION FIFTH SEMESTER ELECTRICAL AND ELECTRONICS ENGINEERING EC1312 DIGITAL LOGIC CIRCUITS Duration: 3 Hours ANSWER ALL THE QUESTIONS PART A (10 X 2 = 20) 1. Convert (53)10 to EX-3 code. 2. What is gray code? What are its applications? 3. What is a priority encoder? 4. Expand the function f (A, B, C) =A +BC to standard SOP form? 5. How many FFs are required to design a mod-7 up down counter? 6. Difference between Moore & mealy type sequential circuits. 7. What is race around condition? 8. What is meant by state assignment? 9. What are the difference between PLA and PAL? 10. What is the advantage of schottky TTL family? PART B (5 X 16 = 80) 11. a) Obtain the minimum sop using QUINE - McCLUSKY method and verify using K-map F=m0+m2+m4+m8+m9+m10+m11+m12+m13. (OR) 11. b) Reduce the Boolean function using k-map technique and implement using gates, f (w, x, y,z)= m (0,1,4,8,9,10) which has the dont cares d (w, x, y, z)= m (2,11). 12. a) i) Design a 2-bit magnitude comparator? a) ii) Using 8 to 1mux, realize the Boolean function, T = F(w, x, y, z) =m (0,1,2,4,5,7,8,9,12,13) (OR) 12. b) Design a 4-bit adder /subtractor-using logic gates and explains its operation. 13. a) i) Summarize the design procedure for synchronous sequential circuit. a) ii) Realize D and T flip flops using JK flip flops. (OR) Max. Marks: 100

13. b) A sequential circuit has two D Flipflops A and B an input x and output y is specified by the following next state and output equations. A (t+1) = Ax + Bx; B (t+1 ) = Ax; Y = (A+B) x (i) Draw the logic diagram of the circuit. (ii) Derive the state table. (iii) Derive the state diagram. 14. a) Minimize the following state table.

(OR) 14. b) Design an Asynchronous 4 bit up-down counter. 15. a) i) Discuss on the concept of working and applications of ROM, EPROM and PLA. a) ii) A combinational circuit is defined by the functions. F1 (a, b, c) = (3, 5, 6, 7) and F2 (a, b, c) = (0, 2, 4, 7) implement the circuit with a PLA. (OR) 15. b) Explain the characteristics and implementation of the following digital logic families. (i) TTL (ii) CMOS