To solve setup violation 1. optimizing/restructuring combination logic between the flops. 2.

Tweak flops to offer lesser setup delay [DFFX1 -> DFFXx] 3. Tweak launch-flop to have better slew at the clock pin, this will make CK->Q of launch flop to be fast there by helping fixing setup violations 4. Play with skew [ tweak clock network delay, slow-down clock to capturing flop and fasten the clock to launch-flop](otherwise called as Useful-s kews) To solve Hold Violations 1. Adding delay/buffer[as buffer offers lesser delay, we go for spl Delay cells whose functionality Y=A, but with more delay] 2. Making the launch flop clock reaching delayed 3. Also, one can add lockup-latches [in cases where the hold time requirement is very huge, basically to avoid data slip] 3. What is antenna Violation & ways to prevent it During the process of plasma etching, charges accumulate along the metal strips. The longer the strips are, the more charges are accumulated. IF a small transis tor gate connected to these long metal strips, the gate oxide can be destroyed ( large electric field over a very thin electric) , This is called as Antenna viol ation. The ways to prevent is , by making jogging the metal line, which is atleast one metal above the layer to be protected. If we want to remove antenna violation in metal2 then need to jog it in metal3 not in metal1. The reason being while we a re etching metal2, metal3 layer is not laid out. So the two pieces of metal2 got disconnected. Only the piece of metal connected to gate hav e charge to gate. When we laydown metal3, the remaining portion of metal got cha rge added to metal3. This is called accumulative antenna effect. Another way of preventing is adding reverse Diodes at the4. We have multiple ins tances in RTL(Register Transfer Language), do you do anything special during syn thesis stage? 4. We have multiple instances in RTL(Register Transfer Language), do you do anyt hing special during synthesis stage? While writing RTL(Register Transfer language),say in verilog or in VHDL language , we dont write the same module functionality again and again, we use a concept called as instantiation, where in as per the language, the instanciation of a mo dule will behave like the parent module in terms of functionality, where during synthesis stage we need the full code so that the synthesis tool can study the l ogic , structure and map it to the library cells, so we use a command in synthes is , called as "UNIQUIFY" which will replace the instantiations with the real lo gic, because once we are in a synthesis stages we have to visualize as real cell s and no more modelling just for functionality alone, we need to visualize in-te rms of physical world as well. 5. what is tie-high and tie-low cells and where it is used Tie-high and Tie-Low cells are used to connect the gate of the transistor to eit

her power or ground. In deep sub micron processes, if the gate is connected to p ower/ground the transistor might be turned on/off due to power or ground bounce. The suggestion from foundry is to use tie cells for this purpose. These cells a re part of standard-cell library. The cells which require Vdd, comes and connect to Tie high...(so tie high is a power supply cell)...while the cells which want s Vss connects itself to Tie-low. 6. what is the difference between latches and flip-flops based designs Latches are level-sensitive and flip-flops are edge sensitive. latch based desig n and flop based design is that latch allowes time borrowing which a tradition f lop does not. That makes latch based design more efficient. But at the same time , latch based design is more complicated and has more issues in min timing (races). Its STA with time borrowing in deep pipelining can be quite complex. gates 7. What is High-Vt and Low-Vt cells. Hvt cells are MOS devices with less leakage due to high Vt but they have higher delay than low VT, where as the low Vt cells are devices which have less delay b ut leakage is high. The thereshold(t) vloltage dictates the transistor switching speed , it matters how much minimum threshold voltage applied can make the tran sistor switching to active state which results to how fast we can switch the tra sistor. disadvantage is it needs to maintain the transistor in a minimum subthre shold voltage level to make ir switch fast so it leads to leakage of current int urn loss of power. 8. What is LEF mean? LEF is an ASCII data format from Cadence Design inc, to describe a standard cell library. It includes the design rules for routing and the Abstract layout of th e cells. LEF file contains the following, Technology: layer, design rules, via-definitions, metal-capacitance Site : Site extension Macros : cell descriptions, cell dimensions, layout of pins and blockages, capac itances To get further insight to the topic, please check this http://www.csee.umbc.edu/ ~cpatel2/links/414/slides/lect03_LEF.pdf 9. what is DEF mean? DEF is an ASCII data format from Cadence Design inc., to describe Design related information. 10. Steps involved in designing an optimal padring 1. Make sure you have corner-pads, across all the corners of the padring, This i s mainly to have the power-continuity as well as the resistance is less . 2. Ensure that the Padring ful-fills the ESD requirement, Identifyh the power-do mains, split the domains, Ensure common ground across all the domains. 3. Ensure the padring has ful-filled the SSN(Simultaneous Switching Noise) requi rement.

4. Placing Transfer-cell Pads in the cross power-domains, for different height p ads, to have rail connectivity. 5. Ensure that the design has sufficient core power-pads. 6. Choose the Drive-strenght of the pads based on the current requirements, timi ng. 7. Ensure that there is seperate analog ground and power pads. 8. A No-Connection Pad is used to fill out the pad-frame if there is no requirem ent for I/O's.Extra VDD/GND pads also could be used. Ensure that no Input/output pads are used with un-connected inputs, as they consume power if the inputs flo at. 9. Ensure that oscillator-pads are used for clock inputs. 10. In-case if the design requirement for source synchronous circuits, make sure that the clock and data pads are of same drive-strength. 11. Breaker-pads are used to break the power-ring, and to isolate the power-stru cture across the pads. 12. Ensure that the metal-wire connected to the pin can carry sufficient amount of the current, check if more than one metal-layer is necessary to carry the max imum current provided at the pin. 13. In case if required , place pads with capacitance.

11. What is metastability and steps to prevent it. Metastability is an unknown state it is neither Zero nor One.Metastability happe ns for the design systems violating setup or hole time requirements. Setup time is a requirement , that the data has to be stable before the clock-edge and hold time is a requirement , that the data has to be stable after the clock-edge. Th e potential violation of the setup and hold violation can happen when the data i s purely asynchronous and clocked synchronously. Steps to prevent Metastability. 1. Using proper synchronizers(two-stage or three stage), as soon as the data is coming from the asynchronous domain. Using Synchronizers, recovers from the meta stable event. 2. Use synchronizers between cross-clocking domains to reduce the possibility fr om metastability. 3. Using Faster flip-flops (which has narrower Metastable Window). 12. what is local-skew, global-skew,useful-skew mean? Local skew : The difference between the clock reaching at the launching flop vs the clock reaching the destination flip-flop of a timing-path. Global skew : The difference between the earliest reaching flip-flop and latest reaching flip-flop for a same clock-domain. Useful skew: Useful skew is a concept of delaying the capturing flip-flop clock

path, this approach helps in meeting setup requirement with in the launch and ca pture timing path. But the hold-requirement has to be met for the design.

13. What are the various timing-paths which i should take care in my STA runs? 1. Timing path starting from an input-port and ending at the output port(purely combinational path). 2. Timing path starting from an input-port and ending at the register. 3. Timing path starting from an Register and ending at the output-port. 4. Timing path starting from an register and ending at the register.

15. What are the various yield-losses in the design? The yield loss in the design is characterized by 1. Functional yield losses, mainly caused by spot defects , especially (shorts & opens) 2. Parametric yield losses, due to process variations. 16. what is meant by virtual clock definition and why do i need it? Virtual clock is mainly used to model the I/O timing specification. Based on wha t clock the output/input pads are passing the data. For Further Understanding of the concept. http://www.vlsichipdesign.com/images/v irtual_clock.jpg 18. What are the various Design constraints used while performing Synthesis for a design? 1. Create the clocks (frequency, duty-cycle). 2. Define the transition-time requirements for the input-ports.3 3. Specify the load values for the output ports 4. For the inputs and the output specify the delay values(input delay and ouput delay), which are already consumed by the neighbour chip. 5. Specify the case-setting (in case of a mux) to report the timing to a specifi c paths. 6. Specify the false-paths in the design 7. Specify the multi-cycle paths in the design. 8. Specify the clock-uncertainity values(w.r.t jitter and the margin values for setup/hold).

19. Specify few verilog constructs which are not supported by the synthesis tool . initial, delays, real, force and release, fork join. 24. what is body effect? Increase in Vt(threshold voltage) , due to increase in Vs(voltage at source), is called as body effect.

25. What is latchup in CMOS design and ways to prevent it? To best understand the concept behind the latchup, we need to understand the con cept behind SCR(Silicon Controlled Rectifiers), and how to model the basic trans istor in an SCR structure and on what conditions SCR structures are created in t he CMOS design process and its effects and what are the ways used to prevent it in the design-phase.An SCR is an acronym for Silicon Controlled Rectifier. It wo rks similar to a typical diode, but is controlled similar to a bipolar transisto r as far as connections go. Connection points are Anode [A], Cathode [K], and Ga te [G]. The SCR is made up of two "P-N" junctions with a "Gate" attachment betwe en them. The gate is connected between the two P-N junctions with a current wait ing in the forward bias direction [+ to -] and the voltage is above 1-volt. A mo mentary pulse to the gate will cause the SCR to conduct and current will flow ac ross the device until the value changes. 25. What are the various design changes you do to meet design power targets? # Design with Multi-VDD designs, Areas which requires high performance, goes wit h high VDD and areas which needs low-performance are working with low Vdd's, by creating Voltage-islands and making sure that appropriate level-shifters are pla ced in the cross-voltage domains # Designing with Multi-Vt's(threshold voltages), areas which require high perfor mance, goes with low Vt, but takes lot of leakage current, and areas which requi re low performance with high Vt cells, which has low leakage numbers, by incorpo rating this design process, we can reduce the leakage power. # As in the design , clocks consume more amount of power, placing optimal clockgating cells, in the design and controlling them by the module enable's gives a lot of power-savings. # As clock-tree's always switch making sure that most number of clock-buffers ar e after the clock-gating cells, this reduces the switching there by power-reduct ion. # Incorporating Dynamic Voltage & Frequency scaling (DVFS) concepts based on the application , there by reducing the systems voltage and frequency numbers when the application does not require to meet the performance targets. # Ensure the design with IR-Drop analysis and ground-bounce analysis, is with-in the design specification requirement. # Place power-switches, so that the leakage power can be reduced. related information. 27. what is meant by Library Characterizing: "Chip designing is all about Modeli ng the silicon", and how well we characterize the silicon, is all the game. So i nitially let us assume our process technology is say "32nm", for example: Now we need to develop a test-chip, having modules (digital & analog), and study our s ilicon timings. Now the toughest job is to generate library views(formats specif

ic to each tool understandable formats).There is a bit of timing in accuracy pos sible in the views across the formats. 28. what is meant by wireload model: In the synthesis tool, in order to model the wires we use a concept called as "W ireload models", Now the question is what is wireload models: Wireload models ar e statistical based on models with respect to fanout. say for a particular techn ology based on our previous chip experience we have a rough estimate we know if a wire goes for "n" number of fanin then we estimate its delay as say "x" delay units. So a model file is created with the fanout numbers and corresponding esti mated delay values. This file is used while performing Synthesis to estimate the delay for Wires, and to estimate the delay for cells, technology specific libra ry model files will be available 29. what are the measures to be taken to design for optimized area As silicon real-estate is very costly and saving is directly propotional to the company's revenue generation lot of emphasize is to design which has optimial ut ilization in the area-front. The steps to reduce area are * If the path is not timing-critical, then optimize the cells to use the low -drive strength cells so that there will saving in the area. * Abut the VDD rows * Analyzing the utilization numbers with multiple floor-planning versions wh ich brings up with optimized area targets. 30. what all will you be thinking while performing floorplan * Study the data-flow graph of the design and place the blocks accordingly, to reducing the weighted sum of area, wire-length. * Minimize the usuage of blocks other-than square shapes, having notches * Place the blocks based on accessibility/connectivity, thereby reducing wir e-length. * Abut the memory, if the pins are one-sided, there-by area could be reduced . * If the memory communicates to the outside world more frequently , then pla cing at the boundary makes much of a sense. * Study the number of pins to be routed, with the minimum metal width allowe d , estimate the routability issues. * Study the architecture and application , so that the blocks which will be enabled should be scattered, to reduce the power-ground noise. 31. what are the measures in the Design taken for Meeting Signal-integrity targe ts As more and more devices are getting packed, results in more congested areas, an d coupling capactiances dominating the wire-capacitance, creates SI violations. Let's see now by what are all the measures we can reduce/solve it. * As clock-tree runs across the whole chip, optimizing the design for SI, is essential route the clock with double-pitch and triple spacing. * In-case of SI violation, spacing the signal nets reduces cross-talk impact s. * Shield the nets with power-nets for high frequency signal nets to prevent from SI. * Enable SI aware routing , so that the tool takes care for SI * Ensure SI enabled STA runs, and guarantee the design meeting the SI requir ements

* Route signals on different layers orthogonal to each other * Minimize the parallel run-length wires, by inserting buffers. 32. what are the measures taken in the Design achieving better Yield Better yield could be achieved by reducing the possibility of manufacturability flaws. Guaranting the circuit performance, by reducing parametric yield, with pr ocess variations playing a major role is a big-challenge. * Create more powerful stringent runset files with pessimistic spacing/short rules. * Check for the areas where the design is prone to lithographic issues, like sharp cuts and try to re-route it. * For via-reliability issues, use redundant vias, to reduce the chances for via-breakage. * In order to design for yield-enhancement , design systems, which could hav e optimal redundancy, like repairable memories. * Optimal placing of de-coupling capacitances, reduces the power-surges. * Doubling the width of the non-critical nets, clock-nets can increase the y ield parameter. * Ensure that the poly-orientation are maintained.

32. what are the measures or precautions to be taken in the Design when the chip has both analog and digital portions Designing for Optimal integration of Analog and Digital * As today's IC has analog components also inbuilt , some design practices a re required for optimal integration. * Ensure in the floorplanning stage that the analog block and the digital bl ock are not siting close-by, to reduce the noise. * Ensure that there exists seperate ground for digital and analog ground to reduce the noise. * Place appropriate guard-rings around the analog-macro's. * Incorporating in-built DAC-ADC converters, allows us to test the analog po rtion using digital testers in an analog loop-back fashion. * Perform techniques like clock-dithering for the digital portion. 33. what are the steps incorporated for Engineering Change Order[ECO] As more and more complex the IC design is , and with lot of first time applicati on , is more prone to last minute changes, there should be provision in the design-flow to accomodate the functional and timing bugs. The step to perform this called as Engineering c hange order(ECO). * Ensure that the design has spare functional gates well distributed across the layout. * Ensure that the selection the spare gates, has many flavours of gates and universal gates, so that any functionality could be achieved. 34. what are the steps performed to achieve Lithography friendly Design Designing for Manufacturability requires validating the design full-filling lith ography rules * Checking the layout confirming the design rules (spacing,trace-width,short s).

* Check for the less-congested areas and increasing the spacing of the nets. 35. what does synthesis mean Synthesis is a step of mapping the RTL files (verilog format or vhdl format) to convert it to the technology specific cells.. 36. what are the pre-requisties to perform synthesis 1. RTL files 2. Synopsys constraints file, Design constraints file, explaining the priorities of cost functions like area/timing/power 3. Technology specific library files. 35. What are the various ways to reduce Clock Insertion Delay in the Design 1. Number of Clock sinks 2. Balancing two different clock frequencies 3. Placement of clock sinks. 4. Placement of Clock gating cells 5. Clock tree buffers/inverters drive strength's 6. Clock Transition 7. placement of Clockgating cells and the clock sinks 8. Combinationals cells in the path of clocks (say clock dividers, muxes, clockg ates) ... 36. what are the various functional verification methodologies * TLM(Transaction Level Modelling) * Linting * RTL Simulation ( Enivronment involving : stimulus generators, monitors, re sponse checkers, transactors) * Gate level Simulation * Mixed-signal simulations * Regression 36. What does formal verification mean? Formal verification uses Mathematical techniquest by prooving the design through assertions or properties. Correctness of the design can be achieved through ass ertions with out the necessity for simulations. The methods of formal verificati on are 1. Equivalence checking In this method of checking the designs are compared base d on mathematical equations and compared whether they are equal or not . Original RTL vs Modified RTL RTL vs Netlist Golden Netlist vs Modified/Edited Netlist Synthesis Netlist vs Place and route Netlist Remember : Formal verification doesnt check for functionality of the RTL c ode. It will be only checking the equivalence. 2. Model checking Property specification languages like PSL or SVA, are fo rmally analyzed to see if they are always true for a design. This can exhaustive ly prove if a property is correct, but does tend to suffer from state-space expl osion: the time to analyse a design is directly propotional to the amount of sta tes. * * * *

42. assume you have defined latency specified by user both in Master clock and i n the Generated clock in STA, how the tool will behave any idea? If we have defined only Master latency and Generated clock with latency numbers, and the clocks are set to propagated mode after clock-tree, then the Static Tim ing Analysis Tool, will honour the Generated clock source and Generated clock ne twork latency numbers only and the master clock source and master clock network latencies are ignored. 43. Assume there is a specific requirement to preserve the logic during synthesi s, how will do it. If there is a requirement that some logic needs to be preserved then we can use a command called set_dont_touch or set_dont_design (complete module) and convey the message to the tool not to optimize or smash the logic.

44. We have multiple instances in RTL(Register Transfer Language), do you do any thing special during synthesis stage? While writing RTL(Register Transfer language),say in verilog or in VHDL language , we dont write the same module functionality again and again, we use a concept called as instantiation, where in as per the language, the instanciation of a mo dule will behave like the parent module in terms of functionality, where during synthesis stage we need the full code so that the synthesis tool can study the l ogic , structure and map it to the library cells, so we use a command in synthes is , called as "UNIQUIFY" which will replace the instantiations with the real lo gic, because once we are in a synthesis stages we have to visualize as real cell s and no more modelling just for functionality alone, we need to visualize in-te rms of physical world as well. 45. what do you call an event and when do you call an assertion? Assertion based Verification Tools, checks whether a statement holds a defined p roperty or not, whereas, Event based Simulators, checks whether there is change in any event, say for every edge of a clock whether there is some activity in a signal or not, in case of an asynchronous designs, checks whether a signal is en abled or not.

1) Why are PMOS transistor networks generally used to produce high (i.e. 1)signa ls, while NMOS networks are used to product low (0) signals? PMOS is used to drive 'high' because of the threshold voltage-effectThe same is true for NMOS to drive 'low'.A NMOS device cant drive a full '1' and PMOS cant d rive full '0' Maximum Level depends on vth of the device. PMOS/NMOS aka CMOS giv es you a defined rail to rail swing 2) On IC schematics, transistors are usually labeled with one, or sometimes two numbers. What do each of those numbers mean? The numbers you see there are usually the width and the length of the devices (c hannel dimensions drawn in the layout)If given only one number it's the width co mbined with a default length 3) Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usuall y limited to four?

To limit the height of the stack. As we all know, the number of transistor in th e stack is usually equal to the number of input. The higher the stack the slower it will be. 4) What is meant by static and dynamic power with respect to the op eration of a CMOS gate? Why do CMOS gates dissipate close to zero static power? Why is the static power not exactly zero? Cool What is a transmission gate, and what is it used for typically? Why are transmission gates made with both PMOS and NMOS transistors? 9) What are the major factors that determine the speed that a logic signal propa gates from the input of one gate to the input of the next driven gate in the sig nal's path? 10) What are some of the major techniques that are usually considered when one w ants to speed up the propagation speed of a signal? 11) What is the difference between a mask layer and a drawn layer in an IC layou t? Why do layout designers usually only specify drawn layers? 12) In an IC layout, what is a polygon and what is a path? What are the advantages and disadvantages of each? A polygon is a polygon and a pad is a pad. A pad can be easily edited and reshap ed, however, it's off grid with 45 degree angle. Polygon is always on-grid, unle ss it's a copy and flip. However, polygon is hard to edit and work with. 13) Wha t is the difference between a contact and a via? What is a "stacked" via process? Via: a contact between two conductive layers. Contact:Opening in an insulating f ilm to allow contact to an underlying electronic device. The placement of vias d irectly over the contacts or other,lower vias is known as stacked via. 14) Why i s it that NMOS transistors can be created directly in a P-type substrate, wherea s PMOS transistors must be created in an N-type well? 15) Why must transistors be provided with "bulk" connections? What voltage levels are connected to a p-type substrate and an n-type well throu gh these connections, and why? To make the parasitic diodes reverse biased.p type substrstrate is generally con nected to the most negative supply and n well is connected to the most positive supply of the circuit 16) What are process design rules? What is their major purpose? How are design rules created? 17) What are width rules, space rules, and overlap rules? 18) What is a "vertical connection diagram"?

What is it used for? vertical connection diagram illustrates the relative position, going vertically, of all the drawn layers. Such diagrams are especially useful in complex process ses, such as DRAM processes. 19) The routing strategies for the power grid and g lobal signals are usually defined at the start of planning a new chip floorplan. Why? 20) What are the major advantages of hierarchical IC design? Concurrent design Design reuse Predictable schedules

21) Define what is meant by the terms design rules checking, layout versus schem atic, and electrical rules check? Are all three procedures required in every chip design? 22) What is meant by the term "porosity"? Why is it desirable for a cell or macro to have high porosity? 23) What are the main differences in priorities between microprocessor design, A SIC design, and memory design? How are those differences reflected in the corresponding design flows? 24) What is an "application-specific memory", according to Clein? What are some specific examples of this part type? 25) What is the difference between a soft IP block (soft core) and a hard IP blo ck (hard core)? Softcore - most flexible - exist either as a gate-netlist or RTL. Hardcare - bes t for plug and play - less portable and less flexible. - physical manifestations of the IP design. 26) In ASIC design, what are the main advantages of expressin g the design using a hardware description language, such as VHDL or Verilog? The main reason for using high level hardware design like VHDL or Verilog is eas y generating hundred of million gate counts chip better than schematic entry des ign. 27) Why are memory layouts designed primarily from the bottom up, instead of fro m the top down, like other ICs? With respect to a memory layout, what is meant by "array efficiency"? 29) What is "pitch-limited layout"? What are some of the major circuits in a memory layout that must meet pitch-limi ted constraints? 30) What are some of the typical kinds of cells that one would expect to find in a library of standard cells? 31) The layout of standard cells is constrained to simplify the job of place & r oute tools. Give several examples of these constraints. 32) Why did older cell l ibraries include so-called feed through cells? Why are such cells no longer required in cell libraries for modern processes?

33) What is electro migration? How does electro migration affect the design of a standard cell based design? 34) What is a gate array? Why are main advantages of using gate arrays to implement an IC? What are some of the main disadvantages, with respect to custom design or standa rd cell based design? 35) Why might one want to use some gate array based design inside an otherwise c ustom IC design, according to Clein's experience? 36) What are some of the major similarities and differences of standard cells an d datapath cells? 37) How is the problem of driving a clock node different from that of designing a regular signal node? What are the key goals when laying out a clock node? What is a "pad frame"? What are "staggered" pads? 39) Why are 90 degree corners usually avoided in the layout of pad cells? 40) In the layout of output pad driver transistors, why is the gate length often lengthened at both ends of the gate? 41) Why is the pad ring provided with power supply connections that are separate from those of the core design? 42) What are so-called friendly cells in a DRAM core design? Why and where these cells included in a memory design? 43) Why are metal straps used along with polysilicon wordlines in memory designs ? 44) Why are wordline driver circuits very long and narrow? 45) Describe some of the alignment keys that are included in IC layouts. 46) Why is the power supply interconnect layout layout planned out before other element s? Similarly, why are busses, differential signals, and shielded signals routed bef ore other general signals? 47) What are the root and resistance styles of power supply layout? 4Cool What are some of the main reasons why clock skew minimization is such a ma jor design challenge? 49) What are the major advantages and disadvantages of using a single clock tree conductor driven by one big buffer?

50) In ASIC design flows, why are clock trees inserted after the logic cells hav e been placed? In such clock trees, how is clock skew minimized at the leaves of the tree? 51) What is a routing channel? Why are routing channels used in IC layouts? 52) Why is the estimated area for routing channels increased by 10% during early stages of layout planning? 53) When routing a signal interconnect, why is it desirable to minimize layer ch anges through vias? 54) Interconnect resistance is usually minimized in IC layouts. Give at least fo ur situations where a deliberably large, but controlled, resistance is usually r equired? 55) Why should minimum-width paths be avoided in the design of deliberate resist ances? 56) Usually one wishes to minimize the capacitance of electrical nodes in an IC design. Give four examples of circuits where one would wish a larger, but contro lled, capacitance at a node? 57) The capacitance on a node is the sum of several components. What is meant by fringe capacitance? How does reducing the width of a conductor affect the fringe capacitance? 5Cool How can the parasitic capacitance between two signal nodes possibly cause the signal transition on one of the nodes to be unexpectedly sped up? 59) How can a layout designer help ensure that the propagation delay along two c onductors is very similar? By running the two traces side by side and making them of equal length. 60) List four situations where it may be desirable to have 45 degree corners in the inte rconnect. 61) Explain what is meant by electromigration. What are some possible consequences of unexpectedly high electromigration? How is electromigration controlled in IC layout design? 62) Why are wide metal conductors, such as those in the power rings, provided wi th slits? What constraints must be followed when positioning these slits? 63) When placing multiple vias to connect two metal conductors, why is it better to space the vias far apart from each other? 64) Why would a DRAM layout be verified against two or more different sets of de sign rules? 65) What is the antenna effect, and how can it cause problems in an IC design? What are two layout techniques that can be used to reduce vulnerability to the a ntenna effect?

66) What is the purpose of minimum area design rules? 67) What is the purpose of end overlap rules? 6Cool What is the phenomenon of latch-up? Why is it a serious concern in CMOS layout design? 69) Describe six different layout strategies that are commonly used to minimize the possibility of latch-up. 70) Why is it wise to plan designs to make it easie r to change details later? 71) What is meant by metal strap programmability and via programmability? Give one example where each techniques is commonly used. 72) What is the differe nce between test pads and probe pads? 73) Dan Clein advocates the use of contact and via cells, which is not a common design practice. What are his reasons? 74) In which situation should one avoid using the minimum allowed feature sizes allowed by the design rules? 75) What fundamental factors limits the speed with which detected design errors can be corrected? 76) When floor planning a chip at the start of the IC layout process, what are t he main goals in deciding how to arrange the major blocks in the design? power line, noise, clock tree? ! 77) How is block floor planning different from chip floor planning? 78 What is a silicon compiler? 79) What is the difference between a channel router and a maze router? Which type of router will tend to produce higher utilization factors? 80) What is a chip assembly tool? What kind of routing should a chip assembly tool provide to have maximum flexibi lity? 81) At IBM, it has been found to be advantageous to sacrifice performance when m igrating a chip design in one process into a second process. Process migration i s facilitated by the use of "migratable design rules". What is the major benefit that can be obtained by such rules to offset the loss in potential chip perform ance? 82) At IBM a design methodology has been developed that makes the layout of stan dard cells very similar to that of gate array cells. What is the potential benef it of intermixing such cells in the same chip design? 83) In its ASIC design flow, IBM uses a formal verification tool that performs a technique called Boolean equivalence checking. What is the primary potential be nefit of using formal verification methods in design verification? What is the conventional way of verifying the equivalence of different implement ations of the same function?

84) IBM has standardized its logic design on the use of pulse-triggered latches, whereas the rest of the industry has tended to adopted design based on edge- tr iggered flip-flops. What is the strategy that IBM has adopted to be able to acco mmodate designers from other companies who wish to have ASICs fabricated through IBM? 85) Why are terminator cells sometimes used when clock trees are inserted into a block of placed standard cells? 86) When constructing a clock tree with distributed buffers, why is it very desi rable to keep the buffers lightly loaded near the root of the clock distribution tree? Why can leaf nodes of the clock tree can be loaded more heavily? Why does one aim to have a balanced clock tree? 87) What is the difference between two- and three-dimensional analysis of interc onnect capacitance. 8Cool Guard bands are usually built into the timing estimate s employed by logic synthesis, cell placers, and other CAD tools. What is lost w hen the guard bands are relatively large? What could be gained if the timing estimates could be made more accurate? 89) Full 3-D capacitance calculations are generally extremely timing consuming. How can the technique of tunneling be used to make such calculations efficient e nough to use in large IC designs? 89) The output of a 3-D field solver is a charge distribution over the signal ne t under consideration, and a charge distribution over the surrounding passive ne ts. Generally the signal net is assumed to be at a potential of 1 volt while the other nets are held at 0 volts. How can the signal net's self-capacitance and c oupling capacitance then be computed? 90) Moore's Law predicts a doubling in the number of transistors per chip every two to three years. The major factor supporting Moore's Law is improvements in l ithographic resolution that permit finer features. What are the two other major factors that Moore believes have allowed Moore's Law to hold? Even if physical factors allow for further increases in per-chip component densi ty, what other factors could slow or even stop Moore's Law in practice? 91) What is meant by the term "dual damascene process"? How has the availability of this type of process simplified the creation of mult iple interconnected metal layers? 92) In processes that have multiple layers of metal interconnect, why is it comm on to make the upper wires thicker than the lower layers? (The use of fat wires is sometimes called "reverse scaling".) In which situation s would one be willing to use reverse scaling and hence appear to throw away the possible advantages of thinner wires? 93) What are some of the important reasons why DRAM technology has been a pionee r for semiconductor technology advances? 94) Briefly explain what are planar DRAM cells, trench capacitor DRAM cells, and stacked capacitor DRAM cells. Which type of cell is becoming dominant in embedd

ed DRAMs? Why is this so? 95) There are numerous technological challenges and additional costs with embedd ed DRAM. Describe three of the main potential advantages that could be gained wi th embedded DRAM. What are characteristics of an application that could benefit from using embedded DRAM? 96) What are the three most common process solutions to providing embedded DRAM? Discuss some of the important trade-offs that must be made when selecting a proc ess strategy for embedded DRAM