Giao Trinh Thuc Hanh Vi Dieu Khien Va Vi Xu Ly

KHOA CNG NGH THNG TIN
B MN IN T - VIN THNG
GIO TRNH:
THC HNH VI IU KHIN & VI X LY
Ngi bin soan: ThS.VU THANH VINH
THAI NGUYN, NM 2010
MUC LUC
PHN I: M T H THNG..........................................................................................4
I.Tng quan h thng.....................................................................................................4
II.Module LMD01.........................................................................................................6
III.Module LMD02........................................................................................................8
IV.Module LMD03........................................................................................................9
V.Module LMD04.......................................................................................................10
VI.Module LMD05......................................................................................................12
VII.Module LMD06....................................................................................................14
VIII.Module LMD07...................................................................................................16
IX.Module LMD09 Module iu khin chnh..........................................................16
PHN II: THC HNH.................................................................................................18
BI 1: KHO ST MA TRN LED 8x8 MT MU V QUT HNG...............18
I. MC CH..........................................................................................................18
II. THIT B S DNG.........................................................................................18
III.THC HNH.....................................................................................................21
1.Kim tra LMD..................................................................................................21
2. Kim tra khi m cathode ULN2803............................................................21
3. Kim tra b m cc dng............................................................................21
4.Kim tra khi cht hng...................................................................................22
5.Kim tra khi m hng...................................................................................22
6.S dng khi LMD09 lp trnh iu khin thay i ni dung hin th ch.....22
BI 2: KHO ST MA TRN LED 8x8 MT MU V QUT CT..................23
I. MC CH..........................................................................................................23
II. THIT B S DNG.........................................................................................23
III. THC HNH....................................................................................................25
1. Kim tra LMD.................................................................................................25
2. Kim tra khi m Cathode ULN2803............................................................26
3.Kim tra b m cc dng.............................................................................26
4.Kim tra khi cht ct......................................................................................26
5.Kim tra khi m ct......................................................................................27
BI 3: KHO ST MA TRN LED 8x8 2 MU XANH V PHNG PHP
QUT HNG..............................................................................................................28
I. MC CH..........................................................................................................28
II. THIT B S DNG.........................................................................................28
III. THC HNH....................................................................................................31
1.Kim tra LMD..................................................................................................31
2. Kim tra b m cc dng............................................................................31
3.Kim tra khi MCHT...............................................................................32
4. S dng khi LMD09 lp trnh iu khin thay i ni dung hin th ch....32
BI 4: KHO ST MA TRN LED 8x8 2 MU XANH V PHNG PHP
QUT CT..................................................................................................................33
I. MC CH..........................................................................................................33
II. THIT B S DNG.........................................................................................33
III. THC HNH....................................................................................................36
1.Kim tra LMD..................................................................................................36
2.Kim tra b m cc m DEMG, DEMR........................................................36
3.Kim tra khi MCHT...............................................................................37
2
BI 5: KHO ST MODULE HIN TH 16x32 IM MT MU......................38

I. MC CH..........................................................................................................38
III. THIT B S DNG........................................................................................38
III.THC HNH.....................................................................................................43
1.Kim tra LMD..................................................................................................43
2.Kim tra b m cc m ULN2803.................................................................43
3.Kho st hot ng ca module........................................................................43
BI 6: KHO ST MODULE HIN TH 16x32 IM HAI MU........................45
I.MC CH...........................................................................................................45
II.THIT B S DNG..........................................................................................45
III.THC HNH.....................................................................................................48
1.Kim tra LMD..................................................................................................48
2.Kim tra b m cc m ULN2803.................................................................48
3.Kho st hot ng ca module........................................................................49
BI 7: KHO ST HOT NG CA BNG TIN IN T..............................50
I. MC CH..........................................................................................................50
II. THIT B S DNG.........................................................................................50
III. THC HNH....................................................................................................50
1.Bt bng tin in t...........................................................................................50
2.Khi ng phn mm iu khin......................................................................50
3.Thay i ni dung, lu ni dung cho bng tin..................................................51
PHN I: M T H THNG
I. Tng quan h thng
Gii thiu
LMD TS l h thng m hnh o to phc v kho st, nghin cu, thc hnh
thit k bng thng tin in t s dng cng ngh ma trn n LED (Light
Emitting Diode i t pht quang). H thng gip sinh vin tip cn vi cng
ngh hin th bng bng ma trn n LED t c bn n nng cao, t sinh
vin c th hiu, thit k c h thng bng. H thng c thit k theo t duy
logic k thut lin mch t u tr cui da theo cch nhn ca sinh vin, cng
vi s sp xp, phn chia bi bn theo cc vn chuyn mn chi tit r rng.
c tnh
Lm quen vi cc linh kin chc nng
Thit k dn tri
Cc im kim tra (test point)
S nguyn l r rng
Phn cp t c bn n nng cao
Phn chia thnh nhiu module
Kho st phng php qut hng, qut ct
Hin th mt mu v t hp 2 mu xanh
Cc thnh phn h thng

H thng c chia thnh 9 module theo bi thc hnh, mt khung gi chnh
bng kim loi cc module. Khi s dng module no th ci module trn
ln ray ca khung gi kim loi.
Bng di y l danh sch cc module v chc nng ca chng
Tn
LMD01
LMD02
LMD03
LMD04
LMD05
LMD06
LMD07
LMD09
Khung
M t
Ma trn LED n sc 8x8, qut theo hng, khi qut hng, m hng,
cht hng, m cathode, m anode, cc cht cp ngun kim th tn
hiu
Ma trn LED n sc 8x8, qut theo ct, khi qut ct, m ct, cht
ct, m cathode, m anode, u ni tn hiu iu iu khin v d
liu, cc cht cp ngun kim th tn hiu
Ma trn LED hai mu xanh/ 8x8, qut theo hng, khi qut hng,
m cht hng, m anode, u ni tn hiu iu iu khin v d
liu, cc cht cp ngun kim th tn hiu
Ma trn LED hai mu xanh/ 8x8, qut theo ct, khi qut ct, m
cht ct, m cathode, u ni tn hiu iu iu khin v d liu, cc
cht cp ngun kim th tn hiu
Module hin th mu , 16x32 pixel, qut theo hng, khi kch dng,
m cht d liu, u vo/u ra tn hiu iu khin v d liu, cc
cht cp ngun kim th tn hiu
Module hin th hai mu xanh/ 16x32 pixel, qut theo hng, khi
kch dng, m cht d liu, u vo/u ra tn hiu iu khin v d
liu, cc cht cp ngun v kim th tn hiu
Bng tin in t 16x96 pixel, outdoor, n sc, giao tip RS232,
ngun 220VAC
Board iu khin chung, MCU AT89S52, 16Kbyte Ram, RS232,
LMD port, KeyBoard, np ISP v cp ngun cho th nghim
Gi bng kim loi
II. Module LMD01

LMD01 l ma trn LED n sc 8x8, qut theo hng, khi qut hng, m hng,
cht hng, m cathode, m anode, cc cht cp ngun kim th tn hiu
LMD01 cha cc loi, linh kin c bn, v l thuyt c bn iu khin bng
LED. LMD01 a ra mt ma trn LED 8x8 im, n sc () v cc linh kin
iu khin mt LMD theo phng php u tin Qut theo hng.
LMD01 gm cc thnh phn sau:
Ma trn LED 8x8 pixel, n sc ()
Khi m Kathode ULN2803
Khi m Anode 74LS574
Khi m d liu hng 74LS164
Khi cht d liu hng 74LS573
Khi qut hng 74LS164
Module c cht cm ngun 5V, jack ni tn hiu iu khin kt ni vi

module iu khin chung. Hnh 1 l module LMD01.
Cc thnh phn c b tr dn tri, c s nguyn l r rng, cc ng tn
hiu c cc cht o th.
S nguyn l
Hnh 1. S nguyn l LMD01
III. Module LMD02

LMD02 a ra mt ma trn LED 8x8 im, n sc () v cc linh kin iu
khin mt LMD theo phng php Qut theo ct.
hiu c cc cht o th.
Ma trn LED 8x8 pixel, n sc ()
Khi m Kathode ULN2803
Khi m Anode 74LS574
Khi m d liu ct 74LS164
Khi cht d liu ct 74LS573
Khi qut ct 74LS164
Module c cht cm ngun 5V , jack ni tn hiu iu khin kt ni vi

S nguyn l

8
IV.Module LMD03
LMD03 a ra mt ma trn LED 8x8 im, hai mu xanh/ v cc linh kin
iu khin mt LMD theo phng php Qut theo hng.
hiu c cc cht o th.
Ma trn LED 8x8 pixel, 2 mu xanh/
Khi m cht d liu mu xanh 74LS595
Khi m cht d liu mu 74LS595
Khi m Anode 74LS574
Khi qut hng 74LS164

S nguyn l
V. Module LMD04
LMD04 a ra mt ma trn LED 8x8 im, hai mu xanh/ v cc linh kin
iu khin mt LMD theo phng php Qut theo ct.
hiu c cc cht o th.
Khi m mu xanh ULN2803
Khi m mu ULN2803
Khi qut ct 74LS164
Khi m cht d liu ct 74LS595

S nguyn l
10
11
VI.Module LMD05
LMD05 l mt module hin th 16x32 pixel, n sc mu trn c m kch
dng Anode, m Kathode, m cht d liu theo hng. Cc thnh phn c b
tr dn tri, c s nguyn l r rng, cc ng tn hiu c cc cht o th.
Ma trn LED 16x32 pixel, 1 mu
Khi m d liu hng 4 IC 74LS574
Khi cht d liu hng 4 IC 74LS574
Khi m Anode 4 IC ULN2803
Jack tn hiu vo, jack tn hiu ra

S nguyn l
12
13
VII.
Module LMD06
LMD06 l mt module hin th 16x32 pixel hai mu xanh v , trn c cc

khi m kch dng Anode, m Kathode, m cht d liu theo hng. Cc thnh
phn c b tr dn tri, c s nguyn l r rng, cc ng tn hiu c cc
cht o th.
Khi m cht d liu hng 16 IC 74LS574
Khi m Anode 4 IC ULN2803
Jack tn hiu vo, jack tn hiu ra

S nguyn l
14
15
VIII.
Module LMD07
Hnh 7. LMD07 Bng tin in t 16x96 pixel n sc (xanh/)

LMD07 l mt bng thng tin in t hon chnh 16x96 pixel mt mu , vi
cc tham s k thut nh sau:
LED outdoor
16x96 pixel mu
MCU AT89S52, 8k flash ROM
16 Kbyte RAM
Giao din truyn thng RS232
S dng ngun 220VAC

IX.Module LMD09 Module iu khin chnh
LMD09 l h vi iu khin cha cc cc thnh phn phc v cho cc bi thc

hnh cc phng php iu khin LMD bng chng trinh iu khin
Cc thnh phn c trn module:
-
MCU PIC AT89S52
16K RAM
Giao din RS232
Bn phm 8
Giao din ISP
Cng iu khin LMD
S nguyn l
16
Hnh 8. S nguyn l mch LMD09
17
PHN II: THC HNH

BI 1: KHO ST MA TRN LED 8x8 MT MU V QUT HNG
I. MC CH
Tm hiu cu trc ca ma trn LED, kim tra sng ca tng n LED, tm
hiu phng php iu khin qut hng, v mt s linh kin iu khin
II. THIT B S DNG
Module LMD01, LMD09, dy ngun, dy cp tn hiu
Nguyn l lm vic
- Khi qut hng lm nhim v to ra tn hiu qut cho 8 chn u ra t H1 n

H8. Cc chn u ra s ln lt v lun phin c tn hiu mc cao, ti mt thi
im ch c mt chn c tn hiu mc cao, cc chn cn li mang tn hiu mc
18
thp ht, sau mt khong thi gian quy nh s chuyn sang chn tip theo, c
nh th t chn u tin cho n ht chn cui cng sau li quay li chn u
tin. Thi gian tn ti trng thi mc cao ca mi chn u ra l bng nhau
nhng c th thay i c, tng thi gian qut ht mt vng 8 chn u ra
cng thay i c, do vy phi quyt nh c thi im bt u chuyn trng
thi ca mt chn bt k. Khi qut hng c mt u vo tn hiu ng b SYN
v mt u vo xung nhp. u vo xung nhp quyt nh thi im chuyn
i trng thi ca u ra, cn u vo tn hiu ng b xc nh thi im bt
u mt vng qut. Ti thi im trc khi bt u mt vng qut mi tn hiu
SYN bng mt, ngay sau l mt xung dng a vo lm cho u ra H1
chuyn trng thi t 0 sang 1, sau mt khong thi gian bt u chuyn trng
thi cho chn u ra tip theo (H2) tn hiu SYN = 0, v lin l mt xung
dng c a vo u vo xung nhp, tn hiu SYN ch bng 1 khi bt u mt
vng qut mi cn li ton b thi gian qut lun = 0.
- Khi m hng lm nhim v cha d liu ca mt hng sng sng cho
vic hin th mt hng, d liu c a vo kiu ni tip v dch chuyn trn
cc chn u ra b1 n b8. D liu b8 c a vo u tin, b1 dch n sau,
dch n khi d liu ca b1 c a vo th d liu b8 dch n chn b8 v d
liu ca b1 c trn chn b1. Khi ny c mt chn u vo xung nhp s dng
cho vic c d liu vo.
- Khi cht hng lm nhim v cht d liu ca mt hng. Trc khi hin th
mt hng d liu phi sn hng cc u vo D ca khi cht hng, mt xung
dng c a vo y d liu t cc chn u vo D ti cc chn u ra Q
v gi nguyn cho mt hng c hin th trong khong thi gian xc
nh trc hin th mt hng tip theo.
- Khi m Kathode lm nhim v to in p m ht dng cho kathode ca
n LED, cc u ra ca khi s ni n cc cathode ca n LED. Cc u vo
c ni vi d liu iu khin n LED.
- Khi m Anode lm nhim v cp ngun dng cho nhm cc LED v cc
u ra Q ni n cc chn A ca n LED.
- Khi ma trn n LED l mt ma trn 8x8 n LED cc chn A ca mt hng
LED c ni chung to nn 8 chn A chung, cc chn K ca mt ct c ni
chung v to nn 8 chn K chung.
19
hin th ton b ma trn LED cc hng s ln lt c lun phin hin th t

hng u tin cho n hng cui cng ri lp li. Ti mt thi im ch c mt
hng c hin th.
Trc thi im bt u hin th hng u tin d liu ca hng u tin c
a vo b m hng theo cch ni tip t b8 vo trc ri n b1, xung nhp
c cp t bn ngoi vo c mi bt d liu tun t, khi ht d liu
ri th xung nhp khng c php lm vic na.
Tip theo l hin th d liu ca hng u tin, khi hin th tn hiu SYN c
a vo = 1, sau s c mt xung dng OUTCLK, xung dng OUTCLK s
ng thi lm hai vic: 1 l a ton b d liu ca hng u tin m ang tn ti
u vo b cht hng n u ra b cht hng v 2 t u ra H1 ca khi qut
hng ln mc cao hin th hng u tin. Vy l d liu ca hng u tin
c chuyn n b m Kathode, H1 cng c chuyn ln mc cao a
vo b m Anode, qu trnh bt u hin th hng u tin hon tt, vic cn
li l ca hai b m. B m Kathode s khuych i o cc bit d liu v
iu khin vic ht dng cho 8 Kathode chung, b m Anode s cp ngun
dng cho mt hng. Trng thi ny c duy tr mt khong thi gian xc nh
cc LED ca hng u tin c hin th trong mt khong thi gian xc nh.
Khi ht thi gian cho vic hin th hng u tin th vic hin th hng th hai s
phi bt u.
Vic bt u cho hin th hng th 2 cng ging nh hng th nht ch c im
duy nht khc bit l tn hiu SYN t vo phi bng 0 cn li th mi th tc
khng c g thay i. Do vy khi c xung OUTCLK th H1 s mc thp v
mc cao trc ca n s c dch sang H2 lm cho A2 c cp ngun v
20
hng th hai sng. Hng th hai cng s c hin th trong mt khong thi
gian xc nh v kt thc
Qu trnh c din ra lp li tng t i vi cc hng sau cho n ht hng 8.
Kt thc thi gian hin th hng 8 l ht mt chu trnh qut ton b LMD, mt
chu trnh qut mi s li bt u. Qu trnh c lp i lp li nh th trong sut
thi gian hot ng ca LMD.
III.THC HNH
1.Kim tra LMD
-
m bo ma trn LED HY2088BS c gn ln MATRIX1
Khng cp ngun cho bng LMD01
Dng ng h vn nng c hc, thang o 1Ohm
a que vo mt chn K1 (dng kp hoc cm tay)
Qut u que en ca ng h qua cc cht t A1 n A8, khi qut

quan st LMD s thy cc n ct 1 sng u ln lt t hng 1 n hng
8 l tt, chng t khng LED no hng v mch ni ng cu hnh chn
Ln lt lm nh th vi cc chn t K2 n K8, kim tra cc
ct cn li ca ton b LMD.
Sau khi kim tra nu khng thy LED no hng l tt.
2. Kim tra khi m cathode ULN2803
-
LMD c kim tra v gn ln MATRIX1
IC ULN2803 gn ln ca khi DEMK
Khng cm IC trn cc khi MA1, v EMK1
Khng cp ngun 5V cho bng, ch u dy cho cht GND
Ni dy t ngun +5V vi mt u in tr 100 Ohm, u kia ca

in tr ni vi mt chn A bt k.
Dng mt dy 5V khc qut qua cc cht t b1 n b8, khi qut
thy cc LED ca hng tng ng vi chn A ln lt sng u l
ULN2803 tt.
3. Kim tra b m cc dng
-
Gi nguyn cc linh kin nh phn trn
Kim tra ca khi QUETHANG khng c g, nu c th b ra
IC 74573(4) gn ln ca khi DEMA
21
Cp ngun 5V v GND cho bng.
Dng mt dy ngun 5V chm vo cht b bt k gia khi CHT

HNG v khi MK
Dng mt dy ngun 5V khc qut qua cc cht t H1 n H8, khi
qut quan st thy cc LED ca ct tng ng vi b sng u l tt. C
hai khi MA V MK u tt.
4.Kim tra khi cht hng
-
Gi nguyn cc linh kin nh phn trn.
Kim tra ic ca khi M HNG khng c g, nu c th b ra
Gn IC 74573(4) ln ca khi CHOTHANG
a tn hiu 0 hoc 1 vo u vo bt k t D1 n D8 ca khi

CHT HNG, dng thanh kim loi hoc ngun 0V hoc 5V qut vo
cht OUTCLK, dng ng h o in p ca cc u ra t Q tng ng
vi u vo D sau mi ln qut.
Lm li nh trn vi ln vi cc tn hiu vo l 0 , 1 ta s thy u
vo D c a n u ra Q v sau mi ln c xung, trng thi u ra s
c gi nguyn nu khng c mt xung qut ln cht OUTCLK mc d
u vo c thay i trng thi 0/1.
5.Kim tra khi m hng
-
Gn IC 74xx164 ln ca khi DEMHANG v QUETHANG
Ch : tt c cc IC phi cm ng chiu
-
Ni cht ngun 5V v GND cho bng (cha bt ngun)
Khi iu khin LMD09 c sn chng trnh LMD01 trn chp

89s52
-
Ni cp tn hiu 4 chn t bng LMD09 ti LMD01
Bt ngun cho c hai khi.
sn.
nu khng c g sai trn LMD s hin th hnh nh/ k t lp trnh
dng my hin sng quan st tn hiu ti cc cht DATA, INCLK,

OUTCLK, B, H, A, K thy r qu trnh lm vic ca khi QUT
HNG, M HNG v ton b h thng
-
Phn tch gin xung ca 4 chn tn hiu
6.S dng khi LMD09 lp trnh iu khin thay i ni dung hin th ch

22
BI 2: KHO ST MA TRN LED 8x8 MT MU V QUT CT

I. MC CH
Kho st phng php iu khin qut ct, v mt s linh kin iu khin.
II. THIT B S DNG
Nguyn l lm vic
- Khi qut ct lm nhim v to ra tn hiu qut cho 8 chn u ra t C1 n

C8. Cc chn u ra s ln lt v lun phin c tn hiu mc cao, ti mt thi
thp ht, sau mt khong thi gian xc nh s chuyn sang chn tip theo, c
cng thay i c, do vy phi quyt nh c thi im bt u chuyn trng
thi ca mt chn bt k. Khi qut ct c mt u vo tn hiu ng b SYN v
mt u vo xung nhp. u vo xung nhp quyt nh thi im chuyn i
trng thi ca u ra, cn u vo tn hiu ng b xc nh thi im bt u
mt vng qut. Ti thi im trc khi bt u mt vng qut mi tn hiu SYN
23
bng mt, ngay sau l mt xung dng a vo lm cho u ra H1 chuyn

trng thi t 0 sang 1, sau mt khong thi gian bt u chuyn trng thi cho
chn u ra tip theo (H2) tn hiu SYN = 0, v lin l mt xung dng c
a vo u vo xung nhp, tn hiu SYN ch bng 1 khi bt u mt vng qut
mi cn li ton b thi gian qut lun = 0.
- Khi m ct lm nhim v cha d liu ca mt ct sng sng cho vic
hin th mt ct, d liu c a vo kiu ni tip v dch chuyn trn cc chn
u ra b1 n b8. D liu ca b8 c a vo u tin, dch dn t b1 n b8,
cho n khi d liu ca b1 c a vo th d liu b8 dch n chn b8 v d
liu ca b1 c trn chn b1. Mt chn u vo xung nhp INCLK cn cho vic
c d liu vo.
- Khi cht ct lm nhim v cht d liu ca mt ct. Trc khi hin th mt
ct d liu phi sn hng cc u vo D ca khi cht ct, mt xung dng
c a vo y d liu t cc chn u vo D ti cc chn u ra Q v gi
nguyn cho mt ct c hin th trong khong thi gian xc nh trc
hin th mt hng tip theo.
- Khi m Kathode lm nhim v to in p m ht dng cho nhm kathode
ca cc n LED, cc u ra ca khi s ni n cc cathode ca n LED. Cc
u vo c ni vi d liu iu khin n LED.
- Khi m Anode lm nhim v cp ngun dng cho cc LED, nn cc u
ra Q ni n cc chn A ca n LED
- Khi ma trn n LED l mt ma trn 8x8 n LED cc chn A ca mt hng
LED c ni chung to nn 8 chn A chung, cc chn K ca mt ct c ni
chung v to nn 8 chn K chung
24
hin th ton b ma trn LED cc ct s ln lt c lun phin hin th t

ct u tin cho n ct cui cng ri lp li. Ti mt thi im ch c mt ct
c hin th.
Trc thi im bt u hin th ct u tin d liu ca ct u tin c a
vo b m ct theo cch ni tip t b8 vo trc ri n b1, xung nhp c cp
t bn ngoi vo c mi bt d liu tun t, khi ht d liu ri th xung
nhp khng c php lm vic na.
Tip theo l hin th d liu ca hng u tin, khi hin th tn hiu SYN=1 c
a vo, sau s c mt xung dng OUTCLK, xung dng OUTCLK s ng
thi lm hai vic: 1 l a ton b d liu ca ct u tin m ang tn ti u
vo b cht ct n u ra b cht ct; v 2 l dch tn hiu SYN=1 n u ra
C1 ca khi qut ct hin th ct u tin. Vy l d liu ca ct u tin
c chuyn n b m Anode, C1 cng c chuyn ln mc cao a vo
b m Kathode, qu trnh bt u hin th hng u tin hon tt, vic cn li
l ca hai b m. B m Anode s khuych i cc bit d liu v iu khin
vic cp ngun dng cho 8 Anode , b m Kathode s khuych i o tn
hiu tch cc ct ht dng cho mt ct. Trng thi ny c duy tr mt
khong thi gian xc nh cc LED ca ct u tin c hin th trong mt
khong thi gian xc nh. Khi ht thi gian cho vic hin th ct u tin th
vic hin th ct th hai s phi bt u.
Vic bt u cho hin th ct th 2 cng ging nh ct th nht ch c im duy
nht khc bit l tn hiu SYN t vo phi bng 0 cn li th mi th tc khng
c g thay i. Do vy khi c xung OUTCLK th C1 s mc thp v mc cao
trc ca n s c dch sang C2 lm cho K2 c ni t v ct th hai
sng. Ct th hai cng s c hin th trong mt khong thi gian xc nh v
kt thc
Qu trnh c din ra lp li tng t i vi cc ct sau cho n ht ct 8.
Kt thc thi gian hin th ct 8 l ht mt chu trnh qut ton b LMD, mt chu
trnh qut mi s li bt u. Qu trnh c lp i lp li nh th trong sut thi
gian hot ng ca LMD.
III. THC HNH
1. Kim tra LMD
-
Gn LMD HY2088BS ln MATRIX1
Khng cp ngun cho bng
25
a in p 0V vo mt chn K1 (dng kp hoc cm tay)
Ni dy t ngun 5V ni tip vi mt u in tr 100 Ohm (dng

kp hoc cm bng tay)
Qut u cn li ca in tr qua cc cht t A1 n A8, khi qut
quan st LMD s thy cc n ct 1 sng u ln lt t hng 1 n hng
8 l tt, chng t khng LED no hng v mch ni ng cu hnh chn
ct cn li ca ton b LMD. Cng c th kim tra theo tng hng bng
cch cho in p dng vo chn A v qut u 0V qua cc chn K1 n
K8.
Sau khi kim tra nu khng thy LED no hng l tt
2. Kim tra khi m Cathode ULN2803
-
LMD c kim tra v gn ln MATRIX1
IC ULN2803 gn ln ca khi DEMK
Khng cm IC trn cc khi DEMA2, v DEMK2
Khng cp ngun 5V cho bng, ch u dy cho cht GND
Ni dy t ngun +5V vi mt u in tr 100 Ohm, u kia ni

vi mt chn A bt k.
Dng mt dy 5V khc qut qua cc cht t b1 n b8, khi qut
thy cc LED ca hng tng ng vi chn A ln lt sng u l
ULN2803 tt.
3.Kim tra b m cc dng
-
Kim tra ca khi CHOTCOT khng c g
Dng mt dy ngun 5V chm vo cht C bt k gia khi

QUETCOT v khi MK
Dng mt dy ngun 5V khc qut qua cc cht t b1 n b8, khi
qut quan st thy cc LED ca ct tng ng vi C u sng l tt. C
hai khi MA V MK u tt.
4.Kim tra khi cht ct
-

26
Kim tra IC ca khi MCT khng c g, nu c th b ra
Gn IC 74573(4) ln ca khi CHOTCT
a tn 0 hoc 1 vo u vo bt k t D1 n D8 ca khi
CHTCOT, dng thanh kim kim loi hoc ngun 0V hoc 5V qut vo
cht OUTCLK, dng ng h o in p ca cc u ra t Q tng ng
vi u vo D sau mi ln qut.
Lm li nh trn vi ln vi cc tn hiu vo l 0 , 1 ta s thy u
vo D c a n u ra Q v sau mi ln c xung, trng thi u ra s
c gi nguyn nu khng c mt xung qut ln cht OUTCLK mc d
u vo c thay i trng thi 0/1.
5.Kim tra khi m ct
-
Gn IC 164 ln ca khi DEMCT v QUETCT
-

89s52
-
Nu khng c g sai trn LMD s hin th ch Z
Dng my hin sng quan st tn hiu ti cc cht DATA, INCLK,

OUTCLK, B, C, A, K thy r qu trnh lm vic ca khi
QUTCTT, MCT v ton b h thng
-
Phn tch gin xung ca 4 chn tn hiu
27
BI 3: KHO ST MA TRN LED 8x8 2 MU XANH V

PHNG PHP QUT HNG
I. MC CH
Kho st cu trc ca ma trn LED 8x8 2 mu xanh , kim tra sng ca
tng n LED, tm hiu phng php iu khin qut hng cho 2 mu, v mt s
linh kin iu khin
II. THIT B S DNG
Nguyn l lm vic
- Khi qut hng lm nhim v to ra tn hiu qut cho 8 chn u ra t H1 n

H8. Cc chn u ra s ln lt v lun phin c tn hiu mc cao, ti mt thi
thp ht, sau mt khong thi gian quy nh s chuyn sang chn tip theo, c
28

cng thay i c, do vy phi quyt nh c thi im bt u chuyn
trng thi ca mt chn bt k. Khi qut hng c mt u vo tn hiu ng b
SYN v mt u vo xung nhp. u vo xung nhp quyt nh thi im
chuyn i trng thi ca u ra, cn u vo tn hiu ng b xc nh thi
im bt u mt vng qut. Ti thi im trc khi bt u mt vng qut mi
tn hiu SYN bng mt, ngay sau l mt xung dng a vo lm cho u ra
H1 chuyn trng thi t 0 sang 1, sau mt khong thi gian bt u chuyn
trng thi cho chn u ra tip theo (H2) tn hiu SYN = 0, v lin l mt
xung dng c a vo u vo xung nhp, tn hiu SYN ch bng khi bt
u mt vng qut mi cn li ton b thi gian qut lun = 0.
-
Khi DEMCHOTG (v DEMCHOTR) lm nhim v cha d liu G v R
ca mt hng v cht d liu ti u ra hin th mt hng, d liu c a

vo kiu ni tip v xut ra song song. D liu ca R8 c a vo u tin, d
liu G1 c a vo cui. Khi 16 bit d liu c a vo 2 b MCHT,
mt xung dng OUTCLK c a vo y d liu ti cc chn u ra v
gi nguyn cho mt hng c hin th trong khong thi gian xc nh
trc khi hin th mt hng tip theo. Mt khi ny lm c 3 vic tng ng 3
khi: MHANG, CHTHNG, MK trong LMD01. MCHOTG phc v
cho mu xanh, MCHOTR phc v mu .
- Khi m Anode lm nhim v cp ngun dng cho nhm cc LED, cc
u ra Q ni n cc chn A ca n LED
- Khi ma trn n LED l mt ma trn 8x8 im, mi im gm 2 n LED
ni chung, Anode cc chn A ca mt hng LED c ni chung to nn 8 chn
A chung, cc chn Cathode ca mu xanh ca mt ct c ni chung v to nn
8 chn G chung, cc chn Cathode ca mu ca mt ct c ni chung v
to nn 8 chn R chung
29
Mt hng c hin th bao gm mt hng xanh v mt hng kt hp

hin th ton b ma trn LED cc hng s ln lt c lun phin hin th t
hng u tin cho n hng cui cng ri lp li. Ti mt thi im ch c mt
hng c hin th.
Trc thi im bt u hin th hng u tin, d liu ca hng u tin c
a vo b m cht theo cch ni tip t R8 vo trc ri n G1, xung nhp
INCLK c cp t bn ngoi vo c mi bt d liu tun t, khi ht
d liu ri th xung nhp khng c php lm vic na.
Tip theo l hin th d liu ca hng u tin, trc khi hin th tn hiu SYN=1
c a vo, sau s c mt xung dng OUTCLK, xung dng OUTCLK s
ng thi lm hai vic: 1 l a ton b d liu ca hng u tin m ang tn ti
trong b MCHT ra cc chn R v G ca LED matrix, v 2 l t u ra H1
ca khi qut hng ln mc cao hin th hng u tin. Vy l d liu ca
hng u tin u tin n cc chn Kathode (R v G), H1 cng c
chuyn ln mc cao a vo b m Anode, qu trnh bt u hin th hng
u tin hon tt, vic cn li l ca b m Anode. Cc bt 0 s iu khin
cho Kathode ni vi n sng, bt 1 s lm cho kathode tt, b m Anode s cp
ngun dng cho mt hang. Trng thi ny c duy tr mt khong thi gian
xc nh cc LED ca hng u tin c hin th trong mt khong thi gian
30
xc nh. Khi ht thi gian cho vic hin th hng u tin th vic hin th hng
th hai s phi bt u.
Vic bt u cho hin th hng th 2 cng ging nh hng th nht ch c im
duy nht khc bit l tn hiu SYN t vo phi bng 0 cn li th mi th tc
khng c g thay i. Do vy khi c xung OUTCLK th H1 s mc thp v
mc cao trc ca n s c dch sang H2 lm cho A2 c cp ngun v
hng th hai sng. Hng th hai cng s c hin th trong mt khong thi
gian xc nh v kt thc
Qu trnh c din ra lp li tng t i vi cc hng sau cho n ht hng 8.
chu trnh qut mi s li bt u. Qu trnh c lp i lp li nh th trong sut
thi gian hot ng ca LMD.
III. THC HNH
1.Kim tra LMD
-
LMD 2088DHG c gn ln MATRIX1
a in p 5V vo mt chn A1 (dng kp hoc cm tay)

kp hoc cm bng tay)
Qut u cn li ca in tr qua cc cht t G1 n R8, khi qut
quan st LMD s thy cc n hng 1 sng u ln lt t R1 n G8 l
tt, chng t khng LED no hng v mch ni ng cu hnh chn
Ln lt lm nh th vi cc chn t A2 n A8, kim tra cc
ct cn li ca ton b LMD
2. Kim tra b m cc dng
-
Kim tra ca khi QUETHANG, MCHT khng c g
Khng cm IC trn cc khi DEMCHOTR v DEMCHOTG
Dng mt dy ngun 0V chm vo cht R hoc G bt k
31
Dng mt dy ngun 5V khc qut qua cc cht t H1 n H8, khi

qut quan st thy cc LED ca ct tng ng vi R hoc G sng u l
Khi MA tt.
3.Kim tra khi MCHT
-
Gn IC 74595 ln ca khi DEMCHOtTR v DEMCHOTG,
Gn IC 74164 ln ca khi QUETHANG
-

89s52
-
Nu khng c g sai trn LMD s hin th ch nh lp trnh sn

OUTCLK, SYN, R, G, H, A thy r qu trnh lm vic ca khi QUT
Phn tch gin xung ca 4 chn tn hiu DATA, INCLK,
OUTCLK, SYN
4. S dng khi LMD09 lp trnh iu khin thay i ni dung hin th ch
32
BI 4: KHO ST MA TRN LED 8x8 2 MU XANH V

PHNG PHP QUT CT
I. MC CH
Kho phng php iu khin qut hng cho 2 mu, v mt s linh kin iu
khin
II. THIT B S DNG
Nguyn l lm vic
33
- Khi qut ct (QUETR, QUETG) lm nhim v to ra tn hiu qut cho 16

chn u ra t C1 n C16. Cc chn u ra s ln lt v lun phin c tn hiu
mc cao, ti mt thi im ch c mt chn c tn hiu mc cao, cc chn cn li
mang tn hiu mc thp ht, sau mt khong thi gian quy nh s chuyn sang
chn tip theo, c nh th t chn u tin cho n ht chn cui cng sau li
quay li chn u tin. Thi gian tn ti trng thi mc cao ca mi chn u ra
l bng nhau nhng c th thay i c, tng thi gian qut ht mt vng 16
chn u ra cng thay i c, do vy phi quyt nh c thi im bt u
chuyn trng thi ca mt chn bt k. Khi qut hng c mt u vo tn hiu
ng b SYN v mt u vo xung nhp OUTCLK. u vo xung nhp quyt
nh thi im chuyn i trng thi ca u ra, cn u vo tn hiu ng b
xc nh thi im bt u mt vng qut. Ti thi im trc khi bt u mt
vng qut mi tn hiu SYN bng mt, ngay sau l mt xung dng a vo
lm cho u ra C1 chuyn trng thi t 0 sang 1, sau mt khong thi gian bt
u chuyn trng thi cho chn u ra tip theo (C2) tn hiu SYN = 0, v lin
l mt xung dng c a vo u vo xung nhp, tn hiu SYN ch bng khi
bt u mt vng qut mi cn li ton b thi gian qut lun = 0.
- Khi DEMCHOTA lm nhim v cha d liu ca mt ct v cht d liu ti
u ra hin th mt ct, d liu c a vo kiu ni tip v xut ra song
song. D liu ca A1 c a vo u tin, d liu A8 c a vo cui. Khi
8 bit d liu c a vo b MCHTA, mt xung dng OUTCLK c
a vo y d liu ti cc chn u ra v gi nguyn cho mt ct
c hin th trong khong thi gian xc nh trc khi hin th mt hng tip
theo. Mt khi ny lm c 3 vic tng ng 3 khi: MCT, CHTCT,
MA trong LMD02.
- Khi DEMR v DEMG lm nhim v khuych i o cp ngun m ht
dng t cc Cathode chung ca LMD.
- Khi ma trn n LED l mt ma trn 8x8 im, mi im gm 2 n LED
ni chung Anode cc chn A ca mt hng LED c ni chung to nn 8 chn
A chung, cc chn Cathode ca mu xanh ca mt ct c ni chung v to nn
8 chn G chung, cc chn Cathode ca mu ca mt ct c ni chung v
to nn 8 chn R chung
34
hin th ton b ma trn LED 16 ct s ln lt c lun phin hin th t

ct C1 n C16 tng ng l G1 n R8 ri lp li. Ti mt thi im ch c mt
ct c hin th.
Trc thi im bt u hin th ct u tin, d liu ca ct u tin c a
vo b m cht theo cch ni tip t A1 vo trc ri n A8, xung nhp
INCLK c cp t bn ngoi vo c mi bt d liu tun t, khi ht
d liu ri th xung nhp khng c php lm vic na.
Tip theo l hin th d liu ca ct u tin, trc khi hin th tn hiu SYN=1
c a vo, sau s c mt xung dng OUTCLK, xung dng OUTCLK s
ng thi lm hai vic: 1 l a ton b d liu ca ct u tin m ang tn ti
trong b MCHT ra cc chn A ca LED matrix, v 2 l t u ra C1 ca
khi qut ct ln mc cao hin th ct u tin. Vy l d liu ca ct u tin
u tin n cc chn A, C1 cng c chuyn ln mc cao a vo
b m Kathode, qu trnh bt u hin th hng u tin hon tt, vic cn li
l ca b m Cathode. Cc bt 1 s iu khin cho Anode ni vi n sng, bt 0
s lm cho Anode tt, b m Cathode s ht dng cho mt ct. Trng thi ny
c duy tr mt khong thi gian xc nh cc LED ca ct u tin c
hin th trong mt khong thi gian xc nh. Khi ht thi gian cho vic hin th
ct u tin th vic hin th hng th hai s phi bt u.
35
Vic bt u cho hin th ct th 2 cng ging nh ct th nht ch c im duy

nht khc bit l tn hiu SYN t vo phi bng 0 cn li th mi th tc khng
c g thay i. Do vy khi c xung OUTCLK th C1 s mc thp v mc cao
trc ca n s c dch sang C2 lm cho K2 c ni t v ct th hai
sng. Ct th hai cng s c hin th trong mt khong thi gian xc nh v
kt thc
Qu trnh c din ra lp li tng t i vi cc ct sau cho n ht ct16. Cc
ct t 1 n 8 l cc ct cho mu xanh, cc ct t 9 n 16 l cc ct cho mu ,
do vy trong phng php ny 8 ct mu xanh c hin th trc sau n 8
ct mu .
Kt thc thi gian hin th ct 16 l ht mt chu trnh qut ton b LMD, mt
chu trnh qut mi s li bt u. Qu trnh c lp i lp li nh th, 8 ct mu
xanh v 8 ct mu lun phin nhau trong sut thi gian hot ng ca LMD.
III. THC HNH
1.Kim tra LMD
-
LMD 2088DHG c gn ln MATRIX1
a in p 5V vo mt chn A1 (dng kp hoc cm tay)

kp hoc cm bng tay)
Qut u cn li ca in tr qua cc cht t G1 n R8, khi qut
quan st LMD s thy cc n hng 1 sng u ln lt t R1 n G8 l
Ln lt lm nh th vi cc chn t A2 n A8, kim tra cc
ct cn li ca ton b LMD
2.Kim tra b m cc m DEMG, DEMR
-
Kim tra ca khi QUETG, QUETR, MCHT khng c g
IC 2803 gn ln ca khi DEMG, DEMR
Dng mt dy ngun 5V chm vo cht A
36
Dng mt dy ngun 5V khc qut qua cc cht t G1 n R8, khi

qut quan st thy cc LED ca hng tng ng vi A sng u l Khi
MG, DEMR tt.
3.Kim tra khi MCHT
-
Gn IC 74595 ln ca khi DEMCHOT
Gn IC 74164 ln ca khi QUETG, QUETR
-

89s52
-
Nu khng c g sai trn LMD s hin th ch X vi mu ch v

nn thay i
OUTCLK, SYN, R, G, H, A thy r qu trnh lm vic ca khi QUT
Phn tch gin xung ca 4 chn tn hiu DATA, INCLK,
OUTCLK, SYN
37
BI 5: KHO ST MODULE HIN TH 16x32 IM MT MU

I. MC CH
Tm hiu thit k ca module hin th 16x32 im, v phng php iu khin.
III. THIT B S DNG
Nguyn l lm vic
LMD05 l m hnh ca mt module hin th, dng ghp ni nhiu module ny
vi nhau c mt kch thc hin th ln hn.
- Khi m hng: lm nhim v tip nhn d liu ca mt hng. Khi m
hng gm cc IC U17, U18, U19, U20. Mi IC l b 8 DFF c lp vi nhau
nhng dng chung u vo CLK, mi IC c 8 u vo D v 8 u ra Q. Bn IC
c mc lin tip vi nhau, 8 u ra ca IC U17 ni vi 8 u vo ca U18,
tng t U19, U20 nh hnh v. u vo ca khi m hng l u vo ca U17.
D liu s c a vo khi m hng tng byte mt (8 bit ng thi) i km
vi mt xung INCLK. Khi d liu c u vo DFF, mt xung dng
INCLK s lm cho d liu chuyn n u ra v lu , u ra li c ni
n u vo ca DFF tip theo ng thi ni n u ra ca ton khi m hng.
Khi m hng c 8 u vo ni tip, 32 u ra dch chuyn, v 8 u ra lin tip
dnh cho vic ghp ni vi module tip theo. D liu c a vo 8 u vo
xen k vi tn hiu INCLK c vo, v dch chuyn trn 32 u ra. Hot ng
ca khi tng t nh thanh ghi dch. 8 bit d liu t vo u vo, 1 xung
dng inclk s dch 8 bit n 8 u ra v ni n b 8 u vo tip theo, sau 4
ln dch th ta c c 4 byte v c mt trn 32 u ra.
- Khi CHT HNG lm nhim v cht d liu ca mt hng u vo n
u ra v gi chng u ra trong thi gian hng hin th.
- Khi ma trn n LED l mt ma n LED 16 hng, 32 ct bao gm U1, U2,
U3, U4, U5, U6, U7 v U8, mi mt khi l mt ma trn 8x8. Mt hng c 16
LED, 16 kathode ca mt hang c ni chung vi nhau thnh mt chn K
chung. Mt hng c 32 LED, v chia lm hai na, 16 cathode ca mi na ni
vi nhau to nn mt chn K chung.
- Khi m Cathode: lm nhim v khuych i o tn hiu qut hng ht
dng cho cathode ca cc hng. u ra khi ny c ni n Cathode chung
ca cc hng (K). Khi ny s dng 4 IC 2803 gm U9, U10, U11 v U12, mi
ic c 8 cng ra, mi cng ra ni n mt chn K, mt chn K l ni chung ca 16
38
cathode ca mt na hng. U9, U10 dnh cho na tri t K1 n K16, U11 v 12

cho na phi t K17 n K32. Ton b khi ny co 32 cng ra chia cho cho na
l 16 cho bn phi, 16 cho bn trai, tng ng vi 16 hng cua ma trn LED.
Khi ny c 16 u vo, tng ng 16 hng. Mi u vo nhn tn hiu iu
khin ca mt hng, iu khin hai u ra cho hai na ca mt hng . Khi
ny n gin ch l khuych i o 16 tn hiu iu khin ni t cho hng v
tch hng thnh hai na cng sut iu khin.
39
40
- 16 tn hiu u vo iu khin hng tng ng vi 16 hng ca ma trn LED

- 8 u vo d liu
- INCLK, tn hiu xung nhp cho d liu vo
- OUTCLK, tn hiu xung nhp cho d liu ra
Cc u ra:
- 16 tn u ra iu khin hng tng ng vi 16 hng ca module tip theo
- 8 u ra d liu, ni n 8 u vo d liu ca module tip theo
- INCLK, dng cho module tip theo
- OUTCLK, dng cho module tip theo
Cc u ra ca module ny s ni n u vo ca module tip theo khi ghp ni
nhiu module khc nhau
hin th ton b ma trn LED, 16 hng s ln lt c lun phin hin th t
hng 1 n hng 16 tng ng l t K1v K2_1 n K16 v K2_16 ri lp li.
Ti mt thi im ch c mt hng c hin th.
a vo b m hng theo trnh t 8 bit mt nh sau: (D25..D32), (D17..D24),
(D9..D16), (D1..D8), vi Dn l cho bit d liu cho ct n. D liu ca im no
phi c dch n ng v tr ca im y trc khi chng c cht n cc
chn A tng ng. Khi c nhiu module c ghp ni vi nhau th c th xem
tng ng hon ton vi mt module ln vi s im ca mt hng di hn,
v trnh t dch chuyn d liu vn tng t nh trn, ngha l d liu ca byte
cui hng s a vo trc v d liu byte u hng a vo sau cng. Xung
nhp INCLK c cp t bn ngoi vo c mi byte d liu ng thi, khi
ht d liu ri th xung nhp khng c php lm vic na.
hin th d liu ca hng u tin, s phi c mt xung dng OUTCLK
cht ton b d liu ca hng u tin m ang tn ti u vo b
CHOTHANG ra cc chn A ca LED matrix, v tn hiu H1ca u vo b m
cathode mc cao hin th ct u tin, cc u vo khc mc thp, b
m cathode ni t cho cathode ca hng u tin. Khi m cathode s
khuych i o tn hiu H1=1 v lm cho u ra K1 ni t, hng 1 c
hin th, cc hng cn li trng thi tr khng cao nn khng sng. Trng thi
ny c duy tr mt khong thi gian xc nh cc LED ca hng u tin
c hin th trong mt khong thi gian xc nh. Khi ht thi gian cho vic
hin th hng u tin u tin th vic hin th hng th hai s phi bt u.
41
Vic bt u cho hin th hng th 2 hon ton ging nh hng th nht, khi y
H1 tr v mc thp, H2 s chuyn ln mc cao, cn li cc u vo cn li
mc thp ht. Hng th hai cng s c hin th trong mt khong thi gian xc
nh v kt thc
Qu trnh c din ra lp li tng t i vi cc hng sau cho n ht hng16.
chu trnh qut mi s li bt u.
III.THC HNH
1.Kim tra LMD
-
8 LMD 2088BS c gn ln MATRIX1
a in p 0V vo chn K1 (dng kp hoc cm tay)

kp hoc cm bng tay)
quan st LMD s thy cc n hng 1 sng u ln lt t A1 n A32 l
hng cn li ca ton b LMD
2.Kim tra b m cc m ULN2803
-
IC ULN2803 gn trn cc khi U9, U10, U11, U12
Ni t cho bng, khng cp ngun.
Dng mt dy ngun 5V chm vo cht A1
Dng mt dy ngun 5V khc qut qua cc cht t H1 n H16,

khi qut quan st thy cc LED ca ct tng ng vi A1 sng u l U9,
U10 tt
-
Lm li nh trn vi A32 kim tra U11, U12.
3.Kho st hot ng ca module

-
Tt c cc IC c gn trn module
-
42

89s52
-
nu khng c g sai trn LMD s hin th ch nh lp trnh sn
dng my hin sng quan st tn hiu ti cc cht DATA, CLKIN,

CLKOUT, D, A, H, K thy r trnh t ca cc tn hiu iu khin v d
liu
43
BI 6: KHO ST MODULE HIN TH 16x32 IM HAI MU

I.MC CH
Tm hiu thit k ca module hin th 16x32 im hai mu, v phng php iu
khin.
II.THIT B S DNG
Nguyn l lm vic
LMD06 l m hnh ca mt module hin th, dng ghp ni nhiu module ny
vi nhau c mt kch thc hin th ln hn.
- Khi m hng: lm nhim v tip nhn d liu ca mt hng, bao gm 1
byte cho mu xanh xen k mt byte cho mu . Khi m hng gm cc IC
U21, U22, U23, U24, U25, U26, U27, U28. Mi IC l b 8 DFF c lp vi nhau
nhng dng chung u vo CLK, mi IC c 8 u vo D v 8 u ra Q. Bn IC
c mc lin tip vi nhau, 8 u ra ca IC U21 ni vi 8 u vo ca U22,
tng t n U27, U280 nh hnh v. u vo ca khi m hng l u vo ca
U21. D liu s c a vo khi m hng tng byte mt (8 bit ng thi) i
km vi mt xung CLKIN. Khi d liu c u vo DFF, mt xung dng
CLKIN s lm cho d liu chuyn n u ra v lu , u ra li c ni
n u vo ca DFF tip theo ng thi ni n u ra ca ton khi m hng.
Khi m hng c 8 u vo ni tip, 64 u ra dch chuyn, v 8 u ra lin tip
dnh cho vic ghp ni vi module tip theo. D liu c a vo 8 u vo ni
tip nhau 1 byte cho mu xanh v mt byte cho mu , tn hiu INCLK c
vo mi byte d liu, v dch chuyn trn 64 u ra. Hot ng ca khi tng t
nh thanh ghi dch. 8 bit d liu t vo u vo, 1 xung dng CLKIN s dch 8
bit n 8 u ra v ni n b 8 u vo tip theo, sau 8 ln dch th ta c
c 8 byte v c mt trn 642 u ra.
- Khi CHT HNG lm nhim v cht d liu ca mt hng u vo n
u ra v gi chng u ra trong thi gian hng hin th, bao gm cc IC
U13, U14, U15, U16, U17, U18, U19, U20.
- Khi ma trn n LED l mt ma n LED 16x32 im, mi im c 1 n
mu xanh v mt n mu , bao gm IC U1, U2, U3, U4, U5, U6, U7 v U8,
(xem trn s nguyn l v s mch in) mi mt khi U l mt ma trn 8x8
im 2 mu 2088DHG. Mt ct c 16 LED, 16 anode ca mt ct c ni
44
chung vi nhau thnh mt chn A chung. Mt hng c 32 LED, v chia lm hai

na, 16 cathode ca mi na ni vi nhau to nn mt chn K chung.
-
- Khi m Cathode: lm nhim v khuych i o tn hiu qut hng ht

dng cho cathode ca cc hng. u ra khi ny c ni n Cathode chung
ca cc hng (K). Khi ny s dng 4 IC 2803 gm U9, U10, U11 v U12, mi
ic c 8 cng ra, mi cng ra ni n mt chn K, mt chn K l ni chung ca 16
cathode ca mt na hng. U9, U10 dnh cho na tri t K1 n K16, U11 v 12
cho na phi t K17 n K32. Ton b khi ny co 32 cng ra chia cho cho na
45
l 16 cho bn phi, 16 cho bn trai, tng ng vi 16 hng cua ma trn LED.

Khi ny c 16 u vo, tng ng 16 hng. Mi u vo nhn tn hiu iu
khin ca mt hng, iu khin hai u ra cho hai na ca mt hng . Khi
ny n gin ch l khuych i o 16 tn hiu iu khin ni t cho hng v
tch hng thnh hai na cng sut iu khin.
Cc u vo:
- 16 tn u vo iu khin hng tng ng vi 16 hng ca ma trn LED
- 8 u vo d liu
- INCLK, tn hiu xung nhp cho d liu vo
- OUTCLK, tn hiu xung nhp cho d liu ra
Cc u ra:
- 16 tn u ra iu khin hng tng ng vi 16 hng ca module tip theo
- 8 u ra d liu, ni n 8 u vo d liu ca module tip theo
- INCLK, dng cho module tip theo
- OUTCLK, dng cho module tip theo
Cc u ra ca module ny s ni n u vo ca module tip theo khi ghp ni
nhiu module khc nhau
hin th ton b ma trn LED, 16 hng s ln lt c lun phin hin th t
hng1 n hng 16 tng ng l t K1v K2_1 n K16 v K2_16 ri lp li. Ti
mt thi im ch c mt hng c hin th.
a vo b m hng theo trnh t 8 bit mt nh sau: (D25..D32), (D17..D24),
(D9..D16), (D1..D8), vi Dn l cho bit d liu cho ct n. D liu ca im no
phi c dch n ng v tr ca im y trc khi chng c cht n cc
chn A tng ng. Khi c nhiu module c ghp ni vi nhau th c th xem
tng ng hon ton vi mt module ln vi s im ca mt hng di hn,
v trnh t dch dch chuyn d liu vn tng t nh trn, ngha l d liu ca
byte cui hng s a vo trc v d liu byte u hng a vo sau cng.
Xung nhp INCLK c cp t bn ngoi vo c mi byte d liu ng thi,
khi ht d liu ri th xung nhp khng c php lm vic na.
hin th d liu ca hng u tin, s phi c mt xung dng OUTCLK
cht ton b d liu ca hng u tin m ang tn ti u vo b
46
CHOTHANG ra cc chn A ca LED matrix, v tn hiu H1ca u vo b m

cathode mc cao hin th ct u tin, cc u vo khc mc thp, b
m cathode ni t cho cathode ca hng u tin. Khi m cathode s
khuych i o tn hiu H1=1 v lm cho u ra K1 ni t, hng 1 c
hin th, cc hng cn li trng thi tr khng cao nn khng sng. Trng thi
ny c duy tr mt khong thi gian xc nh cc LED ca hng u tin
c hin th trong mt khong thi gian xc nh. Khi ht thi gian cho vic
hin th hng u tin u tin th vic hin th hng th hai s phi bt u.
Vic bt u cho hin th hng th 2 hon ton ging nh hng th nht, khi y
H1 tr v mc thp, H2 s chuyn ln mc cao, cn li cc u vo cn li
mc thp ht. Hng th hai cng s c hin th trong mt khong thi gian xc
nh v kt thc
Qu trnh c din ra lp li tng t i vi cc hng sau cho n ht hng16.
chu trnh qut mi s li bt u.
III.THC HNH
1.Kim tra LMD
-
8 LMD 2088BS c gn ln MATRIX1
a in p 0V vo chn K1 (dng kp hoc cm tay)

kp hoc cm bng tay)
quan st LMD s thy cc n hng 1 sng u ln lt t A1 n A32 l
hng cn li ca ton b LMD
2.Kim tra b m cc m ULN2803
-
IC ULN2803 gn trn cc khi U9, U10, U11, U12
Ni t cho bng, khng cp ngun.
Dng mt dy ngun 5V chm vo cht A1
47
Dng mt dy ngun 5V khc qut qua cc cht t H1 n H16,

khi qut quan st thy cc LED ca ct tng ng vi A1 sng u l U9,
U10 tt
-
Lm li nh trn vi A32 kim tra U11, U12.
3.Kho st hot ng ca module

-
Tt c cc IC c gn trn module
-

89s52
-
nu khng c g sai trn LMD s hin th ch hnh mi tn
Dng my hin sng quan st tn hiu ti cc cht DATA, CLKIN,

CLKOUT, D, A, H, K thy r trnh t ca cc tn hiu iu khin v d
liu
48
BI 7: KHO ST HOT NG CA BNG TIN IN T

I. MC CH
Lm quen vi bng tin in t va, lm quen vi phn mm iu khin bng tin
in t t my tnh. Thc hnh cp nht ni dung, thay i font ch cho bn tin
in t bng phn mm trn my tnh.
II. THIT B S DNG
Module LMD07 (bng tin in t), my tnh c ci phn mm LMD Controller
III. THC HNH
1.Bt bng tin in t
Ngay khi va cm ngun bng tin s hin th ni dung lu t trc vi
hiu ng cun ngang. Ni hin th ny c lu t trc trong Flash ROM
ca b iu khin (do ln s dng trc ngi dng dng lnh Save), khi
mi cp ngun chng trnh s Load ni dung ny ln theo trnh t lm vic ca
phn mm v thc hin hiu ng cun ngang (Roll).
2.Khi ng phn mm iu khin
Sau khi kch p vo file LMDControl.exe bn s thy giao din chng trnh
nh sau:
49
T trn xung di giao din s dng ca phn mm gm nhng thnh phn sau:
- Ca s Preview: l ca s mu en xem bn tin hin trc khi cho hin
th trn bng in t
- Khung Display Option gm c: Nt lnh Font dng chn font ch, v
Message l nhp ni dung bn tin hin th. Nt lnh Font s cho php chn
Font, Size, Style ca bn tin s hin th trn bng tin in t
- Dimension Inf: l thng bo kt qu kch thc ca bn tin d inh
hin th, kch thc c tnh bng s im nh ca chiu cao v rng
- Khung Preview gm: Nt lnh Capture l lnh thc hin chuyn on vn
bn thnh bc nh vi cc im nh n gin (ch c mu v mu en).
Nt lnh Preview l lnh xem trc bn tin trn my trc khi cho hin th
trn bng tin in t. Top Cutting ct i phn trn ca bc nh bng s
dng im nh hin ti ca . Bottom Cutting ct i phn di ca bc
nh theo s dng im nh hin ti ca . Threshold dng t ngng
cho chuyn i mt im nh nhiu mc thnh mt im nh n gin (0
hoc 1).
- Nt lnh Bit2Byte: mng bt cc im nh n gin thnh mng byte, thc
cht l ghp 8 bit thnh mt byte truyn i qua cng COM my tnh theo
tng byte
- Nt lnh Out Array: l lnh Truyn Mng cc Byte xung bng tin in
t, lnh ny truyn mng byte l kt qu chuyn i v m ha bn tin vi
nh dng yu cu trc xung bng tin in t v yu cu bng tin in t
hin th c nh ni dung ca bn tin ny (khng thc hin hiu ng g)
-
Nt lnh Roll
Stop dng hiu ng
Save lu trng thi hin ti vo ROM
Load np li ni dung lu
3.Thay i ni dung, lu ni dung cho bng tin

thay i ni dung lm nh sau:
- Sau khi khi ng ng phn mm, message c ni dung l Hello!
LMD kch chut vo message g ni dung cn hin th (khng c b
qua, bt buc phi g g d mt du cch ri li xa i)
50
- Kch vo Capture, Preview, ca s Preview s hin th nh hnh di vi

thng tin v kch thc nh
- Ni dy truyn thng RS232 ca bng tin in t vi cng COM ca my

tnh
-
Kch Bit2Byte, Out Array, Bng in t s hin th ni dung nh Preview
Kch Roll, thc hin hiu ng cun ngang
Kch Stop thc hin dng hiu ng
- Kch Save lu trng thi hin ti ca bng vo ROM (trng thi ny s

c gi li trong ROM ngay c khi mt in)
-
Kch Load ly li trng thi ghi vo ROM trc
thay i Font lm nh sau:

-
Kch vo Font s xut hin ca s nh hnh di y:
51
- Chn Font, Font style, Size thay i font, kiu cch, v c ch nh

mong mun, sau chn OK
- Kch Capture, Preview, xem li kt qu chnh sa v thng bo v kch
thc trong Dimension Inf
-
hin th kt qu mi chn Bit2byte, Out Array
- Nu sau khi capture thng bo kch thc nh ln hn kch thc bng tin
hin c th ni dung hin th s b mt i phn trn ca bc nh xem trong
Preview
- Dng cc iu chnh Top cutting, v Bottom Cutting ct nh phn trn
v di ca bc nh
- Kch Capture xem thng bo v kch thc nh sau mi ln chnh sa,
lu kch thc tht ca bng hin c l cao 16 im v c th hin th bn
tin rng 256 im, mt kch thc nh rng hn s hin th b mt i phn
trn v phn bn phi.
-
Kch Preview xem qua
Ch sau mi ln chnh sa ni dung phi kch vo Capture c ni dung mi,

chn Preview xem li ni dung mi, chn Bit2Byte v Out Array truyn
bn tin ra bng in t
52
Ph Lc
M ngun chng trnh
Bi 1:
/* Chuong trinh mau LMD1
NTL viet tren Keil C
*/
#include <reg51.h>
sbit clkIN
= 0xB3;//tao xung dich vao bo dem ghi dich
sbit DuLieu = 0x97;

sbit clkOUT = 0xB4;//tao xung xuat ra dong thoi cua cac bo dem
sbit DongBo = 0xB5;//tao xung dong bo hang dau tien, chan nay noi toi dau vao
bo ghi dich quet hang
void main (void){
char data X[8] = {0xC0,0xD2,0xDA,0xD6,0xD2,0xC0,0xFC,0xFC};//
Ch L v n
char TrungGian;
int i,j;
P1 = 0;
while (1){
DongBo = 1;
for (i = 0; i <= 7; i++ ) {
TrungGian = X[i];
for (j=0; j<=7; j++) {
DuLieu = TrungGian%2; //phat bit LSB
TrungGian = TrungGian/2; //dich phai
clkIN = 1; //tao mot xung vuong kich vao bo dem ghi
dich
53
clkIN = 0;
}
clkOUT = 1; //tao mot xung vuong de bo dem xuat ra dong
thoi mot hang
clkOUT = 0; //dich xung dong bo hang xuong hang tiep theo
DongBo = 0; //tat xung dong bo o cac hang sau
}
}
}
Bi 2:
/*chuong trinh thu nghiem LMD2
-----------------------------dung hai ngat ngoai de dieu khien thay doi du lieu trong mang hien thi.
khi co ngat o chan 12 hien thi chu A
khi co ngat o chan 13 hien thi chu Z
mang char dc khai bao o ngoai
-------------------------Viet tren Keil C
NTL
*/
#include <reg51.h>
sbit clkIN
sbit DuLieu = 0x97;

sbit Ngat
= 0xAF; //EA
sbit Ngatchan12
= 0xA8; //EX0
54
sbit Ngatchan13
= 0xAA; //EX1
char data X[8] = {0x41,0x63,0x36,0x1c,0x1c,0x36,0x63,0x41}; //du lieu hien thi

/*--------------------------------------------------------------------*/
#pragma NOAREGS // ko su dung cac ky hieu thanh ghi tuyet doi cho cac
// ham duoc goi tu dich vu ngat
static void XuLiNgatChan12 (void) { //chuyen du lieu thanh chu A
X[0] = 0x10; //nap du lieu chu A cho bang X
X[1] = 0x38;
X[2] = 0x6c;
X[3] = 0xc6;
X[4] = 0xfe;
X[5] = 0xc6;
X[6] = 0xc6;
X[7] = 0xc6;
}
static void XuLiNgatChan13 (void) { //chuyen du lieu thanh chu Z
X[0] = 0x7f; //nap du lieu chu Z cho bang X
X[1] = 0x7f;
X[2] = 0x06;
X[3] = 0x0c;
X[4] = 0x18;
X[5] = 0x30;
X[6] = 0x7f;
X[7] = 0x7f;
}
#pragma AREGS
/*--------------------------------------------------------------------*/
55
void ngatchan12 (void) interrupt 0 using 1{

XuLiNgatChan12 (); //hien thi chi A
}
void ngatchan13 (void) interrupt 2 using 1{
XuLiNgatChan13 (); //hien thi chi Z
}
/*--------------------------------------------------------------------*/
void main (void){
char TrungGian;
int i,j;
Ngat = 1;
//cho phep ngat toan cuc
Ngatchan12 = 1;//cho phep ngat chan 12

Ngatchan13 = 1;//cho phep ngat chan 13
P1 = 0;
while (1){
DongBo = 1;
for (i = 7; i >= 0; i-- ) {
TrungGian = X[i];
for (j=0; j<=7; j++){
dich
clkIN = 0;
}
thoi mot hang
56

}
}
}
Bi 3:
---------------------------------hien thi chu A
----------------------------------NTL
*/
#include <reg51.h>
//cac chan tin hieu dieu khien
sbit clkIN
sbit DuLieu = 0x97;

//cac bit cho phep ngat
sbit Ngat
= 0xAF; //EA
sbit Ngatchan12
= 0xA8; //EX0
sbit Ngatchan13
= 0xAA; //EX1
sbit NgatDinhthoi0 = 0xA9;

// bang du lieu khoi tao
57
//day la bang du lieu toan cuc

char data X[24] = { 0xFF,0xEF,0xD7,
0xBB,0x83,0xBB,
0xBB,0xFF,0xFF,
0xFF,0xFF,0xFF,
0xFF,0xFF,0xFF,
0xFF,0xFF,0xFF,
0xFF,0xFF,0xFF,
0xFF,0xFF,0xFF
};
int hang,cot;
bit msb,lsb;
void main (void){
char TrungGian;
int i,j;
hang = 0;
cot = 2;
P1 = 0;
while (1)
{
DongBo = 1;
for (i = 0; i <= 23; i++ ) {
TrungGian = X[i];
for (j=0; j<=7; j++) {
58
clkIN = 1; //tao mot xung vuong kich vao dem ghi dich
clkIN = 0;
}
thoi mot hang
}
}
}
Bi 4:
*/
#include <reg51.h>
sbit clkIN
= 0xB3;
sbit DuLieu = 0x97;

sbit clkOUT = 0xB4;
sbit DongBo = 0xB5;
//day la bang du lieu toan cuc
char data X[64] = { 0x00,0x00,0x00,0x00,
0x00,0x01,0x00,0x00,
0x80,0x01,0x00,0x00,
0xc0,0x01,0x00,0x00,
59
0xe0,0x01,0x00,0x00,
0xb0,0xff,0xff,0x3f,
0x98,0xff,0xff,0x3f,
0x0c,0x00,0x00,0x30,
0x0c,0x00,0x00,0x30,
0xe0,0x01,0x00,0x00,
0xc0,0x01,0x00,0x00,
0x80,0x01,0x00,0x00,
0x00,0x01,0x00,0x00,
0x00,0x00,0x00,0x00
};
/*--------------------------------------------------------------------*/
/*sau day la chuong trinh chinh
1. NHIEM VU:
- khai bao, khoi tao
khoi tao mang hien thi
khoi tao cac biet dieu khien chi so mang de phuc vu xuat mang
khoi tao tin hieu dieu khien
- dieu khien xuat mang theo vong lap vo han
2. GIAI THUAT
3. Danh sach cac bien, du lieu tac dong
- du lieu toan cuc
+ mang du lieu hien thi: X
+ Cac chan tin hieu dieu khien
port1: Dulieu
chan dieu khien xung dich vao bo dem: clkIN
chan dieu khien xung dich ra bo dem: clkOUT
chan tao xung dong bo hang dau tien: DongBo
- Du lieu cuc bo
60
Bien trung gian xac dinh tri so mang: chiso

bien dung de dem so byte trong 1 hang, dung cho viec phat 1 hang: k
bien dung de dem so hang trong anh, dung cho viec phat 1 hang: i
*/
void main (void){
int i,k,chiso;
while (1){
DongBo = 1;
for (i = 0; i <= 15; i++ ) {
for (k=0; k<=3; k++) {
chiso = i*4 + k;
DuLieu = X[chiso];
dich
clkIN = 0;
}
thoi mot hang
}
}
}
Bi 5:
/*chuong trinh thu nghiem LMD5 --- "CHAY TOT !!!"
dieu khien mach quet LED co so do phan cung nhu ...
dieu khien quet LED bang ngat dinh thoi
61
moi khi say ra ngat dinh thoi 0 chuong trinh se xuat ra mot hang dua vao bien
ChiSo
va chot giu. cu the viec do la
- xuat ra lien tuc cac byte cua hang do xe ke xung clkIN
- sau khi xuat het cac byte thi xuat ra mot xung clkOUT
ChiSo la bien toan cuc dc khoi tao do chuong trinh chinh
neu ChiSo bang 0, tuc la hang dau tien dc xuat, khi ay xuat ra DongBo = 1
neu ChiSo khac 0 thi xuat ra mot ra DongBo = 0
sau khi xuat het so byte kiem tra neu ChiSo = 63 thi dua tro ve 0
cong P1 xuat ra song song DuLieu
cac chan 21, 22, 23 (p20, p21, p22) dieu khien clkIN, clkOUT, DongBo
*/
#include <reg51.h>
sfr DuLieu = 0x90; //chan 1,2,3,4,5,6,7,8 cong P1 cua 8951 duong dl song
song noi den dau vao bo dem ghi dich
sbit clkIN
= 0xA0; //chan 21 8951 tao xung dich vao bo dem ghi dich
sbit clkOUT = 0xA1; //chan 22 8951 tao xung xuat ra dong thoi cua bo dem
sbit DongBo = 0xA2; //chan 23 8951 tao xung dong bo hang dau tien, chan nay
noi toi dau vao bo ghi dich quet hang
//cac thanh ghi va bit chuc nang dac biet
sfr CheDoDinhThoi = 0x89;
sfr ByteThapDinhThoi0 = 0x8A;
sfr ByteCaoDinhThoi0 = 0x8C;
sbit BatDinhThoi0 = 0x8C;
sbit Ngat
= 0xAF; //EA
62
//DINH NGHIA CAC THAM SO KICH THUOC BANG, THOI GIAN QUET
#define BeRong 4
//so byte cua mot hang
#define ChieuCao 16
#define SoByteMang 64
//so hang
//so byte cua mang hien thi X
#define SoLanNgat 5
//so lan say ra ngat dinh thoi
#define SoDemDinhThoi 256
//so xung nhip dinh thoi can dem

// 16 11 1985
char data X[SoByteMang] = {
0x00,0x00,0x00,0x00,
0x00,0x00,0x06,0x00,
0x00,0x00,0x49,0x00,
0xFF,0xFF,0x49,0xFF,
0x40,0x40,0x49,0x40,
0x20,0x20,0x25,0x20,
0x00,0x00,0x1E,0x00,
0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,
0x8c,0x6E,0x7C,0x00,
0x92,0x91,0xA2,0x00,
0xA1,0x91,0x91,0xFF,
0xA1,0x91,0x91,0x40,
0xA1,0x91,0x91,0x20,
0x72,0x6E,0x62,0x00,
0x00,0x00,0x00,0x00
};
/*--------------------------------------------------------------------*/
int ChiSo,n;//chi so mang va bien n de dem so lan say ra ngat
/*--------------------------------------------------------------------*/
63

/*----------------------------------*/
static void XuLiNgatDinhThoi0 (void) //xuat ra mot hang thu x
/*day la chuong chinh con phuc vu ngat dinh thoi 0
nhiem vu cua chuong trinh con nay la:
- dem so lan say ra ngat dinh thoi qua bien n
- khi n < 100 thi tang len 1 ket thuc
- khi n = 100 thi xuat ra hang ket thuc
viec xuat ra mot hang dua vao bien ChiSo.
bien ChiSo ban dau dc main gan la 0, la chi so cua byte dau hang
+ kietm tra neu la hang dau tien (n==0) thi DongBo=0, nguoc lai =1
+ su dung vong lap voi so vong la so byte cua hang
moi chu trinh lap se xuat ra mot byte, va clkIN, tang ChiSo
+ ket thuc vong lap thi xuat ra mot xung chot clkOUT, va chi so da tro den hang
tiep theo
+ kiem tra neu xuat het mang (chiso=SoByteMang) thi gan lai chiso=0
*/
{
int k; //bien dem so byte trong mot hang
if (n==SoLanNgat) //neu ngat SoLanNgat lan thi
{
n=0;
//dem lai tu 0 voi lan sau
if (ChiSo==0)
{DongBo = 1;}//DongBo=1 o hang dau tien
else
{DongBo = 0;}//
for (k=1; k<=BeRong; k++)
=0 cac hang sau
//va xuat ra mot hang
{
DuLieu = X[ChiSo];
clkIN = 1;
//tao mot xung vuong kich vao bo dem ghi
dich
clkIN = 0;
ChiSo++;
//tang chi so len 1,
64
//ket thuc for chi so se tang len 4
clkOUT = 1; //tao mot xung vuong de bo dem xuat ra dong thoi

mot hang
if (ChiSo > (SoByteMang-1)) {ChiSo=0;}
}
else
//neu n < 100 thi
{
n++;//tiep tuc dem so lan ngat
}
}
#pragma AREGS
/*--------------------------------------------------------------------*/
void NgatDinhThoi0 (void) interrupt 1 using 1
{
XuLiNgatDinhThoi0 (); //dich 1 cot tu trai qua phai
}
/*--------------------------------------------------------------------*/
1. NHIEM VU:
+ khoi tao cac gia tri bien:
khoi tao bien dieu khien chi so mang ChiSo de phuc vu xuat mang
khoi tao bien dem n de tinh toc do ngat
+ thiet lap cac che do ngat va dinh thoi
cho phep ngat toan cuc
cho phep ngat dinh thoi
2. GIAI THUAT
Bit cho phep ngat toan cuc: Ngat
Bit cho phep ngat dinh thoi 0: Ngatdinhthoi0
65

Bien dem so lan say ra ngat: n
Gia tri thanh ghi dinh thoi
*/
void main (void){
//khoi tao
ChiSo = 0;
//khoi tao chi so cua mang
n = 0;
//khoi tao bien dem so lan ngat
//thiet lamp che do cho dinh thoi

CheDoDinhThoi = (CheDoDinhThoi & 0xf0) | 0x02;
// thiet lap che do tu dong lap lai 8 bit cho T0
ByteCaoDinhThoi0 = 256 - SoDemDinhThoi;
// nap lai cho TL0 de dem SoDemDinhThoi xung nhip he thong
ByteThapDinhThoi0 = ByteCaoDinhThoi0;
//khoi dong he thong
Ngat = 1;
NgatDinhthoi0 = 1;//cho phep ngat dinh thoi 0

BatDinhThoi0 = 1; // khoi dong dinh thoi 0
//doi
while (1);
}
Bi 6:
/*chuong trinh thu nghiem LMD6 --- "CHAY TOT !!!"
dieu khien mach quet LED co so do phan cung nhu ...
dieu khien quet LED bang ngat dinh thoi
tao hieu ung dich chuyen ngang
moi khi say ra ngat dinh thoi 0 chuong trinh se xuat ra mot hang dua vao bien
ChiSo
va chot giu. cu the viec do la
66
- xuat ra lien tuc cac byte cua hang do xe ke xung clkIN

- sau khi xuat het cac byte thi xuat ra mot xung clkOUT
ChiSo la bien toan cuc dc khoi tao do chuong trinh chinh
neu ChiSo bang 0, tuc la hang dau tien dc xuat, khi ay xuat ra DongBo = 1
neu ChiSo khac 0 thi xuat ra mot ra DongBo = 0
sau khi xuat het so byte kiem tra neu ChiSo = 63 thi dua tro ve 0
cong P1 xuat ra song song DuLieu
*/
#include <reg51.h>
sbit clkIN
sfr DuLieu
= 0x90;
//cac thanh ghi va bit chuc nang dac biet

sfr CheDoDinhThoi = 0x89;
sfr ByteThapDinhThoi0 = 0x8A;
sfr ByteCaoDinhThoi0 = 0x8C;
sbit BatDinhThoi0 = 0x8C;
sbit Ngat
= 0xAF;

//DINH NGHIA CAC THAM SO KICH THUOC BANG, THOI GIAN QUET
#define BeRong 4
//so byte cua mot hang
67
#define ChieuCao 16
//so hang
#define SoByteMang 64
//BeRong * ChieuCao = so byte cua mang hien thi X
#define NgatDu 5
//so lan say ra ngat dinh thoi
#define SoDemDinhThoi 256
//so xung nhip dinh thoi can dem

char code KhoiTao[SoByteMang] ={0x00,0x00,0x00,0x00,
0x00,0x01,0x00,0x00,
0x80,0x01,0x00,0x00,
0xc0,0x01,0x00,0x00,
0xe0,0x01,0x00,0x00,
0x0c,0x00,0x00,0x30,
0x0c,0x00,0x00,0x30,
0xe0,0x01,0x00,0x00,
0xc0,0x01,0x00,0x00,
0x80,0x01,0x00,0x00,
0x00,0x01,0x00,0x00,
0x00,0x00,0x00,0x00
};
char idata X[SoByteMang];
68
char bdata ThanhGhiTrungGian; //day la thanh ghi trung gian truy cap bit
sbit BitThapNhat= ThanhGhiTrungGian ^ 0;
sbit BitCaoNhat = ThanhGhiTrungGian ^ 7;
bit BitRa;//bit chua bit di ra tu bit dau hang
bit BitVao;//bit chua bit di Vao cuoi hang
/*--------------------------------------------------------------------*/
int ChiSo,DemSoLanNgatT0;//chi so mang va bien n de dem so lan say ra ngat
int SoDongDaXuat;
/*--------------------------------------------------------------------*/
/*----------------------------------*/
static void XuLiNgatDinhThoi0 (void) //xuat ra mot hang thu x
/*day la chuong chinh con phuc vu ngat dinh thoi 0
nhiem vu cua chuong trinh con nay la:
- dem so lan say ra ngat dinh thoi qua bien n
- khi n < SoLanNgat thi tang len 1 ket thuc
- khi n = SoLanNgat thi xuat ra hang ket thuc
viec xuat ra mot hang dua vao bien ChiSo.
bien ChiSo ban dau dc main gan la 0, la chi so cua byte dau hang
+ kietm tra neu la hang dau tien (n==0) thi DongBo=0, nguoc lai =1
+ su dung vong lap voi so vong la so byte cua hang
moi chu trinh lap se xuat ra mot byte, va clkIN, tang ChiSo
+ ket thuc vong lap thi xuat ra mot xung chot clkOUT, va chi so da tro den hang
tiep theo
+ kiem tra neu xuat het mang (chiso=SoByteMang) thi gan lai chiso=0
*/
{
int k; //bien dem so byte trong mot hang
if (++DemSoLanNgatT0==NgatDu)
//neu ngat SoLanNgat lan thi
69
DemSoLanNgatT0=0;
//dem lai tu 0 voi lan sau
SoDongDaXuat++;
if (ChiSo==0)
{DongBo = 1;}//DongBo=1 o hang dau tien
else
{DongBo = 0;}//
for (k=1; k<=BeRong; k++)
=0 cac hang sau
//va xuat ra mot hang
{
DuLieu = X[ChiSo];
clkIN = 1;
//tao mot xung vuong kich vao bo dem ghi
dich
clkIN = 0;
ChiSo++;
}
//tang chi so len 1,

//ket thuc for chi so se tang len 4
clkOUT = 1; //tao mot xung vuong de bo dem xuat ra dong thoi

mot hang
if (ChiSo > (SoByteMang-1)) {ChiSo=0;}
}
}
#pragma AREGS
/*--------------------------------------------------------------------*/
void NgatDinhThoi0 (void) interrupt 1 using 1
{
XuLiNgatDinhThoi0 (); //dich 1 cot tu trai qua phai
}
/*--------------------------------------------------------------------*/
void Quay1DiemCho1Hang (int SoHang)//so hang bat dau tu 1 den 16
/*day la thu tuc dich chuyen mot hang
thu tuc nay se lam cho mot hang quay di mot cot theo giai thuat sau:
- ve dau hang
- chep bit dau hang
70
- thuc hien vong lap quay cac byte tu cuoi

hang den dau hang co kem theo bit dau hang
+ chep byte vao ThanhGhiTrungGian
+ dich trai (*2)
+ BitVao->BitThapNhat
+ BitRa ->BitVao
+ nhay den byte tiep theo thuc hien tiep chu trinh
*/
{
int SoByte;
ThanhGhiTrungGian = X[SoHang*BeRong - 1];
hang vao ThanhGhiTrungGian
BitVao = BitCaoNhat;
BitTrungGian
//chep Byte dau
//chep bit dau hang vao
for (SoByte=0; SoByte<BeRong; SoByte++)//thuc hien vong lap quay cac

byte tu cuoi
{
bit dau hang
//hang den dau hang co kem theo

ThanhGhiTrungGian = X[(SoHang-1)*BeRong + SoByte];//chep
byte dang tro

BitRa = BitCaoNhat;
//chep bit Cao nhat truoc khi
dich
ThanhGhiTrungGian *=2; //dich trai
if (BitVao) {ThanhGhiTrungGian++;}
BitVao = BitRa;
X[(SoHang-1)*BeRong + SoByte] = ThanhGhiTrungGian;
}
}
/*--------------------------------------------------------------------*/
1. NHIEM VU:
71
+ khoi tao cac gia tri bien:

khoi tao bien dieu khien chi so mang ChiSo de phuc vu xuat mang
khoi tao bien dem n de tinh toc do ngat
+ thiet lap cac che do ngat va dinh thoi
cho phep ngat toan cuc
cho phep ngat dinh thoi
2. GIAI THUAT
Bit cho phep ngat toan cuc: Ngat
Bit cho phep ngat dinh thoi 0: Ngatdinhthoi0
Bien dem so lan say ra ngat: n
Gia tri thanh ghi dinh thoi
*/
void main (void)
{
int Hang;//bien mang mang chi so hang
//khoi tao
SoDongDaXuat=0;
ThanhGhiTrungGian = 0;
ChiSo = 0;
//khoi tao chi so cua mang
DemSoLanNgatT0 = 0;
//khoi tao bien dem so lan ngat
for (Hang=0; Hang<=SoByteMang; Hang++)//nap du lieu khoi tao

{X[Hang] = KhoiTao[Hang];}
//thiet lamp che do cho dinh thoi
CheDoDinhThoi = (CheDoDinhThoi & 0xf0) | 0x02; // thiet lap che do
tu dong lap lai 8 bit cho T0
ByteCaoDinhThoi0 = 256 - SoDemDinhThoi;
de dem SoDemDinhThoi xung nhip he thong
// nap lai cho TL0
ByteThapDinhThoi0 = ByteCaoDinhThoi0;
72
//khoi dong he thong

Ngat = 1;
NgatDinhthoi0 = 1;//cho phep ngat dinh thoi 0

BatDinhThoi0 = 1; // khoi dong dinh thoi 0
//vong lap thuc hien hieu ung dich chuyen
while (1)
{
if (SoDongDaXuat==48) //neu da dc 48 dong
{
SoDongDaXuat=0; //xoa
for ( Hang=1; Hang<=16; Hang++) //dich ca hinh di 1 cot
{Quay1DiemCho1Hang(Hang);}
};
};
}
TI LIU THC HNH PIC

73
MC LC
I. GII THIU H THNG.......................................................................................77

II. M T CC THNH PHN CA H THNG................................................79
1. DIP SWITCH (DIPSW)......................................................................................79
2. JUMPERs............................................................................................................80
3. MCU SOCKETs..................................................................................................80
4. POWER SUPPLY...............................................................................................83
5. ON-BOARD PROGRAMMER..........................................................................83
6. REAL TIME CLOCK (RTC) DS1307................................................................84
7. RS-232 COMMUNICATION ............................................................................85
8. USB COMMUNICATION..................................................................................86
9. PS/2 COMMUNICATION..................................................................................87
10. DS1820 DIGITAL THERMOMETER.............................................................88
11. A-D CONVERTER INPUT..............................................................................89
12. DIRECT PORT ACCESS.................................................................................90
PHN II: THC HNH.................................................................................................92
Bi thc hnh s 1.......................................................................................................92
S DNG PHN MM WINPIC800 .......................................................................92
TRUY CP CNG VO RA S V IU KHIN LED 7 DON........................92
I. MC CH..........................................................................................................92
II. CHUN B.........................................................................................................92
III. THC HNH....................................................................................................92
Bi thc hnh s 2.....................................................................................................101
BIN I ADC, O IN P, NHIT ...........................................................101
HIN TH TRN LED V TRUYN THNG QUA RS232.................................101
I. MC CH........................................................................................................101
II. CHUN B.......................................................................................................101
III. THC HNH..................................................................................................101
Bi thc hnh s 3.....................................................................................................105
C PHM BM, IU KHIN RELAY .............................................................105
V C THI GIAN THC DS1307 HIN TH TRN LEB 7 ON..............105
I. MC CH........................................................................................................105
II. CHUN B.......................................................................................................105
III. THC HNH..................................................................................................106
PH LC......................................................................................................................112
Phn I: L thuyt chung v CPLD v VHDL................................................................146
Gii thiu.......................................................................................................................146
I. L thuyt chung v CPLD..........................................................................................147
1. Gii thiu chung....................................................................................................147
1.1. Lch s Logic kh trnh...................................................................................147
1.2. Thit b logic kh trnh phc tp CPLD.........................................................149
1.3. Mng cng Logic kh trnh min FPGA........................................................152
1.4. Hp nht cng ngh Logic.............................................................................154
2. Cc gii php cng ngh ca Xilinx......................................................................154
2.1. Gii thiu........................................................................................................154
74
2.2. Cc thit b ca Xilinx....................................................................................155

2.3. CPLD Xilinx...................................................................................................155
II. L thuyt chung v VHDL.......................................................................................162
1. Cc phng php thit k s truyn thng............................................................163
1.1. Phng php thit k dng hm Boolean.......................................................163
1.2. Phng php thit k da trn s (L s m rng ca phng php thit k
dng hm Boolean)................................................................................................163
1.3. Nhc im ca cc phng php thit k truyn thng...............................164
2. Phng php thit k s bng ngn ng m t phn cng....................................164
3. Cc qu trnh thc hin thit k s bng HDL trn FPGA....................................166
4. Ngn ng m t phn cng VHDL.......................................................................171
4.1. Gii thiu........................................................................................................171
4.2. Cu trc mt m hnh h thng m t bng VHDL.......................................173
Phn II: Thc hnh........................................................................................................177
Bi 1: Lm quen vi phng php thit k s bng VHDL trn phn mm ISE ca
Xilinx.............................................................................................................................177
1. Mc ch................................................................................................................177
2. Thit b s dng.....................................................................................................177
3. Ni dung thc hnh...............................................................................................177
3.1. To d n mi.................................................................................................177
3.2. Bin son HDL...............................................................................................181
3.3. Bin son lu trng thi.............................................................................186
3.4. Thit k VHDL mc nh...............................................................................193
3.5. Thit k s nguyn l mc nh.................................................................203
4. Cc bi thc hnh nng cao...................................................................................212
Bi 2: Tm hiu v cu trc phn cng X-Board...........................................................213
1. Mc ch................................................................................................................213
2. Thit b s dng.....................................................................................................213
3. Ni dung thc hnh...............................................................................................213
4. Yu cu sau bui thc hnh...................................................................................219
Bi 3: Thc hnh vi Project mu trn X-Board...........................................................220
1. Mc ch................................................................................................................220
2. Thit b thc hnh..................................................................................................220
75
PHN I: M T THIT B
I. GII THIU H THNG
H THNG O TO PIC (PIC.TS) l board mch y cc cng c cho
vic hc tp v nghin cu vi iu khin PIC ca Microchip. Sinh vin d dng
thc hnh, kim tra v nh gi kh nng ca vi iu khin PIC. PIC.TS cho
php PIC giao tip vi mt s lng ln cc thit b ngoi vi v mch ngoi. Vi
PIC.TS, sinh vin khng cn lo lng v phn cng m ch cn tp trung vo vic
pht trin phn mm. Trn PIC.TS, mi thnh phn c in thng trn board
mch rt r rng nh du s m t kt ni n cc thit b cng mt vi ghi ch
hu ch.
Hnh 1.1 - PIC.TS
76
Hnh 1.2 - S nguyn l PIC.TS

77
II. M T CC THNH PHN CA H THNG

1. DIP SWITCH (DIPSW)
PIC.TS c c tnh l kt ni vi nhiu thit v ngoi vi. kt ni nhng thit b
ny trc khi lp trnh, cn phi kim tra v thit t ca cc jumper v DIPSW.
DIPSW l linh kin tp hp nhiu switch c 2 v tr ON v OFF dng ni hoc
ngt gia 2 chn vi nhau. PIC.TS c 2 DIPSW.
DIPSW1 cho php kt ni gia cc port ca PIC (PORTA v PORTE) vi in
tr pull-up/down bn ngoi. Cc in tr pull-up/down phi c tch ri ra khi
cc chn ca cc port ny dng lm ng vo Analog v lm nh hng n mc
in p u vo. Khi cc chn ca PORTA v PORTE s dng nh digital
inputs/outputs th nhng in tr pull-up/down li thch hp v c cho php.
Su switches u ca DIPSW2 cho php kt ni ti PortA iu khin 6 LED 7
on (7-Segment display). Nu khng cn 7-seg Display trong bi tp th cc SW
ny cn phi OFF.
Hai switches u ca SW2 cho php kt ni DS1307 n chn RC4 v RC3 ca
PIC. Khi khng c nhu cu s dng DS1307 th nn a cc SW ny v v tr
OFF.
Hnh 1.3 - Dip switch
78
2. JUMPERs
Jumpers cng ging nh switches, c th ngt hoc ni hai im vi nhau. Bn
trong v bc nha ca jumper l mt l kim loi dng tip xc. N s ni (dn
in) nu jumper ny c gn vo hai pin ang b ngt.
V d: Hai bin tr trong mch ADC c ngt ri vi RA2 v RA3. ni
chng vi nhau cn s dng jumper.
Hnh 1.4 - Jumper nh mt Switch

Cc jumper cng thng c s dng la chn gia hai kt ni. Nh minh
ha trong hnh di, im gia c ni vi bn phi hoc bn tri tu thuc vo
v tr ca jumper.
Hnh 1.5 La chn kt ni vi jumper

3. MCU SOCKETs
PIC.TS c thit k s dng cho cc loi vi iu khin PIC 16F v 18F. Ngi
s dng c th dng cc PIC khc nhau thch hp cho cng vic ca mnh c cc
kiu chn ph hp vi socket DIP40, DIP28, DIP18.
79
Hnh 1.6 - MCU socket

Ch : Tt c cc sockets trn c ni song song vi nhau, v vy trong
cng mt thi im bn ch c th s dng c mt vi iu khin PIC m thi.
Chn MCU c s dng ni n nhiu thit b ngoi vi nh c minh ho
trong Hnh 1.8. Do tt c cc port u kt ni trc tip n nhng u ni 5x2.
Nhng u ni nh vy cho php m rng kt ni n cc thit b ngoi vi bn
ngoi hoc hu ch cho vic kt ni vi cc u d digital logic.
Tt c cc ports u c ni n in tr pull-ip/down v c nh s ghi ch
rt chi tit d dng cho vic kim tra v o th.
Mt vi chn c kt ni ti cc thit b ngoi vi khc nh DS1820 temperature
sensor, RS-232 communication, 7-segment displays, LCD.
80
Hnh 1.8 - S kt ni h thng

PIC.TS c mt nt bm s dng cho mc ch RESET, s mch RESET
c nhn thy trong hnh di.
Hnh 1.9 S mch reset
81
4. POWER SUPPLY
h thng lm vic cn phi cp ngun. PIC.TS c th hoch ng bng ngun
ngoi hoc c cung cp qua cable USB.
Trong trng hp cp ngun qua USB, h thng phi c ni vi PC bng
cable USB v cng tc ngun phi c gt v pha USB. Lu l vic cp
ngun qua USB ch s dng khi chy th chng trnh. Khi np chng trnh cho
chip bn phi s dng ngun ngoi. Khi s dng ngun ngoi, PIC.TS s to ra in
p +5V cp cho h thng v in p +13V dng lm in p lp trnh chip.
Power supply connector
Power supply swiches
Hnh 1.10 La chn ngun cung cp

5. ON-BOARD PROGRAMMER
Khng cn s dng bt k mch np no khc, PIC.TS c ring mt mch np
on-board rt tin li v d s dng. Bn ch cn cm cp kt ni n PC qua cng
LPT.
82
Mch np cho PIC trn PIC.TS
Cp kt ni
Hnh 1.11 Mch np

y l mch np giao tip qua cng my in s dng phn mm WinPIC800 c
n nh cao, tc nhanh, h tr rt nhiu PIC.
6. REAL TIME CLOCK (RTC) DS1307
PIC.TS s dng ng h thi gian thc DS1307 giao tip chun I2C vi vi iu
khin PIC. Hai chn SCL v SDA ni vi RC3 v RC4 qua SW2. Pin CMOS
dng nui DS1307 khi ngt ngun.
RTC DS1307
Pin Cmos
83
Hnh 1.12 S kt ni DS1307

7. RS-232 COMMUNICATION
Truyn thng RS-232 cho php truyn d liu im ti im. RS232 thng
c dng trong cc ng dng giao tip truyn thng gia gia vi iu khin v
my tnh. Mc in p gia vi iu
khin v my tnh khng thch hp nhau.
Do vy b m Max-232 c s dng.
s dng linh hot hn, trn PIC.TS vi
iu khin c ni ti Max232 qua cp
jumper JP_TX v JP_TD. Jumper
JP_RX c s dng ni ti ng
Rx ti RC7, RB2 hoc RB1. Jumper
JP_TX c s dng ni ti ng
RS-232 communiction
84
Tx ti RC6, RB5 hoc RB2. Ch : JP5 v JP6 khng c ni cng lc n

RB2.
Hnh 1.13 - Kt ni PIC vi my tnh

8. USB COMMUNICATION
PIC.TS c mt cng USB. N c s
dng cho nhng loi vi iu khin PIC c
h tr giao tio USB nh 18F2450,
18F2550, 18F4550 ngoi kh nng giao
tip USB n cn l b phn cp ngun 5V
cho ch chy th (khng s dng c
ngun USB ch np).
kt ni gia vi iu khin v socket
USB cn phi ni c 3 jumpers JP17, JP18
v JP19 ln pha trn. Kt qu l vi iu
USB communication connector
85
khin c RC3, RC4 v RC5 c tch ra khi cc phn t khc trn board v ni
vi socket USB.
Hnh 1.14 S kt ni truyn thng USB

9. PS/2 COMMUNICATION
u ni PS/2 cho php kt ni trc tip gia PIC.TS vi nhng thit b c s
dng giao tip PS/2 nh PC, bn phm hoc chut. V d: vi iu khin c ni
vi bn phm c nhng phm c nhn hoc kt ni vi PC hot ng
nh mt bn phm. ng DATA c CLK c s dng cho vic truyn d liu.
Trong trng hp ny chng c ni ti nhng pin tng ng RC1 v RC0 ca
vi iu khin.
86
Hnh 1.15 S kt ni PS/2 vi vi iu khin

10. DS1820 DIGITAL THERMOMETER
DS1820 l IC cm bin nhit dng s rt tt cho vic o nhit mi trng
vi di nhit o rng -55 OC n 125OC vi chnh xc +/- 0.5 OC. N phi
c t chnh xc trong socket 3 chn v ng chiu vi hnh v in trn PIC.TS.
Nu khng DS1820 c th b hng. Chn data ca DS1820 c th ni ti pin
RA5 hoc RE2 ca vi iu khin PIC bi jumper JP14.
87
Hnh 1.16 S kt ni DS18b20 vi vi iu khin

11. A-D CONVERTER INPUT
Board pht trin Kit pht trin Vi iu khin PIC c 2 bin tr lm vic vi
Analog to Digital converter ADC. Bin tr P1 th hot ng khi Jumper JP 15
c chn gn vo cho tn hiu analog n chn RA2 ca Microcontroller. Bin
tr P2 th hot ng khi jumper JP16 c chn gn vo cho tn hiu analog n
chn RA3 ca microcontroller. C 2 u ra analog ca bin tr trong phm vi 0V
n 5V.
88
Hnh 1.17 - ADC Converter input

o tn hiu tng t cc jumper pull-up/down ca PORTA cn phi c loi
b. Cc chn ca PORTA khng kt ni ti bt c cc thnh phn thit b no
khc.
ng dng chuyn i tng t - s khc nhau, vi iu khin nhn tn hiu tng
t t chn u vo v chuyn n thnh tn hiu s. V c bn, bn c th o bt
k tn hiu tng t no trong phm vi 0 5V
Hnh 1.18 S kt ni khi o ADC

12. DIRECT PORT ACCESS
Tt c cc pin vo/ra ca microcontroller c th c truy cp trc tip qua cc
u ni t bn mp phi ca PIC.TS cho mi PORTA, PORTB, PORTC,
PORTD v PORTE. y l socket 10-pin (5x2) cung cp VDD, GND v 8 pin
port kt ni vi bn ngoi bng cp kt ni.
Nhng u ni ny s dng cho vic m rng h thng vi nhng board m rng
h thng bn ngoi v cn bo m nhng thit b ngoi vi trn board phi c
tch ra bng vic t cc jumper thch hp khi thit b ngoi vi bn ngoi cng
dng chn .
Nhng u ni cng c th s dng gn u d logic hoc cc thit b o th khc.
89
Hnh 1.19 - S kt ni PORTB
90
PHN II: THC HNH

Bi thc hnh s 1
S DNG PHN MM WINPIC800
TRUY CP CNG VO RA S V IU KHIN LED 7 DON
I. MC CH
Lm quen vi phn mm WinPIC800, bit cch s dng phn mm
v mch np c sn trn PIC.TS np chng trnh cho PIC.
-
Tm hiu cc cng vo ra ca vi iu khin PIC16f877A.
Vit chng trnh iu khin cc cng vo ra, thc hin gii m v

hin th cc s t 0 9 trn leb 7 thanh.
II. CHUN B
My tnh c ci chng trnh WinPIC800, trnh dch CCS,
HT-PIC.
PIC.TS v cc module, vi iu khin PIC16F877A, ng h o,
cp ngun, cp kt ni.
L thuyt v lp trnh C, lp trnh C cho PIC trn CCS, HTPIC
-
Gii m v hin th vi led 7 thanh.
III. THC HNH

1. Np chng trnh cho PIC bng phn mm WinPIC
Trn PIC.TS c thit k sn mt mch np do s khng cn bt k
mch np no t bn ngoi. Mt khc vi mch np sn c ny bn khng cn
phi tho chip nhiu ln trnh cc phin phc v h hng vt l.
Phn mn WinPIC800 i cng khng cn ci t c th s dng ngay rt tin
li. Nhn dp vo biu tng WinPIC800 trn desktop hoc file WinPIC800.exe
trong th mc WinPIC800. Ca s chng trnh WinPIC800 hin ln:
91
Hnh 2.1 Giao din WinPIC800

Nhn vo menu Settings ->Hardware chn cu hnh s dng WinPIC800
cho PIC.TS nh sau:
Hnh 2.2 Cu hnh cho WinPIC800

Lu :
- Nu khng hin ln bng nh hnh trn th nhp chut vo trn s 1
- Nhp vo trn s 2 bt cc chc nng chn cu hnh
Ci t cu hnh cho WinPIC800 chnh xc nh hnh sau:
92
Hnh 2.3 Cu hnh WinPIC800 s dng cho PIC.TS

Nhn vo nt Apply edits xc nhn ci t.
Kt ni vi PIC.TS:
- Chuyn chuyn mch ngun sang ch ngun t kit (ln trn).
- Bt Cng tc ngun n Power sng.
- Ni cable programmer vo cng LPTx ca PC v bo mch.
Kim tra kt ni:
Sau khi kt ni phn cng, chy phn mm WinPIC800. Nhn vo Icon Detect
device (trong vng trn hnh di) mn hnh hin ln nh hnh sau:
93
Hnh 2.4 Qu trnh kim tra kt ni v loi pic s dng

Nhn chn Close this window. ln sau bng detect t ng. Nhn nt
accept ng ca s.
Lu : Khi nhn nt detect device WinPIC800 s t ng chn device m n
detect c. iu ny ny gip bn khi tn cng chn device.
Kch vo menu chn File -> Open sau chn ng dn dn file .hex.
V d: D:\PIC\port test.hex chn OK.
Sau vo menu chn thc n Device -> Program All.
Kt qu: Chp s c np chng trnh iu khin.
94
Hnh 2.5 ang np chng trnh cho vi iu khin

Ch : Sau khi np chng trnh thnh cng phi tho cp np trnh gy
nh hng ti hot ng ca h thng.
2. Truy cp cng vo ra s
Nhim v: Tm hiu vi iu khin 16F877A v lp trnh iu khin cc cng vo
ra s.
95
A0
A1
D0
D1
A2
A3
D2
A4
D3
D4
A5
B0
D5
B1
D6
D7
B2
B3
D8
B4
D9
D10
B5
B6
D11
B7
D12
D13
C0
C1
D14
D15
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
C2
C3
C4
C5
C6
C7
D0
D1
D2
D3
D4
D5
D6
D7
E0
E1
D16
D17
R16
R17
D18
D19
R18
R19
A1
A3
A5
B0
B2
B4
B6
JP1
A0
A2
A4
VCC
1
3
5
7
9
D20
R20
D21
D22
R21
R22
B1
B3
B5
B7
C0
C2
C4
C6
JP2
2
4
6
8
10
1
3
5
7
9
D23
R23
D24
D25
R24
R25
C1
C3
C5
C7
D0
D2
D4
D6
JP3
2
4
6
8
10
VCC
VCC
1
3
5
7
9
D26
R26
D27
D28
R27
R28
D1
D3
D5
D7
E0
E2
JP4
2
4
6
8
10
VCC
1
3
5
7
9
D29
R29
D30
R30
E2
D31
R31
D32
R32
JP5
2
4
6
8
10
1
3
5
7
9
2
4
6
8
10
E1
VCC
Hnh 2.6 S nguyn l module PIC.TS01

Nguyn l hot ng:
Cc n led trn PIC.TS01 s c ni trc tip chn anot n cng ca vi iu
khin PIC trn PIC.TS ng thi ni tip mt in tr 100ohm ri a xung t.
Cc cng ca PIC c th cp dng trc tip cho led m khng cn m hay
khuch i. Mi cng vo ra s c ni vi mt n led. Khi mt cng c
xut gi tr l 1 th led sng ngc li nu xut gi tr 0 led tt. Ch : y
gi nh l PIC ang c cu hnh l mt cng ra s.
Cc bc tin hnh:
- Ni cc cng PA, PB, PC, PD v PE ca PIC.TS tng ng vi cc
JP1, JP2, JP3, JP4 v JP5 ca module PIC.TS01.
- Vit chng trnh iu kin cc n led tt sng theo yu cu.
- Bin dch v np chng trnh ln vi iu khin PIC
- Sa li chng trnh c c chu chnh led sng theo mun.
C th chy th chng trnh mu: PORT_TEST.C c sn th mc
.../sample/ PORT_TEST/ tham kho hoc kim tra cc module c chy tt hay
khng trc khi vit mt chng trnh cho ring mnh.
3. iu khin led 7 on
Nhim v: Tm hiu led 7 on, PIC16F877A trong iu khin v gii m hin
th cc s. Vit c chng trnh gii m hin th cc s theo yu cu trn led 7
on.
96
A0
A1
A2
A3
A4
A5
B4
B5
B6
B7
R0
R1
R2
R3
R4
R5
R10
R11
R12
R13
D0
A0
A2
A4
D1
JP1
1
3
5
7
9
2
4
6
8
10
D2
D3
A1
A3
A5
B0
B2
B4
B6
VCC
D4
D5
JP2
1
3
5
7
9
D10
B1
B3
B5
B7
2
4
6
8
10
C0
C2
C4
C6
VCC
JP3
1
3
5
7
9
2
4
6
8
10
C1
C3
C5
C7
VCC
D0
D2
D4
D6
DIGIT2
7
6
4
2
1
9
10
5
a
b
c
d
e
f
g
DP
DIGIT1
A
A
3
8
D0
D1
D2
D3
D4
D5
D6
D7
R22
R23
R24
R25
R26
R27
R28
R29
1
3
5
7
9
2
4
6
8
10
D12
D1
D3
D5
D7
E0
E2
VCC
VCC
C0 R14
C1 R15
C2 R16
C3 R17
C4 R18
C5 R19
C6 R20
C7R21
JP4
D11
7
6
4
2
1
9
10
5
a
b
c
d
e
f
g
DP
A
A
D13
JP5
1
3
5
7
9
2
4
6
8
10
E1
VCC
E0
E1
E2
R30
R31
R32
3
8
D30
D31
D32
B3
B2
B1
B0
F1
F2
F3
F4
VCC
JP
1
2
3
Hnh 2.7 S nguyn l PIC.TS03

Nguyn l hot ng:
Trong PIC.TS03 s dng cc led catot chung. Anot ca mi thanh led ca led 7
on c ni n cng vi iu khin PIC thng qua in tr 100ohm nhm hn
dng. Catot ca mi led 7 on c ni xung t. Khi cng xut gi tr l
1 th thnh led sng v ngc li xut 0 th tt. Ch s bn phi ni vi cng
PC, ch s bn tri ni vi cng PD. Cc thanh a, b, c, d, e, f, g ca mi ch s
tng ng ni vi cc bit b0, b1, b2, b3, b4, b5, b6 ca mi cng.
Cc bc tin hnh:
- Ni cc PORT PC v PD PIC.TS tng ng vi JP3 v JP4 trn
module PIC.TS03.
- Vit chng trnh iu kin led 7 on hin th ch s theo yu
cu.
- Bin dch v np chng trnh cho vi iu khin PIC.
- Sa li chng trnh c c s hin th theo yu cu.
97
C th chy th chng trnh mu: 7SegCount00To99.c c sn th mc

/sample/7SEGS_LED/ tham kho hoc kim tra module c chy tt hay
khng trc khi vit mt chng trnh theo mun.
4. iu khin n giao thng
Nhim v: Tm hiu PIC16F877A trong vic vo ra s v gii m iu khin led
7 on. Vit chng trnh iu khin n giao thng.
A0
A1
A2
A3
A4
A5
B4
B5
B6
B7
R0
R1
R2
R3
R4
R5
R10
R11
R12
R13
D0
A0
A2
A4
D1
JP1
1
3
5
7
9
2
4
6
8
10
D2
D3
A1
A3
A5
B0
B2
B4
B6
VCC
D4
D5
JP2
1
3
5
7
9
D10
B1
B3
B5
B7
2
4
6
8
10
C0
C2
C4
C6
VCC
JP3
1
3
5
7
9
2
4
6
8
10
C1
C3
C5
C7
VCC
D0
D2
D4
D6
DIGIT2
7
6
4
2
1
9
10
5
a
b
c
d
e
f
g
DP
DIGIT1
A
A
3
8
D0
D1
D2
D3
D4
D5
D6
D7
R22
R23
R24
R25
R26
R27
R28
R29
1
3
5
7
9
2
4
6
8
10
D12
D1
D3
D5
D7
E0
E2
VCC
VCC
C0 R14
C1 R15
C2 R16
C3 R17
C4 R18
C5 R19
C6 R20
C7R21
JP4
D11
7
6
4
2
1
9
10
5
a
b
c
d
e
f
g
DP
A
A
D13
JP5
1
3
5
7
9
2
4
6
8
10
E1
VCC
E0
E1
E2
R30
R31
R32
3
8
D30
D31
D32
B3
B2
B1
B0
F1
F2
F3
F4
VCC
JP
1
2
3
Nguyn l hot ng:

Trong PIC.TS03 s dng cc led catot chung. Anot ca mi thanh led ca led 7
on c ni n cng vi iu khin PIC thng qua in tr 100ohm nhm hn
dng. Catot ca mi led 7 on c ni xung t. Khi cng xut gi tr l
1 th thnh led sng v ngc li xut 0 th tt. Ch s bn phi ni vi cng
PC, ch s bn tri ni vi cng PD. Cc thanh a, b, c, d, e, f, g ca mi ch s
tng ng ni vi cc bit b0, b1, b2, b3, b4, b5, b6 ca mi cng.
Cc n led xanh, v vng cng c ni n cc cng ca vi iu khin PIC
thng qua tr 100ohm. Khi vi iu khin xut gi tr 1 ra cng th n tng
98
ng sng ngc li nu xut gi tr 0 n s tt. Cc n led v led 7 on c

ni vi vi iu khin PIC theo nh bng sau:
Bng 1
LED
D0
D1
D2
D3
D4
D5
D11
D12
D13
D30
D31
D32
F1
F2
F3
F43
Tn cng
A0
A1
A2
A3
B4
A5
B5
B6
B7
E0
E1
E2
B0
B1
B2
B3
Gi ch
Vng
Xanh
Xanh
Vng
Vng
Xanh
Xanh
Vng
Nt 1
Nt 2
Nt 3
Nt 4
Cch tin hnh:

Ni cc port PA, PB, PC, PD v PE ca kit chnh PIC.TS tng
ng vi cc port JP1, JP2, JP3, JP4 v JP5 ca module PIC.TS03.
- Vit chng trnh iu kin cc n led xanh, , vng tt sng theo thi
gian yu cu ng thi hin th thi gian m ngc trn led 7 on cho
mt chiu c quy nh.
- Bin dch v np chng trnh ln vi iu khin PIC.
- Sa li chng trnh c c thi gian lu thng cc lung theo theo
yu cu.
C th th chng trnh mu: TRAFFIC_LIGHT.c c sn th mc
/sample/TRAFFIC_LIGHT/ tham kho hoc kim tra module c chy tt
hay khng trc khi vit mt chng trnh theo yu cu.
M rng, nu c th hy vit chng trnh dng cc phm F thay i thi gian
lu thng ca cc lung.
99
Bi thc hnh s 2
BIN I ADC, O IN P, NHIT
HIN TH TRN LED V TRUYN THNG QUA RS232
I. MC CH
Lm quen vi b bin i tng t s ADC c sn trn vi iu khin
PIC16F877A. Tm hiu chun 1 dy v truyn thng khng ng b UART. Vit
chng trnh bin i ADC, o in p, giao tip vi cm bin nhit
DS18B20.
II. CHUN B
HT-PIC.
cp ngun, cp kt ni.
L thuyt v chun 1 dy, truyn thng khng ng b
UART.
III. THC HNH
1. Bin i ADC v hin th trn led
Nhim v: Tm hiu v s dng b bin i ADC ca vi iu khin PIC16F877A
VCC
JP_ADC1
JP_ADC2
1
2
3
RA2
VR2
2
1
2
1
VR1
1
2
3
RA3
Hnh 2.9 S nguyn l khi bin tr

Nguyn l hot ng:
Khi vn bin tr VR1 v VR2 tng ng in p tai RA2 v RA3 s thay i.
Cu hnh PIC cho php b bin i ADC knh 2 v knh 3 (RA2 v RA3) hot
100
ng. Gi tr tng t tai RA2 v RA3 s c b ADC ca PIC chuyn sang

thnh tn hiu s.
Cch tin hnh:
- Kim tra jumper JP_ADC2 trng thi kt ni, ni u ra bin tr
vi u vo ADC ca PIC. VR2 v JP_ADC2 ni n ng vo AN3.
- Cng tc DIP_SW1.3, DIP_SW1.4 trng thi OFF ngt u vo
ADC ra khi in tr treo khi lm vic vi in p tng t (in tr
treo dng khi lm vic ch vo ra tn hiu s)
- Ni port PC (PD) ca kit chnh PIC.TS vi cc port JP3 (JP4) ca
module PIC.TS03
- Vit chng trnh c gi tr t b chuyn i ADC v xut ra cng C
(D)
- Sau khi np thnh cng, khi chng trnh ang chy, vn bin tr t
min n max s thy gi tr ca in p c chuyn i thnh tn hiu
s hin th trn cc led ni vi PC (PD) thay i theo mi v tr ca
chit p
C th th chng trnh mu: ADC Single_LED.c c sn th mc
/sample/ADC2PORTC/ tham kho hoc kim tra module c chy tt hay
khng trc khi vit mt chng trnh theo yu cu.
2. o in p v truyn thng qua RS232
Nhim v:
S dng b ADC trn PIC o in p t u ra ca bin tr sau truyn d
liu o c ln my tnh qua RS232.
Cch tin hnh:
- Kim tra jumper JP_ADC1, JP_ADC2 trng thi kt ni, ni u
ra chit p vi u vo ADC ca PIC
- Cng tc DIP_SW1.3, DIP_SW1.4 trng thi OFF ngt u vo
ADC ra khi in tr treo khi lm vic vi in p tng t (in tr treo
dng khi lm vic ch vo ra tn hiu s)
- Kim tra JP_TX v JP_RX trng thi ni chn 5 vi chn 6 ni
chn TX v RX ca b thu pht UART vi b pht thu MAX232
- Ni cng truyn thng ni tip ca PIC.TS vi cng COM ca my tnh
101
- S dng trnh HyperTermial giao tip vi tn hiu trn knh RS232

Vo Hyper Terminal nh hnh di y
Hnh 2.10a - Hyper Terminal

G tn l 9600 trong Name nh hnh di, ri chn OK.
Hnh 2.10b - Hyper Terminal

Chn COM1 trong Connect using nh sau:
Hnh 2.10c - Hyper Terminal
102
t cc thuc tnh nh hnh di, ri chn OK
Hnh 2.10d - Hyper Terminal

Bm vo biu tng Call kt ni
- Vit chng trnh c gi tr t b chuyn i ADC v truyn d liu
qua b truyn thng ni tip
- Sau khi np thnh cng, khi chng trnh ang chy, vn bin tr t min
n max trn mn hnh my tnh s hin th cc gi tr ca in p c
chuyn i thnh tn hiu s thay i theo mi v tr ca chit p.
C th th chng trnh mu: ADC1.c c sn th mc /sample/
ADC2UART/ tham kho, hoc kim tra module c chy tt hay khng, trc
khi vit mt chng trnh theo yu cu.
M rng: c th thay i chng trnh chuyn i gi tr u ra ADC thnh
gi tr in p tng ng v gi ln my tnh theo dng
U1 = X.X (V) , U2 = Y.Y (V). Trong X.X l in p ca VR1, Y.Y l in p
ca VR2, nm trong khong 0.0V n 5.0V.
V d: U1 = 2.5 (V), U2 = 1.8 (V)
3. o nhit v truyn thng qua RS232
Nhim v:
Thc hnh vi b cm bin nhit DS18B20 c sn trn PIC.TS. Giao tip PIC
vi DS18B20 thng qua giao tip 1 dy (one wire interface), truyn d liu
khng ng b UART c sn trn PIC qua chun RS232. Vit chng trnh c
d liu nhit t DS18B20 v truyn d liu qua UART.
Cch tin hnh:
103
- Kim tra jumper JP_temp trng thi kt ni chn 1 (bn phi) vi chn
2 ni chn data ca DS1820 vi RE2 ca PIC.
- Cng tc DIP_SW1.5 trng thi ON ni n in tr treo (in tr
treo dng khi lm vic ch vo ra tn hiu s).
- Kim tra JP_TX v JP_RX trng thi ni chn 5 vi chn 6, ni
chn TX v RX ca b thu pht UART vi b pht thu MAX232.
- Ni cng truyn thng ni tip ca Kit chnh vi cng COM ca my
tnh.
- S dng trnh HyperTermial giao tip vi tn hiu trn knh RS232.
- Vit chng trnh c gi tr nhit t DS1820 v truyn i qua b
truyn thng khng ng b.
- Sau khi np thnh cng, khi chng trnh ang chy, dng tay (hoc mt
ngun nhit no ) trm vo cm bin nhit DS1820 v quan st thy gi
tr nhit hin th trn mn hnh t t tng ln (Ch tr l tng i
ln, c 1 giy v gi tr hin th c c th sai lch vi ). Khi b tay ra
nhit s gim xung t t.
C th th chng trnh mu c sn th mc /sample/TEMP2UART/
tham kho hoc kim tra module c chy tt hay khng, trc khi vit mt
chng trnh cho ring mnh.
Bi thc hnh s 3
C PHM BM, IU KHIN RELAY
V C THI GIAN THC DS1307 HIN TH TRN LEB 7 ON
I. MC CH
c phm bm, phng php qut ma trn phm. Tm hiu lm quen vi Thi
gian thc DS1307 c sn trn PIC.TS. Vit chng trnh c phm bm v iu
khin vo ra s, c d liu thi gian t DS1307 v hin th trn led 7 on.
II. CHUN B
HT-PIC.
cp ngun, cp kt ni.
104

Phng php qut ma trn phm, chng rung phm co kh
bng phn mm.
-
L thuyt v giao tip chun I2C.
III. THC HNH

1. c phm bm
Nhim v: Lm quen s dng phm bm, giao tip vi phm bm bng cng vo
ra s. Vit chng trnh s dng cc cng vo ra nhn lnh t phm bm.
Cch tin hnh:
- Ni cc port PA, PB, PC v PD ca kit chnh PIC.TS tng ng vi cc
port JP1, JP2, JP4 v JP3 ca module PIC.TS01
- Kim tra jumper KEY_JP ca module PIC.TS02 ni xung t ni 8
cc ca 8 phm bm F0 n F7 xung t, tm cc cn li ni n cng port
D ca PIC.
- Kim tra jumper JP4 ca kit chnh PIC.TS ni ln dng ngun (v tr bn
di) ni treo port D ln dng ngun
Nh vy, Port D s c treo ln dng ngun ng thi ni n 8 phm bm,
cc cc cn li ca 8 phm bm ni xung t, khi phm c bm s lm cho
port c ni xung t, khi khng c bm port s c ni n 5V qua in
tr treo 4,7K.
- Vit chng trnh nhn bit trng thi ca 8 phm bm trn port D v thc
hin lnh quy nh cho phm , gi s bt sng mt s thanh led no
trn 6 led 7 on
- Sa li chng trnh c c chc nng ca cc phm theo yu cu
khc.
C th th chng trnh mu: BUTTON.c c sn th mc/sample/
BUTTON/ tham kho hoc kim tra cc module c chy tt hay khng trc
khi vit mt chng trnh cho ring mnh
2. c phm bm t bn phm ma trn
Nhim v:
105
Lm quen vi vic giao tip vi bn phm ma trn, giao tip PIC vi bn phm
ma trn bng cng vo ra s. Vit mt chng trnh s dng cc cng vo ra
nhn lnh t phm bm.
Jum1
VCC
3
2
1
P40
1
2
3
4
5
P41
P43
P45
P47
1 2
3 4
5 6
7 8
9 10
Jum2
VCC
3
2
1
B01
B02
B03
B10
B11
B12
B13
B20
B21
B22
B23
B30
B31
B32
B33
AR0
JP4
P40
P42
P44
P46
B00
P41
P42
VCC
P43
AR1
1
2
3
4
5
P44
P45
P46
P47
Hnh 2.11 S nguyn l kt ni bn phm ma trn

Cch tin hnh:
- Ni cc port PA, PB, PC v PD ca kit chnh PIC.TS tng ng vi cc
port JP1, JP2, JP4 v JP3 ca module PIC.TS02
Cc chn RC0 n RC7 ca PIC ln lt ni ti cc hng 0 n 3,
cc ct 0 n 3 ca ma trn bn phm:
RC[0..3] -> hng[0..3]
RC[4..7] -> ct[0..3]
- Kim tra jumper JUM1 ca module PIC.TS02 ni ln dng ngun
ni 4 cng PC[0..3] ln dng ngun.
- Kim tra jumper JUM2 trng thi khng kt ni
- Vit chng trnh nhn bit trng thi ca 16 phm bm trn port C v
thc hin lnh quy nh cho phm , gi s bt sng mt s thanh led no
trn 6 led 7 on
khc
C th th chng trnh mu: KEY_BOARD.c c sn th mc /sample/
KEY_BOARD/ tham kho hoc kim tra cc module c chy tt hay khng,
trc khi vit mt chng trnh cho ring mnh.
106
3. c phm bm v iu khin relay

Nhim v: Vit chng trnh nhn bit phm bm , chng ny phm v iu khin
ng ngt relay tng ng vi phm yu cu.

Nguyn l hot ng:
Cc chn RB6, RB4, RB2 v RB0 ca PIC ln lt ni ti cc u vo IN1 n
IN 4 ca ULN2803. RB1, RB3, RB5v RB7 ln lt F3. Port B s c treo ln
dng ngun ng thi ni n 4 phm bm, cc cc cn li ca 4 phm bm ni
xung t, khi phm c bm s l cho port c ni xung t, khi khng
c bm port s c ni n 5V qua in tr treo 4,7K.
Khi u vo IN1 n IN4 ca ULN2803 c gi tr logic l 1 do vi iu khin
xut ra thi tng ng OUT1 n OUT4 s c ni xung t, relay s ng.
Ngc li khi u vo c gi tr logic l 0 Relay m.
Cch tin hnh:
107
- Ni port PB ca PIC.TS vi port JP2 ca module PIC.TS04

- Kim tra jumper KEY_JP ca module PIC.TS04 ni xung t.
- Kim tra jumper JP2 ca PIC.TS ni ln dng ngun.
- Vit chng trnh nhn bit trng thi ca 4 phm bm trn port B v khi
mt phm c bm mt ln s thc hin lt chuyn trng thi ca
RELAY tng ng v gi trng thi cho n ln bm sau s li
chuyn trng thi. Chuyn trng thi c ngha l nu RELAY ang
ng s chuyn sang trng thi m, cn nu n ang m s chuyn sang
trng thi ng.
khc.
C th th chng trnh mu: RELAY.c c sn th mc /sample/ RELAY/
tham kho hoc kim tra cc module c chy tt hay khng trc khi vit mt
chng trnh khc theo yu cu.
4. c thi gian thc hin th trn Led 7 on
Nhim v:
Lm quen vi b m thi gian thc DS11307, giao tip PIC vi DS1307 qua
giao tip I2C. Vit chng trnh giao tip PIC vi DS1307, giao tip PIC vi b
hin th led 7 on theo ch qut (hin th ng), c d liu thi gian t
DS1307 v hin th trn b hin th led 7 on.
SW2
RA0
RA1
RA2
RA3
RA4
RA5
RC3_U
RC4_U
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
R_rtc1
4K7
R_rtc2
VCC
4K7
X 32768Hz
6
5
1
2
4
RTC
SCL
VCC
SDA
VBAT
X1
X2
SQW/OUT
8
3
7
GND
DS1307
BATTERY
Hnh 2.13 S nguyn l khi thi gian thc
108
Digit4
3
A
8
A
Digit3
3
A
8
A
Digit1
3
A
8
A
a
b
c
d
e
f
g
DP
seg_a 7
seg_b 6
seg_c 4
seg_d 2
seg_e 1
seg_f 9
seg_g 10
seg_P 5
a
b
c
d
e
f
g
DP
seg_a 7
seg_b 6
seg_c 4
seg_d 2
seg_e 1
seg_f 9
seg_g 10
seg_P 5
a
b
c
d
e
f
g
DP
Q2
3
A
8
A
Q3
Digit0
3
A
8
A
Q4
Q1
VCC
1
VCC
Q5
P21
P23
P25
P27
seg_a 7
seg_b 6
seg_c 4
seg_d 2
seg_e 1
seg_f 9
seg_g 10
seg_P 5
1 2
3 4
5 6
7 8
9 10
a
b
c
d
e
f
g
DP
JP2
P20
P22
P24
P26
Digit2
3
A
8
A
A0
a
b
c
d
e
f
g
DP
seg_a 7
seg_b 6
seg_c 4
seg_d 2
seg_e 1
seg_f 9
seg_g 10
seg_P 5
A1
seg_a 7
seg_b 6
seg_c 4
seg_d 2
seg_e 1
seg_f 9
seg_g 10
seg_P 5
A2
Digit5
seg_a 7
a
seg_b 6
b
seg_c 4
c
seg_d 2
d
seg_e 1
e
seg_f 9
f
seg_g 10
g
seg_P 5
DP
A3
220
220
220
220
220
220
220
220
A4
R0
R1
R2
R3
R4
R5
R6
R7
A5
P20
P21
P22
P23
P24
P25
P26
P27
R8
10K
R9
10K
R10
10K
R11
10K
R12
10K
R13
10K
P15
P14
P13
P12
P11
P10
JP1
P10
P12
P14
1 2
3 4
5 6
7 8
9 10
P11
P13
P15
VCC
JP3
P30
P32
P34
P36
1 2
3 4
5 6
7 8
9 10
P37
P31
P33
P35
P37
F7
P36
F6
P35
F5
P34
F4
P33
F3
P32
F2
P31
F1
P30
F0
VCC KEY JP
VCC
1
2
3
Hnh 2.14 S nguyn l khi phm bm v hin th PIC.TS02
Nguyn tt hot ng:

Chn SCL v SDA ca DS1307 c ni vi RC3 v RC4 ca PIC. y l hai
chn h tr giao tip I2C ca PIC. Cc thanh a, b, c, d, e, f, g, p chung ca 6 led 7
on tng ng s c ni n port B ca vi iu khin PIC trn PIC.TS ni
tip qua mt in tr 100 ohm. Cng A ca PIC s iu khin 6 Transitor qua 6
in tr cp ngun cho 6 anot chung ca 6 led 7 on tng ng.
109
Q0
Bng sau y m t th t kt ni cc chn ca hai cng A v B

Chn
PIC
RA5
RA4
RA3
RA2
RA1
RA0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
in tr
R8
R9
R10
R11
R12
R13
R7
R6
R5
R4
R3
R2
R1
R0
Chn Led Transitor

7 thanh
A5
Q5
A4
Q4
A3
Q3
A2
Q2
A1
Q1
A0
Q0
p
g
f
e
d
c
b
a
Chng trnh iu khin s dng hai cng A v B iu khin b hin th 6 led

7 thanh ng thi giao tip vi DS1307 c gi tr gi, pht, giy v hin th
trn b hin th led 7 thanh.
Cch tin hnh:
- Kim tra SW2.7, SW2.8 trng thi ON ni chn SCL v SDA ca
DS1307 vi RC3 v RC4 ca PIC.
- Ni cc port PA, PB v PD ca PIC.TS tng ng vi cc port JP1, JP2
v JP3 ca module PIC.TS02.
- Vit chng trnh c gi, pht, giy t DS1307 v hin th trn b hin
th led 7 thanh.
- Bin dch v np chng trnh ln vi iu khin PIC.
- Sau khi np thnh cng, khi chng trnh ang chy, tt ngun cho h
thng, mt thi gian sau bt li ta s thy thi gian vn tip tc chy
khi tt ngun .
C th th chng trnh mu: \samples\DS1307-7SEG\Ds1307 LED.c
110
c sn th mc tham kho hoc kim tra module c chy tt hay khng

trc khi vit mt chng trnh theo yu cu khc.
PH LC
/****************************************
Bo mon DTVT Khoa CNTT Thai Nguyen
FILE NAME: Test led PortD.c
***************************************/
#include<16f877A.h>
#fuses HS,NOLVP,NOWDT,PUT
#use delay(clock=8000000) // defind crystal = 8MHz
//******************************
// main program start here
//******************************
void main()
{
char i,count;
while(TRUE)
{
count=1;
//ship a
for (i=0;i<=6;i++)
{
output_a(count);
delay_ms(150);
count=count<<1;
}
count=1;
//ship b
for (i=0;i<=8;i++)
111
{
output_b(count);
delay_ms(150);
count=count<<1;
}
count=1;
//ship c
for (i=0;i<=8;i++)
{
output_c(count);
delay_ms(150);
count=count<<1;
}
count=1;
//ship d
for (i=0;i<=8;i++)
{
output_d(count);
delay_ms(150);
count=count<<1;
}
count=1;
//ship e
for (i=0;i<=3;i++)
{
output_e(count);
delay_ms(150);
count=count<<1;
}
output_a(0xff);
// a
112
delay_ms(150);
output_a(0x00);
output_b(0xff);
// b
delay_ms(150);
output_b(0x00);
output_c(0xff);
// c
delay_ms(150);
output_c(0x00);
output_d(0xff);
// d
delay_ms(150);
output_d(0x00);
output_e(0xff);
// e
delay_ms(150);
output_e(0x00);
delay_ms(150);
output_a(0xff);
//flash all ON
output_b(0xff);
output_c(0xff);
output_d(0xff);
output_e(0xff);
delay_ms(150);
output_a(0x00); // OFF
output_b(0x00);
output_c(0x00);
output_d(0x00);
output_e(0x00);
delay_ms(150);
output_a(0xff); // ON
113
output_b(0xff);
output_c(0xff);
output_d(0xff);
output_e(0xff);
delay_ms(150);
output_a(0x00); // OFF
output_b(0x00);
output_c(0x00);
output_d(0x00);
output_e(0x00);
delay_ms(150);
}}
//===============================================//TEN DE
TAI :HE THONG DAO TAO VI DIEU KHIEN PIC
//Ngon ngu
:C cho PIC, dung trinh bien dich CCS compiler
//Lap trinh vien :Bo mon DTVT Khoa CNTT TN

//Chuong trinh
//Su dung MCU
//Ngay bat dau
:VAO RA CONG
:16f877a cua Microchip.thach anh 8 Mhz
:Ngay xx thang' xx nam 2008
//Ngay hoan thanh :Ngay xx thang' xx nam 2008

//Mo ta hardware
:DEN GIAO THONG
//File name: Trafic_light.c

//===============================================
#include <16f877A.h>
#include <def_877a.h> //file header do nguoi dung dinh nghia
#fuses HS,NOLVP,NOWDT,PUT
#use delay(clock=8000000) // defind crystal = 8MHz
byte const DIGITS[] = {0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f};
114
void display_right_led(byte digit);

void display_left_led(byte digit);
void displayh(byte n);
void displayl(byte k);
//******************************
// main program start here
//******************************
void main()
{
char i;
//tat het cac den
output_a(0x00);
output_b(0x00);
output_c(0x00);
output_d(0x00);
output_e(0x00);
delay_ms(3);
while(TRUE)
{
//phase 1
//duong ngang
RA2 = 1; RE0 = 1;//xanh
RA1 = 0; RE1 = 0;//vang
RA0 = 0; RE2 = 0;//do
//duong doc
RA3 = 0; RB7 = 0;//xanh
RB4 = 0; RB6 = 0;//vang
RA5 = 1; RB5 = 1;//do
//dem
115
for (i=30;i>3;i--)
displayh(i);
//phase2
//duong ngang
RA2 = 0; RE0 = 0;//xanh
RA1 = 1; RE1 = 1;//vang
RA0 = 0; RE2 = 0;//do
//duong doc
RA3 = 0; RB7 = 0;//xanh
RB4 = 0; RB6 = 0;//vang
RA5 = 1; RB5 = 1;//do
//dem
for (i=3;i>0;i--)
displayl(i);
//============
//phase 3
//duong ngang
RA2 = 0; RE0 = 0;//xanh
RA1 = 0; RE1 = 0;//vang
RA0 = 1; RE2 = 1;//do
//duong doc
RA3 = 1; RB7 = 1;//xanh
RB4 = 0; RB6 = 0;//vang
RA5 = 0; RB5 = 0;//do
//dem
for (i=30;i>3;i--)
displayh(i);
116
//=============
//phase4
//duong ngang
RA2 = 0; RE0 = 0;//xanh
RA1 = 0; RE1 = 0;//vang
RA0 = 1; RE2 = 1;//do
//duong doc
RA3 = 0; RB7 = 0;//xanh
RB4 = 1; RB6 = 1;//vang
RA5 = 0; RB5 = 0;//do
//dem
for (i=3;i>0;i--)
displayl(i);
}
}
//===================================
void display_right_led(byte digit)
{
output_c(DIGITS[digit] ^ 0xff);
}
//===================================
void display_left_led(byte digit)
{
output_d(DIGITS[digit] ^ 0xff);
}
//===================================
void displayh(byte n) {
byte i;
117
for (i = 0; i < 100; i++) {

display_left_led(n / 10);
display_right_led(n % 10);
delay_ms(6);
}
}
//==================================
void displayl(byte k) {
byte i;
for (i = 0; i < 2; i++) {
display_left_led(k / 10);
display_right_led(k % 10);
delay_ms(180);
output_c(0xff);
output_d(0xff);
delay_ms(120);
}
}
/***********************************************************
*
*

File name: 7seccount00to99.c
************************************************************/
#include <16F877A.h>
#fuses HS, NOWDT, PUT,NOLVP
#use delay (clock=8000000) // define crystal = 8MHz
#define LEFT_LED_C1 PIN_A1
#define RIGHT_LED_C2 PIN_A0
//
0 1 2 3 4 5 6 7 8 9
118

void display_right_led(byte digit);
void display_right_led(byte digit)
void display_left_led(byte digit);
//***********************************************************
//Chuong trinh chinh
void main() {
while (true)
count_00_99();
}
//**********************************************************
void display_right_led(byte digit) {
output_c(DIGITS[digit] ^ 0xff);
}
//*************************************************************
void display_left_led(byte digit) {
output_d(DIGITS[digit] ^ 0xff);
}
//***************************************************************
//ham display n hien thi 100 viec goi ham hien thi hang truc va hang don vi
void display(byte n) {
byte i;
for (i = 0; i < 100; i++) {
display_left_led(n / 10);
display_right_led(n % 10);
delay_ms(1);
}
}
//****************************************************************
//ham dem tu 0 den 99 thuc hien 100 lan ham display(i) voi bien i = 0 den 100
119
void count_00_99() {
byte i;
for (i = 0; i < 100; i++)
display(i);
}
//****************************************************************
/**********************************************
Bo mon DTVT Khoa CNTT Dai hoc Thai Nguyen *
File name: ADC Single_LED.c
***********************************************/
#fuses HS, NOWDT, NOPROTECT, NOLVP
#device 16F877*=16, ADC=8
#use delay(clock=8000000)
//*********************************************
void main()
{
setup_adc(adc_clock_internal);
setup_adc_ports(ALL_ANALOG);
set_adc_channel(3); // PIC.TS VR1 JP1=RA2, VR2 JP2=RA3
delay_ms(10);
while (true)
output_c(read_adc());
}
//*********************************************
/****************************************************
* Bo mon DTVT Khoa CNTT Dai hoc Thai Nguyen
*
120
* File name: ADC1.c

*****************************************************/
// PIC16F877 header file
#device 16f877*=16, ADC=10
// 10 bits ADC
// for 8Mhz crystal
#fuses HS, NOWDT, NOPROTECT, NOLVP
// for debug mode
#use rs232(baud=9600, xmit=PIN_C7, rcv=PIN_C6, stream=MYPC)

// rs232 setting
#define DO_NOTHING
#define DO_START_ADC
#define DO_END_ADC
1
2
/*============================================*/
void main(void)
{
int16 int_volt;
int8 str_volt[21];
float flt_volt;
int8 do_what = DO_NOTHING;
int8 tmp;
printf( "S: Start ADC\n\r");
Printf( "Q: END ADC\n\r");
while(true){
// if rs232 get char
if(0 != kbhit())
{
tmp = fgetc(MYPC);
switch(tmp)
{
case 'S':
case 's':
121
printf( "S: Start ADC\n\r" );

do_what = DO_START_ADC;
// init pic16f877a adc
setup_adc_ports(RA0_RA1_RA3_ANALOG);
setup_adc(ADC_CLOCK_INTERNAL);
set_adc_channel(3);
break;
case 'Q':
case 'q':
printf( "Q:EndADC\n\r" );
do_what = DO_END_ADC;
// adc off
setup_adc(ADC_OFF);
break;
default :
// rs232 get other char
putc(tmp);
break;
}//end switch(tmp)
}//end if(kbhit())
switch(do_what)
{
case DO_START_ADC:
// start adc and send result to PC
int_volt = read_adc();
flt_volt = 5.0 * int_volt / 0x3ff;
sprintf(str_volt, "ADC: %1.3fV\n\r", flt_volt);
printf(str_volt);
printf( "\n\r" );
122
delay_ms(500);
break;
case DO_END_ADC:
// you want to do
break;
case DO_NOTHING:
// you want to do
break;
default:
break;
}//end switch(do_what)
}//end while(1)
}//end main()
/****************************************
chuong trinh dieu khien led de kiem tra cong
Bo mon DTVT Khoa CNTT Dai hoc Thai Nguyen
***************************************/
#device *=16
#device adc=8
#FUSES NOWDT, HS, PUT, NOPROTECT, NODEBUG, BROWNOUT,
NOLVP, NOCPD, NOWRT
#include <1wire.c>
#use rs232(baud=9600, xmit=PIN_C7, rcv=PIN_C6, stream=MYPC)
// rs232 setting
#include <ds1820.c>
123
void main()
{
float temperature;
setup_psp(PSP_DISABLED); // huy bo PSP
setup_spi(FALSE);
//THIET PAP SPI
setup_timer_0(RTCC_INTERNAL|RTCC_DIV_1); //Thiet lap bo dinh thoi ben

setup_timer_1(T1_DISABLED); //cam
setup_timer_2(T2_DISABLED,0,1); //cam
setup_comparator(NC_NC_NC_NC);
setup_vref(VREF_LOW|-2);
printf("\n\r Bo mon Dien Tu Vien Thong Khoa CNTT");
printf( "\n\rXin chao, toi la PIC.TS, Toi dang do nhiet do\n\r",);
delay_ms(100);
while (TRUE)
{
temperature = ds1820_read();
printf( "Nhiet do: %3.1f ", temperature);
printf( "oC, ");
if(temperature >= 30)
printf("Nong!\n\r
");
else if( temperature >= 20 && temperature < 30)

printf("Nhiet do vua\n\r!");
else
printf("Lanh!\n\r ");
delay_ms(20);
}
}
//*****************************************************
124
File name:
//==============================================
//TEN DE TAI
:HE THONG DAO TAO VI DIEU KHIEN PIC
//Ngon ngu
:C cho PIC, dung trinh bien dich CCS compiler
//Lap trinh vien :Bo mon dien tu Vien Thong

//Chuong trinh
:CHUONG TRINH DOC PHIM
//Su dung MCU

//Ngay bat dau
:16f877a cua Microchip.thach anh 8 Mhz

:Ngay xx thang' xx nam 2008
//Ngay hoan thanh :Ngay xx thang' xx nam 2008

//file name: button.c
//===============================================
#fuses HS,NOWDT,NOPROTECT,NOLVP
#use delay (clock=8000000) // define crystal = 8MHz
#use Fast_IO(D)
byte command;
//
//ma lenh
0 1 2 3 4 5 6 7 8 9
void keyscan();
void display();
//*****************************************************
void main()
{
Set_tris_D(1);
command = 0;
output_a(0x00);//bat chan A5
while(true)
125
{
keyscan();
display();
}
}//end of main program
//****************************************************
void keyscan()
{
output_d(0xff);
if(input(PIN_D0) == 0)
{
delay_ms(150);
if (input(PIN_D0)==0) command = 1;
display() ;
}
{
delay_ms(150);
display() ;
}
{
delay_ms(150);
display() ;
}
{
126
delay_ms(150);
display() ;
}
{
delay_ms(150);
display() ;
}
{
delay_ms(150);
display() ;
}
{
delay_ms(150);
display() ;
}
{
delay_ms(150);
display() ;
}
output_d(0xff);
}
127
//******************************************************
void display()
{
output_b(DIGITS[command] ^ 0xff);
}
//*****************************************************
//END PROGRAM
//========================================================
=====================
//TEN DE TAI
:RELAY
//Ngon ngu:ANSI C cho PIC, dung trinh bien dich Hi-Tech PICC compiler
//Lap trinh vien : Bo mon DTVT Khoa CNTT
//Chuong trinh :HIEN THI SO BAT KY TREN LED_7T
//Su dung MCU : 16f877a cua Microchip.thach anh 20 Mhz
//Ngay bat dau :Ngay xx thang' xx nam 20xx
//Ngay hoan thanh : Ngay xx thang' xx nam 20xx
//Mo ta hardware :
//khi dich chon dung loai PIC:Configure-->Select Device-->chon loai PIC
//============================================
#include<pic.h>
__CONFIG(UNPROTECT & WDTEN & HS & PWRTEN & BOREN &
LVPDIS & DUNPROT & DEBUGDIS);
//**************************************************
void init(void);
void Delay(void);
//===========Chuong trinh =========================
void main()
//chuong trinh trinh
128
{
init();
while(1)
{
if (RB1 == 0)
{
Delay();
if (RB1 == 0)RB0 ^= 1;}
if (RB3 == 0)
{
Delay();
if (RB3 == 0)RB2 ^= 1;}
if (RB5 == 0)
{
Delay();
if (RB5 == 0)RB4 ^= 1;}
if (RB7 == 0)
{
Delay();
if (RB7 == 0)RB6 ^= 1;}
CLRWDT();
}
CLRWDT();
}
//==============THE END =========================
void init(void)
{
//---------Dinh nghi cacs cong-----------------OPTION = 0x01000000;
TRISB = 0b10101010;
129
Delay();
PORTB = 0b10101010;
}
//===============================================
void Delay()
{
unsigned char i;
for (i =0;i<20;i++)
{
NOP(); NOP(); NOP(); NOP(); NOP();
}
}
//================THE END =====================
//===============================================//TEN DE
TAI : Ma tran phim
//Ngon ngu
:ANSI C cho PIC, dung trinh bien dich Hi-Tech PICC compiler
//Lap trinh vien :Bo mon DTVT

//Chuong trinh : HIEN THI SO BAT KY TREN LED_7T
//Su dung MCU :16f877a cua Microchip.thach anh 20 Mhz
//Mo ta firmware :Coi keu khi duoc 5s va co phim RB7 bam thi no keu-theo thoi
gian tuy
//khi dich chon dung loai PIC:Configure-->Select Device-->chon loai PIC
//============================================
130
#include<pic.h>
__CONFIG(UNPROTECT & WDTEN & HS & PWRTEN & BOREN &
LVPDIS & DUNPROT & DEBUGDIS);
//===============Mang phng so; p vo mauc thu
hai===================
#define KEYPORT PORTC
#define NOKEY 16
bit keyfound = 0;
const unsigned char KEY_IO[16] = {0xEE, 0xDE, 0xBE, 0x7E, //C4 C5 C6 C7
0xED, 0xDD, 0xBD, 0x7D,//C3
0xEB, 0xDB, 0xBB, 0x7B,//C2
0xE7, 0xD7, 0xB7, 0x77};
const unsigned char KEY_MAP[16] = {12,11, 0,10,
13, 9, 8, 7,
14, 6, 5, 4,
15, 3, 2, 1};
// 0 1 2 3 4 5 6 7 8 9 a b c d e f
const unsigned char DIGITS[] =
{0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f,0x77,0x7c,0x39,0x5e,0x7
9,0x71};
unsigned char maphim;
//===========Cac dinh nghia =========================
void init(void);
//su bat dau
void keyscan(void);
void display(void);
unsigned char kboard_idkey(void);
void delay(void);
//==================Chuong trinh chinh'===============
void main()
//chuong trinh trinh
{
131
init();
//bat dau chuong trinh
PORTA = 0xff;
maphim = 0;
PORTB = (DIGITS[maphim] ^ 0xff);
while(1)
thoat khoi
//lenh While(bt).Neu bt=1 luon dung thi lap lai ko

//lenh While(bt).Neu bt=0 thi sai thi thoat khoi vong lap
{
keyscan();
display();
CLRWDT();
}
CLRWDT();
}
//================THE END MAIN===================
void init(void)
{
//---------Dinh nghi cacs cong-----------------TRISD
= 0b00000000;
//cong X la ra
PORTD
= 0b11111111;
//CONG RA MUC 0 HAY 1
TRISE = 0b00000011;
TRISB = 0b00000000;
PORTB = 0b00000000;
//--------Dinh nghia cong A-------ADCON1
= 0b00001111;
//4bt dau ko lm g; 4bt sau de cong ra
TRISA
= 0b11000000;
//C?ng A c A0-5 l ra
so
TRISC = 0b11110000;
PORTC = 0b11110000;
}
132
//--------------chia lay gia tri chung cho moi cai--------------//===================================

void keyscan()
{
maphim = KEY_MAP[(kboard_idkey())];
}
void delay()
{
NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP();
NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP();
}
void display()
{
if (keyfound)
{
PORTB = (DIGITS[maphim] ^ 0xff);
PORTA = 0x00;
}
}
//=================================
unsigned char kboard_idkey()
{
unsigned char key = 0xFF;
keyfound = 0;
do
133
{
key++;
KEYPORT &= 0xF0;
// clear lower nibble
KEYPORT |= KEY_IO[key] & 0x0F; // output lower nibble

NOP();
NOP();
keyfound = ((KEYPORT & 0xF0) == (KEY_IO[key] & 0xF0));
} while((key < NOKEY) && (!keyfound));
return(key);
}
//=======================THE
END===============================
/***************************************************************
* Real time Clock DS1307
* Dong ho so su dung DS1307 hien thi tren 6 LED 7-segment hh.mm.ss *

* Compiler Sofware: Compiler CCS Ver 4.018
* Program design: Bo Mon DTVT - Khoa CNTT Thai Nguyen

* Harware:
* - Pull up PORTD, Pull-down Switches, connect PORTD to Switches *

* - PORTA and PORTB to control leb
* - Switches: F0 - Mode, F1 - set time, F2 - clean status
*
*
* - DIP Swich SW2 all ON (Enable 7-segment and RTC DS1307)
File name: DS1307.c

****************************************************************/
//file header nguoi dung dinh nghia
#include <def_877a.h>
#include <ds1307.c>
134
#fuses HS,NOWDT,NOPROTECT,NOLVP
#use
delay(clock=8000000)
byte sec,min,hour;
//Su dung led 7 thanh loai catot
//
// 1 2 3 4 5 6 7 8 9
byte const MAP[10] =

{0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90};
byte DIS1,DIS2,DIS3,DIS4,DIS5,DIS6;
byte key,mode;
int1 ampm,blink,blink_sec,blink_min,blink_hour;
int1 on_off;
int16 count;
#bit SW1 = 0x8.0 // D0 - mode
#bit SW2 = 0x8.1 // D1 - set_time
#bit SW3 = 0x8.2 // D2 - Clear_status
//****************************************************************
**
//Khai bao chuong trinh con
//****************************************************************
**
void init(void);
void set_blink(void);
void change_time(void);
void update_1307(void);
void keyscan(void);
void set_sec(void);
void set_min(void);
135
void set_hour(void);
void clear_status(void);
void read_time(void);
void update_time(void);
void display(void);
//****************************************************************
**
//Chuong trinh chinh
//****************************************************************
**
void main() {
byte u;
Delay_ms(5);
init();
u=read_ds1307(0);
sec=u & 0x7F;// enable RTC
write_ds1307(0,sec);// set second to 00 and enable clock(bit7=0)
//Xoa tat ca cac co khien
key=5;mode=0;blink=0;
blink_sec=0;blink_min=0;blink_hour=0;
count=15;on_off=1;
ampm = bit_test(hour,5);// test AM_PM
if(ampm==0) {RD4 = 0;RD5=1;} //LED AM
if(ampm==1) {RD4 = 1;RD5=0;} //LED PM
while(true)
{
read_time();
display();
keyscan();
}
136
}//end of main program

//****************************************************************
**
void set_blink()
{
switch (mode)
{
case 1: blink_sec=1; break;
case 2: {blink_min=1;blink_sec=0;} break;
case 3: {blink_hour=1;blink_min=0;} break;
case 4:
{
blink=0;mode = 0;blink_sec=0;
blink_min=0;blink_hour=0;
}
break;
}
}
//****************************************************************
**
void change_time()
{
if(mode == 1) {blink_sec=1;set_sec();}
if(mode == 2) {blink_min=1;set_min();}
if(mode == 3) {blink_hour=1;set_hour();}
if(mode == 4)
{
blink=0;mode = 0;
blink_sec=0; blink_min=0; blink_hour=0;
}
137
}
//****************************************************************
**
void update_1307()
{
write_DS1307(0,sec);
write_DS1307(1,min);
bit_set(hour,6);
if (ampm == 0) {bit_clear(hour,5); write_DS1307(2,hour);} // AM
if (ampm == 1) {bit_set (hour,5); write_DS1307(2,hour);} // PM
}
//****************************************************************
**
void keyscan() {
RD0=1;RD1=1;RD2=1;RD3=1;
if(SW1 != 1) { key=0;SW1=1;delay_ms(150);}
if(key != 5)
{
switch (key)
{
case 0: {mode++;key = 5;blink=1;set_blink();}
break;
case 1: {change_time();key = 5;update_1307();}
break;
case 2: {clear_status();key = 5;}
break;
}
}
138
}
//****************************************************************
**
void set_sec()
{
sec=read_ds1307(0);
if (sec>=0x30) {sec=0; min++; write_ds1307(1,min);}
else sec=0;
write_ds1307(0,sec);
}
//****************************************************************
**
void set_min()
{
byte j;
min=read_ds1307(1);
min++;
j=min & 0x0F;
if (j>=0x0A) min=min+0x06;
if (min>=0x60) min=0;
write_ds1307(1,min);
}
//****************************************************************
**
void set_hour()
{
hour= hour & 0x1F;
hour++;
if(hour== 0x0a) hour = hour+0x06;
if(hour == 0x13)
{ hour = 0x00;
if (ampm == 0) ampm = 1;
139
else ampm = 0;
}
}
//****************************************************************
**
void clear_status() {
mode=4; set_blink();
}
//****************************************************************
**
void read_time()
{ sec = read_DS1307(0);
min = read_DS1307(1);
hour = read_DS1307(2);
update_time();
}
//****************************************************************
**
void update_time()
{
ampm = bit_test(hour,5); //test AM PM
if(ampm == 0) {RD4 = 0;RD5=1;} //AM
if(ampm == 1) {RD4 = 1;RD5=0;} // PM
DIS1= sec & 0x0F;
DIS2=(sec & 0xF0)>>4; //convert to BCD SEC
DIS3= min & 0x0F;
DIS4=(min & 0xF0)>>4; //convert to BCD MIN
DIS5= hour & 0x0F;
DIS6=(hour & 0x10)>>4; //convert to BCD HOUR
}
//****************************************************************
**
140
void display() {
TRISB=0x00;TRISA=0x00;
if(blink==0) goto norm;
if(on_off==0) goto led_blink;
norm:
//----------------------------------------------------------------// sec - min - hour
PortB=MAP[DIS1]; RA5=0;//DIS1
delay_ms(1);
RA5=1;
PortB=MAP[DIS2]; RA4=0; //DIS2

delay_ms(1);
RA4=1;
PortB=MAP[DIS3];output_low(PIN_B7);RA3=0;//DIS3
delay_ms(1);
RA3=1;
PortB=MAP[DIS4]; RA2=0;//DIS4
delay_ms(1);
RA2=1;
PortB=MAP[DIS5];output_low(PIN_B7); RA1=0;//DIS5
delay_ms(1);
RA1=1;
PortB=MAP[DIS6];if (portb==0xC0) RA0=1; else RA0=0;//DIS6

delay_ms(1);
RA0=1;//*/
if(count!=0) goto exit;

else
{
count=15;
on_off=0;
}
goto exit;
led_blink:
PortB=MAP[DIS1];
141
if (blink_sec==1) RA5=1;//DIS1
else RA5=0;
delay_ms(3);
RA5=1;
PortB=MAP[DIS2];
if (blink_sec==1) RA4=1;//DIS2
else RA4=0;
delay_ms(3);
RA4=1;
PortB=MAP[DIS3];output_low(PIN_B7);
if(blink_min==1)
RA3=1;//DIS3
else RA3=0;//DIS3
delay_ms(3);
RA3=1;
PortB=MAP[DIS4];
if(blink_min==1)
RA2=1;//DIS4
else RA2=0;//DIS4
delay_ms(3);
RA2=1;
PortB=MAP[DIS5];output_low(PIN_B7);
if(blink_hour==1)
RA1=1;//DIS5
else RA1=0;//DIS5
delay_ms(3);
RA1=1;
PortB=MAP[DIS6];
if(blink_hour==1)
RA0=1;//DIS6
else {if (portb==0xC0) RA0=1; else RA0=0;}//DIS6

delay_ms(3);
RA0=1;//*/
if(count==0) {count=15;on_off=1;}
//-----------------------------------------------------------------exit:
count--;
}
//*************************************************
void init()
{
142
Trisd = 0x0F;
Trisb = 0x00;//output
Trisa = 0x00;
RD4=1;RD5=1;
init_ds1307();
}
//*************************************************
//END PROGRAM
TI LIU THC HNH CPLD

MC LC
I. GII THIU H THNG.......................................................................................77
143
II. M T CC THNH PHN CA H THNG................................................79

1. DIP SWITCH (DIPSW)......................................................................................79
2. JUMPERs............................................................................................................80
3. MCU SOCKETs..................................................................................................80
4. POWER SUPPLY...............................................................................................83
5. ON-BOARD PROGRAMMER..........................................................................83
6. REAL TIME CLOCK (RTC) DS1307................................................................84
7. RS-232 COMMUNICATION ............................................................................85
8. USB COMMUNICATION..................................................................................86
9. PS/2 COMMUNICATION..................................................................................87
10. DS1820 DIGITAL THERMOMETER.............................................................88
11. A-D CONVERTER INPUT..............................................................................89
12. DIRECT PORT ACCESS.................................................................................90
PHN II: THC HNH.................................................................................................92
Bi thc hnh s 1.......................................................................................................92
S DNG PHN MM WINPIC800 .......................................................................92
TRUY CP CNG VO RA S V IU KHIN LED 7 DON........................92
I. MC CH..........................................................................................................92
II. CHUN B.........................................................................................................92
III. THC HNH....................................................................................................92
Bi thc hnh s 2.....................................................................................................101
BIN I ADC, O IN P, NHIT ...........................................................101
HIN TH TRN LED V TRUYN THNG QUA RS232.................................101
I. MC CH........................................................................................................101
II. CHUN B.......................................................................................................101
III. THC HNH..................................................................................................101
Bi thc hnh s 3.....................................................................................................105
C PHM BM, IU KHIN RELAY .............................................................105
V C THI GIAN THC DS1307 HIN TH TRN LEB 7 ON..............105
I. MC CH........................................................................................................105
II. CHUN B.......................................................................................................105
III. THC HNH..................................................................................................106
PH LC......................................................................................................................112
Phn I: L thuyt chung v CPLD v VHDL................................................................146
Gii thiu.......................................................................................................................146
I. L thuyt chung v CPLD..........................................................................................147
1. Gii thiu chung....................................................................................................147
1.1. Lch s Logic kh trnh...................................................................................147
1.2. Thit b logic kh trnh phc tp CPLD.........................................................149
1.3. Mng cng Logic kh trnh min FPGA........................................................152
1.4. Hp nht cng ngh Logic.............................................................................154
2. Cc gii php cng ngh ca Xilinx......................................................................154
2.1. Gii thiu........................................................................................................154
2.2. Cc thit b ca Xilinx....................................................................................155
2.3. CPLD Xilinx...................................................................................................155
II. L thuyt chung v VHDL.......................................................................................162
1. Cc phng php thit k s truyn thng............................................................163
1.1. Phng php thit k dng hm Boolean.......................................................163
1.2. Phng php thit k da trn s (L s m rng ca phng php thit k
dng hm Boolean)................................................................................................163
144
1.3. Nhc im ca cc phng php thit k truyn thng...............................164

2. Phng php thit k s bng ngn ng m t phn cng....................................164
3. Cc qu trnh thc hin thit k s bng HDL trn FPGA....................................166
4. Ngn ng m t phn cng VHDL.......................................................................171
4.1. Gii thiu........................................................................................................171
4.2. Cu trc mt m hnh h thng m t bng VHDL.......................................173
Phn II: Thc hnh........................................................................................................177
Bi 1: Lm quen vi phng php thit k s bng VHDL trn phn mm ISE ca
Xilinx.............................................................................................................................177
1. Mc ch................................................................................................................177
2. Thit b s dng.....................................................................................................177
3. Ni dung thc hnh...............................................................................................177
3.1. To d n mi.................................................................................................177
3.2. Bin son HDL...............................................................................................181
3.3. Bin son lu trng thi.............................................................................186
3.4. Thit k VHDL mc nh...............................................................................193
3.5. Thit k s nguyn l mc nh.................................................................203
4. Cc bi thc hnh nng cao...................................................................................212
Bi 2: Tm hiu v cu trc phn cng X-Board...........................................................213
1. Mc ch................................................................................................................213
2. Thit b s dng.....................................................................................................213
3. Ni dung thc hnh...............................................................................................213
Bi 3: Thc hnh vi Project mu trn X-Board...........................................................220
1. Mc ch................................................................................................................220
2. Thit b thc hnh..................................................................................................220
Phn I: L thuyt chung v CPLD v VHDL

Gii thiu
D bn ang thit k logic dng cc phn t logic ri rc, hay da trn vi iu
khin, hay n gin hn l bn ang hc cch s dng phn mm thit k logic
tn tin nht th cun ti liu ny cng mang n cho bn nhiu th v v mt
cch thit k khc bit.
Cc thit b logic kh trnh c pht minh vo cui nhng nm 70, v t
c ci tin tr nn ph bin v tr thnh mt trong nhng lnh vc tng
trng nhanh nht trong cng nghip bn dn. Ti sao cc thit b logic kh trnh
li c s dng rng ri n vy? Lun i bn nhng nh thit k l thit b
logic kh trnh vi mm do linh ng ti a cung cp u im v thi gian
hon thnh sn phm a ra th trng v mc tch hp trong thit k. u
th hn na, h c th thit k v lp trnh i lp trnh li nhiu ln nng
cp cc tnh nng h thng.
145
Ti liu ny ni chi tit v lch s ca logic kh trnh, khi no th s dng v s

dng chng nh th no, cch ci t phm mm thit k bn min ph v bn
chc nng (Xilinx ISE WebPACK) v sau hng dn bn thc hin mt thit
k u tin ca ring mnh. Cng c nhng phn ni v thit k ban u theo s
mch v VHDL. Hy vng cc bn s tm thy s b ch trong quyn ti liu
ny v c l thuyt v thc hnh c th d dng xy dng cc thit k ca ring
mnh.
I. L thuyt chung v CPLD
1. Gii thiu chung
1.1. Lch s Logic kh trnh
Cui nhng nm 1970, cc linh kin logic chun thnh hnh v c thit k trn
cc bng mch in. Mt s ngi t vn : S th no nu nh thit k c
th thc hin kt ni cc ng mch trong mt thit b ln hn. iu ny s
cho php cc nh thit k tch hp nhiu linh kin logic chun trong mt thit b.
a ra cch ti u nht trong thit k, Ron Cline t hng Signetics (hng ny
sau c mua bi Philips v cui cng l Xilinx) to ra hai mng kh trnh
c pht trin t s kt hp gia 2 cng AND v OR cng nh l s phn b
cc s hng AND qua cc cng OR.
y l kin trc mm do nhng vo thi s tr ln u vo v u ra lm
cho cc linh kin hot ng kh chm.
c im PLA l:
- C hai mng kh trnh
- Bt k s kt hp no l ca cc cng AND v OR.
- Mt logic cao nht.
- Nhiu cu ch, chm hn PAL.
- Mng logic kh trnh.
146
Simple PLA.
Tip theo l MMI (c mua li bi AMD sau ) tham gia nh ngun th hai
trong mng PLA. Sau trong qu trnh ch to c s thay i nh v ci tin
thnh logic mng kh trnh PAL.
Kin trc mi ny khc vi PLA ch l mt trong cc mng kh trnh c c
nh - mng cng OR. Kin trc PAL nhanh hn, phn mm t phc tp hn,
nhng khng c linh ng nh PLA.
Cc kin trc khc nh PLD. Cc loi thit b c gi l Simple PLD
Mt mng kh trnh gm cc cng AND /OR c nh
Kt hp hn ch ca cc cng AND / OR
Mt logic trung bnh
t cu ch hn, v nhanh hn PLA (thi im , c ch to trn
quy trnh 10m).
Logic mng kh trnh
147
Kin trc SPLD (PAL).

Kin trc ny c mt mng li kt ni ngang v dc. mi kt ni c mt cu
ch. Vi s tr gip ca cng c phn mm, ngi thit k c th la chn cch
kt ni bng cch ph v tt c cc cu ch khng cn thit (vic ny c thc
hin bi mt b np, nhng by gi thng lm bng cng ngh ISP).
Cc chn u vo c ni ti cc kt ni theo chiu ngang. Cc ng chiu
ng c ni ti cc cng AND OR c gi l product term. Chng ln lt
c ni vi cc Flip-Flop chuyn dng. Cc cng ra ca cc Flip Flop ny
c ni vi cc chn u ra.
PLD cung cp hn 50 ln s cng trong mt b ng gi so vi cc thit b logic
ri rc. y l s ci tin cc ln v t thit b hn nhng c tin cy cao hn
i vi cc php logic chun.
Cng ngh PLD pht trin t nhng ngy u tin bi Xilinx bng vic to ra
nhng thit b CMOS tiu th nng lng cc nh, da trn cng ngh lu tr
flash. Flash PLD cho php kh nng lp trnh li nhiu ln gm c lp trnh v
xo bng in. qua ci thi m phi mt hn 20 pht xo bng UV eraser.
1.2. Thit b logic kh trnh phc tp CPLD
CPLD m rng mt ca SPLD, ni nm na n c mt vi khi PLD hay cn
gi l macrocells trong mt thit b n vi mc ch chung l to kt ni gia
cc mng bn trong. Cc ng logic n gin c th c thc hin vi mt
148
khi n. Logic tinh vi hn yu cu nhiu khi t hp v s dng vi mng kt

ni chung to ra nhng kt ni ny.
Cc CPLD c c im sau:
Lin kt ni chung trung tm
n gin, c kh nng nh thi
nh tuyn d dng
Cng c PLD thm vo lin kt ni
Tc ng ca cng phc tp, nhanh v gn
Kin trc CPLD.

CPLD hay ch x l nhng tc ng phc tp v rng vi tc sc bn v
d c 5 ns, tng ng 200MHz. M hnh nh thi ca CPLD c tnh ton
d dng, do vy trc khi bt u thit k bn c th tnh ton tc u vo u ra.
L do dng CPLD
CPLD cho php thit k d dng, chi ph pht trin thp hn, nhn c li
nhun, v a c sn phm ra th trng.
Thit k d: CPLD a ra cch thit k n gin thc hin thit
k. Khi mt thit k c m t bng s nguyn l, hay HDL, bn ch

n gin dng cng c pht trin CPLD ti u, khp, v m phng thit
k. Cng c thit k to ra mt file m s c s dng p dng tu
theo loi CPLD vi chc nng mong mun. iu cho php thc hin mt
149
nguyn mu phn cng v thc hin g li ngay t lc bt u. Khi cn

thit phi thay i, bn c th thay i bng cng c thit k, sau li
thc hin v kim tra thit k mi ngay lp tc.
Chi ph pht trin thp: CPLD lm cho ch ph pht trin gim
xung cn rt thp. V c th lp trnh li c, bn c th d dng v

khng tn km g thay i thit k ca bn. iu ny cho php ti u
thit k v thm nhng tnh nng mi v nng cp sn phm. Cng c
thit k CPLD tin cy v rt r (hoc min ph i vi trng hp Xilinx).
Theo cch truyn thng th ngi thit k phi i mt vi chi ph ln nh
lp li cng vic, tho ri v thi gian pht trin .Vi CPLD, bn c
nhng cch gii quyt linh ng hn v th trnh c nhiu li thit k
truyn thng.
Li ch kinh t ln: CPLD c mt chu trnh pht trin ngn, sn
phm nhanh chng chim lnh th trng v thu c li nhun nhanh.

Bi v CPLD c kh nng ti s dng, d thay i s dng ISP trn
internet. iu ny ln lt cho php bn gii thiu mt cc c tnh mi
mt cch d dng v nhanh chng to ra li nhun mi. Hng nghn cc
nh thit k ang s dng CPLD thm nhp th trng nhanh hn v
tn ti trong th trng lu hn bng vic tip tc nng cao sn phm ca
h.
Gim kch thc bo mch s dng: CPLD a ra mt mc tch hp
cao hn (tc l mt mc ln cc cng h thng trn mt n v din

tch). iu ny cung cp mt gii php hon chnh cho ngi thit k m
sn phm ca h phi thch hp vi cc ti liu nh nh km hoc c din
tch bo mch gii hn thc thi thit k logic. Xilinx CoolRunner II c
sn trong cc dng chip mi nht. V d, CP56 CPLD c cao ca chn
l 0,5mm v kch thc ch l 6x6 mm, to cho n s l tng trong sn
phm c cng sut thp. CoolRunner II CPLD cng c sn gi QF
(vung, phng) to ra dng nh nht trong cng nghip. QF32 c kch
thc ch l 5x5mm.
150
Cc kch thc ng gi khc nhau.

Chi ph ca ngi s dng: Chi ph ngi s dng c th nh
ngha nh l chi ph bo dng, sa cha hoc bo hnh sn phm.
Chng hn, mt thit k cn thay i cc phn cng phi c to ra
mt s t nguyn mu, chi ph th kh nh. Nhng khi mt s cc n
v cn thay i, chi ph c kh nng rt ln. Bi v CPLD c kh nng
ti lp trnh, khng i hi phi ti lp li phn cng, nh vy chi ph
rt t thay i thit k s dng chng.
tin cy: c tng ln bi s dng cng sut nh CoolRunnerCPLD
1.3. Mng cng Logic kh trnh min FPGA
Nm 1985 Xilinx gii thiu mt tng mi hon ton: kt hp gia vic iu
khin ca ngi dng v thi gian tip cn th trng ca cc PLD cng vi mt
v quan h vn li t mng cc cng.Ngi mua quan tm, v FPGA ra i.
By gi th Xilinx l s mt v nh cung cp FPGA trn th gii.
Mt FPGA thng l cu trc ca cc t bo logic (hay module) v c s lin
kt, cc lin kt hon ton iu khin c. iu ny c ngha l bn c th thit
k, lp trnh v thay i mch bt c lc no mun.
FPGA ngy nay ang vt qua gii hn 10 triu cng, bn c th thc hin
nhng tham vng ln. FPGA c c im nh sau:
nh tuyn da trn knh
nh thi gian theo v tr
Cng c phc tp hn CPLD
Ht mn.
X l thanh ghi nhanh
151
Kin trc FPGA.

T khi gii thiu dng Spartan ca dng FPGA, n gi Xilinx hon thin
mng cng v mi kha cnh gi c, cng, s cc u vo ra cng nh hiu
nng v chi ph.
C hai loi FPGA c bn: loi kh trnh da trn SRAM v loi OTP (lp trnh
mt ln). Hai loi FPGA ny khc nhau v vic thc hin cc t bo logic v c
cu s dng to nn kt ni trong thit b.
Loi u th hn c l loi da trn SRAM v c th lp trnh li nu bn chn.
Thc t th mt SRAM FPGA c lp trnh li mi ln khi ng, v FPGA l
mt vi mch lu tr tch hp. iu ny gii thch ti sao cn c mt s PROM
hay h thng nh vi mi SRAM FPGA.
SRAM Logic Cell.

152
Trong cc t bo logic, thay cho cc cng thng thng th mt LUT xc

nh u ra da trn gi tr u vo (Trong t bo logic SRAM trn th 6 s
kt hp khc nhau ca 4 u vo s xc nh gi tr u ra). Cc bit trong SRAM
cng c dng kt ni.
Cc OTP FPGA dng cc i cu ch (khc vi cu ch, y cc kt ni c
to ra ch khng b ct nh trong qu trnh lp trnh) to nn nhng kt ni c
nh trong vi mch. Tuy vy th cc OTP FPGA khng cn SPOM hay cc
phng tin khc ti chng trnh v FPGA. Tuy nhin mi khi mun thay
i thit k, bn phi thay chip khc. Cc t bo logic OTP cng tng t nh b
PLD vi cc b cng v cc flip-flop chuyn dng.
OTP Logic Cell.

1.4. Hp nht cng ngh Logic
S hp nht ca logic chun h 74 vo trong mt CPLD gi r l mt gi hp
dn. Khng ch l vn tit kim din tch mch in v chi ph h thng ca
bn c gim m bn cn mua v d tr c mt din tch rng ln ca hn
20 linh kin logic tin nh ngha.
Bng vic s dng cc thit b ca Xilinx CoolRunner bn c th c nhng thun
li t cng sut tiu th thp v gim c s to nhit nng. iu ln lt
dn n s gim chi ph khi phi ch to b tn nhit v to ra b sn phm c
tin cy cao hn.
2. Cc gii php cng ngh ca Xilinx
2.1. Gii thiu
Gii php logic kh trnh ca Xilinx gip ti thiu ri ro cho vic ch to thit b
in t bng cch rt ngn thi gian cn thit pht trin sn phm v a ra th
trng. Bn c th thit k v kim tra mch in duy nht trong cc thit b
logic kh trnh ca Xilinx nhanh hn so vi vic la chn cc phng php thit
153
k truyn thng nh l mng cng logic c nh v lp trnh mt n. Hn na cc

thit b ca Xilinx l cc phn chun m ch cn lp trnh, bn khng mt thi
gian ch i c c nguyn mu hoc khng phi tr tin cho chi ph nghin
cu khng tp trung.
Nhng khch hng ng dng logic kh trnh ca Xilinx trong cc sn phm
nhiu mng th trng. Trong c cch lnh vc nh x l d liu, vin thng,
iu khin cng nghip, my cng c, in t gia dng, t ng ho, quc phng,
v hng khng.
Nhng sn phm mi nhn, nhng gii php phn mm ti tn v s h tr k
thut trn th gii to nn mt gii php tng th m Xilinx cung cp. Gii php
phn mm l mu cht thnh cng ca d n. Gii php phn mm ca Xilinx
cung cp cng c hu dng lm cho vic thit k logic kh trnh tr nn n
gin. Nhng lung thit k n phm, nhng h tr online c tch hp, nhng
ti liu a phng tin, v cc cng c tng tc t ng v t ng c hiu sut
cao gip bn t c cc kt qu ti u.Thm na, cng ngh logic kh trnh v
s linh ng tch bit ca cp pht c chn lc ca cng ngh tch hp EDA l
cc mng ng dng rng ri nht trong cng nghip Xilinx ang pht trin v
cng ngh kch hot phn cng trong cc h thng ca Xilinx c nng cp
tnh iu khin i vi cc loi mng, k c internet, thm ch c sau khi vt
dng vn c chuyn cho khch hng. Xilinx-H thng c th nng cp trc
tuyns cho php cc nh my sn xut thit b thm t xa nhng tnh nng v
c im cho h thng ci t hoc sa li m khng cn thay i phn cng.
2.2. Cc thit b ca Xilinx
2.3. CPLD Xilinx
Hin ti Xilinx chia cc sn phm CPLD ca mnh ra lm 2 loi: XC9500 v
CoolRunner. Ti liu ny tp trung ch yu l hai dng ph bin nht l
XC9500XL v CoolRunner II. c th la chn c CPLD cho mnh hy
xem phn tnh nng sn phm bn di xc nh dng sn phm ph hp vi
ng dng ca bn. Bn cng nn lu chn cn thn tm c thit b tt nht
cho tiu chun thit k ca bn.
154
Cc thit b ca Xilinx.
Cc tnh nng sn phm
Thit b XC9500 - Dng XC9500XL ISP CPLD: tc cao, chi
ph thit k thp.
CoolRunner-II: tiu th nng lng cc t, dn u trong cc thit
b cm tay. Vi dng d tr nh c uA v tiu th cng sut nh nn

CoolRunner II c bit ph hp vi cc ng dng cm tay chy pin, hay
nhng ng dng c ngun cung cp nhy cm.
Ch chn la
tm c thit b tt nht cho cc tiu chun thit k ca bn, cn ch ti
cc chi tit thit k v c im sn phm c nhng thng tin chi tit v thit
b mnh cn.
Mt : Mi phn u c mt lng cng hay c lng mt
logic mi phn.
S lng thanh ghi: m s thanh ghi cn cho b m, my trng
thi, thanh ghi v kha. S lng cc macrocell cn thit trong mt thit

b.
S lng chn Vo/Ra: Mch thit k cn bao nhiu li vo v bao
nhiu li ra
155
Tc : Thnh phn no s quyt nh t hp nhanh nht trong
thit b ca bn s quyt nh Tpd (c ns) ca thit b. Mch dy nhanh

nht cho bit fMax ca thit b.
ng gi: Tc ng ca cc iu kin in c, v cc kiu ng gi
khc nhau.
Cng sut nh: Bn s dng ngun pin hay ngun cc. Thit k
ca bn c yu cu cng sut thp nht khng nh nht . Bn c quan tm

n gim nhit lng ca thit b khng?
Cu trc ca h thng bc cao: C nhng thit b nhiu in th
no trn bng? Bn mun i mc gia cc thit b khng? Bn c mun

to ra cc xung vung clock? Bn c cn giao din cho b nh v cc chip
vi x l khng?
Gii thiu CPLD cng sut nh CoolRunner-II
CoolRunner-II CPLDs kt hp gia ngun tiu th cc thp v tc
cao, nhiu cng vo ra trn mt thit b. Dng CoolRunner-II c t 32

n 512 macro cell. CRII-CPLD l nt c bit ca cng ngh RealDigital
cho php cc thit b gn nh khng tiu th ngun ch ch. iu
ny lm cho n tr thnh l tng cho cc mng th trng cc thit b
in t cm tay, chy pin ang tng trng nhanh nh: Laptop PCs, in
thoi cm tay, PDA, tr chi in t,...
Cc CPLD cng c dng nh ngun kh n nh trong qu trnh
hot ng thc t (so snh vi CPLD thng thng). y l mt c im

quan trng cho cc thit b c hiu sut cao, nhy cm vi nhit nh l
cc chuyn mch vin thng, h thng hi ngh bng hnh nh, cc b m
phng, cc b kim tra u cui...
156
Dng CR II ca CPLD c dng cho cc ng dng cng sut
nh bao gm: ng dng v ngun, thit b cm tay, di ng. Mi phn

ca dng gm cng ngh thit k RealDigital, kt hp cng sut nh vi
tc nhanh. Vi k thut thit k ny, cc dng yu cu tc tht t
chn ny ti chn kia khong 5s, trong khi ngun cung cp cng lc nh
hn 16A (ch) m khng cn power down bits c bit no. Bng cch
thay th phng php khuch i thng thng thc hin cc php
ton logic (mt k thut c s dng trong PLD k t k nguyn lng
cc) vi mt chui cng CMOS thun ty, ngun ng cng thp hn bt
k CPLD cng cnh tranh.
Cc CoolRunner-II CPLDs cp pht tc cao v khng rng buc
nhiu vi cc h XC9500/XL/XV CPLD v s a nng caXPLA3 cng

sut nh. iu ny c ngha l cc thit b ging nhau c dng cho cc
phng tin truyn d liu tc cao, h thng my tnh, sn phm cm
tay cng vi nhng tin dng thm vo ca ISP. Cng sut tiu th nh v
tc x l nhanh kt hp vo trong mt dng sn phm vi chi ph thp
v d s dng nn rt d s dng v gi c cng thc t. Xilinx to ra
Fast Zero Power c quyn vi cng sut nh m khng cn cc phng
php thit k c bit no.
K thut clocking v cc c tnh tit kim cng sut khc m
rng cc khi cng sut ca bn. Nhng c im thit k ny c h tr

bi phn mm Xilinx ISE 4.li. Hnh di ch ra mt s yu cu ca gi
CoolRunner-II CPLD vi cc kch thc. Tt c cc b ny l cc gi gn
157
mt vi nhau, vi hn mt na l cng ngh li hnh trn. Cc ng gi

siu nh ny gii hn dung lng ln nht trn mt din tch nh nht c
th.
Cng ngh CMOS c dng trong CoolRunner-II CPLD pht ra
nhit lng rt nh, cho php s dng nhng b ng gi nh trong sut

qu trnh hot ng tc cao. Mi ng gi c t nht hai mt tn
ti, vi 3 mt nh trongVQ100 (100-chn, 1.0mm QFP), TQ144(144chn,1.4mm QFP) v FT256 (256-chn,1.0mm-spacing FLBGA). Loi
FT256 c bit ph hp vi cc sn phm cm tay mng vi yu cu mt
logic cao.
Bng 2-1 ch ra s phn b ca cc c im ni tri thng qua
dng CoolRunner-II CPLD. H ny c nhng c im c bn v ng

nht trong vng hiu dng nht. V d, n c th khng hp vi 4 nhm
I/O trn cc b 32 v 64 marcocell nhng li ng cho cc b 384 v 512
macrocell.
Cc nhm I/O l tp hp ca cc chn I/O s dng bt k mt trong
cc tp con ca chun in th thch hp tc l cng mc VCCIO. Kh

nng phn chia nh thi th km hiu qu i vi cc thit b nh nhng
li hu dng v thch hp cho nhng thit b ln hn. Cng ngh
DataGATE, mt kh thi cht u vo tit kim nng lng th rt
tt cho cc thit b ln nhng li c nhng ng dng gii hn vi cc thit
b nh.
158
M t kin trc CoolRunner-II
CoolRunner-II CPLD l dng ng b mc cao ca thit b
nhanh, cng sut thp. Kin trc c bn l kin trc CPLD truyn thng,
kt hp cc macrocell thnh nhng khi chc nng c ni vi mt ma
trn nh tuyn kt ni gi l Xilinx Advanced Interconnect Matrix
(AIM). Cc b c trng ny dng cu hnh PLA cho php tt c nhng
product term c nh hng v chia s trong bt k cc macrocell no
ca cc macrocell ca khi chc nng ny.
Phn mm thit k c th tng hp mt cch hiu qu v ti u
logic sau ph hp vi khi chc nng v c ni vi nhau c th

tn dng lng ln cc ngun thit b. Phn mm ny qun l cc thay i
thit k rt d v t ng, tn dng 100% cc b nh thi ca PLA trong
mi khi chc nng. Phn mm thit k t ng qun l cc ngun thit b
nn chng ta ch c th biu th thit k s dng cc cu to chung hon
ton m khng cn nhng thng tin v kin trc hay cu to. Nu c kinh
nghim hn chng ta c th tham kho thm cc thng tin hiu su hn
na v vic chn phn mm cng nh a ra c kt qu chnh xc.
Hnh 2-5 ch ra kin trc bc cao mi khi khi chc nng c kt ni ti cc
chn v lin kt vi chn khc trong ma trn lin kt ni b. Mi khi chc nng
cha 16 macrocell
159
Khi chc nng CoolRunner-II
Cc khi chc nng CoolRunner-II CPLD cha 16 macrocell vi
40 v tr tn hiu chuyn ti cc kt ni v thit lp logic. C cu logic

bn trong gm 56 PLA. Tt c cc khi chc nng, khng k s cha
trong thit b, u cng loi vi nhau. mc cao th cc p-term tn ti
trong mt PLA. M hnh thc s rt linh ng v thit thc khi c so
snh vi cc khi chc nng p-term c nh v p- term tng. Loi CPLD
c in c mt vi p - term dnh cho cc ng tc cao i vi cc
macrocell c a ra. Chng da vo vic bt cc p - term khng s
dng t nhng macrocell cn k m rng product term khi cn. Kt qu
ca kin trc ny l m hnh thi gian bin thin v kh nng ca logic bt
kh dng trong khi chc nng.
PLA khc v tt hn nhiu. Th nht l bt k p-term no cng c
th lin kt vi mt cng OR bn trong macrocell khi chc nng. Th

hai, bt k chc nng logic no cng c nhiu p- term cn thit ni vi n
trong khi chc nng, ti mt mc gii hn cao hn 56. Th ba, bn c
th dng li product term chc nng OR macrocell kp nn trong mt
khi chc nng bn c th cn to mt sn phm logic c bit mt ln,
nhng cng c th dng li n ti 16 ln trong khi chc nng. Bnh
thng vic ny cng rt d vi phn mm ph hp xc nh cc product
term c th c chia s.
160
1.
Phn mm ny t rt nhiu chc nng c th a vo trong mt
khi chc nng. Khng cn thit t cc chc nng ca macrocell gn
nhau hay c bt k cc hn ch no khc tr vic t n trong cng mt
khi c x l bi phn mm. Cc chc nng khng cn dng chung
xung nhp, chung set/reset hay chung li ra c th c nhng ng dng
y ca PLA. Hn na, mi p- term ti cng thi gian tr nh trc.
Khng c nhng b cng thi gian ni tng t nhiu hn product term
trong khi chc nng. Khi khi chc nng p- term t c, th mt b
nh thi lin kt nh nh tuyn tn hiu ti mt khi chc nng khc
tip tc to mch logic. Phn mm thit k Xilinx iu khin vic ny mt
cch t ng.
II. L thuyt chung v VHDL
Hin nay cc mch tch hp ngy cng thc hin c nhiu chc nng hn, do
chng ngy cng tr nn phc tp hn. Cc phng php thit k mch truyn
thng nh dng ti thiu ho hm Boolean hay dng s cc phn t khng
cn p ng c cc yu cu t ra khi thit k. Hn na cc mch thit k ra
yu cu phi c th nghim k lng trc khi a vo ch to hng lot. Hn
na cn phi xy dng mt b ti liu hng dn vn hnh h thng hon chnh
d hiu v thng nht. V th ngi ta thng s dng cc ngn ng m phng
phn cng lm phng tin thit k, m phng th nghim cc h thng s.
161
1. Cc phng php thit k s truyn thng

1.1. Phng php thit k dng hm Boolean
Tt c cc mch da trn cc phn t logic c bn gm cng logic v cc mch
flip-flop u c th thit k bng cc hm Boolean. C nhiu phng php
c s dng ti thiu ho hm Boolean nhm tng tnh hiu qu s dng cc
phn t logic, chng hn nh phng php dng ba ccn. V mt l thuyt bt
k h thng s no cng c th biu din di dng cc hm Boolean. Nhng
vic ti thiu ho cng nh x l hng nghn hm logic r rng l khng thc t.
Trong khi cc yu cu thit k h thng hin nay i hi ti hng nhiu nghn
hm Boolean.
Minh ha cho phng php thit k dng hm Boolean.

1.2. Phng php thit k da trn s (L s m rng ca phng php thit
k dng hm Boolean)
Trong phng php ny, ngi thit k c th s dng thm cc mch chc nng
thng dng khc ngoi cc phn t c bn l cng v flip-flop. Nh vy, phng
php ny cho php thit k thit k h thng mt cch c cu trc. Phng php
thit k da trn s c dng ph bin v c rt nhiu phn mm thit k
cung cp cho ngi thit k mt giao din thit k ho thun tin. Trong nhiu
nm phng php ny l phng php c s dng ch yu trong ngnh cng
nghip ch to phn cng s.
162
Minh ha cho phng php thit k dng s .

1.3. Nhc im ca cc phng php thit k truyn thng
Mc d c u im l d hiu v d s dng, phng php thit k dng hm
Boolean v phng php thit k da trn s c mt s nhc im. Nhc
im ln nht ca cc phng php ny l chng ch m t h thng di dng
mng cc phn t ni vi nhau. Nhn vo mt h thng c m t bng hai
phng php trn (di dng hm Boolean hay dng s ) ta khng th lp tc
ch ra c cc ch tiu v chc nng chung nht ca h thng. thit k mt
h thng bng phng php truyn thng, ngi thit k cn phi i qua hai bc
thc hin hon ton th cng: l chuyn t cc yu cu v chc nng ca h
thng sang biu din h thng bng hm Boolean, sau chuyn t hm Boolean
sang s mch ca h thng. Cng tng t khi cn hiu c mt h thng
ngi phn tch cn phn tch s mch ca h thng chuyn n thnh cc hm
Boolean sau mi lp li c cc chc nng, hot ng ca h thng. V cc
bc ni trn hon ton phi thc hin th cng khng c bt k s tr gip no
ca my tnh. y ngi thit k ch c th s dng my tnh lm cng c h
tr trong vic v s mch ca h thng (dng cng c CAE Computer
Aided Tool) v chuyn t s mch sang cng c tng hp mch vt l (dng
cng c Synthesis).
Mt nhc im khc ca phng php thit k truyn thng l s gii hn trong
phc tp ca h thng. Phng php dng hm Boolean ch c th dng
thit k cc h thng ln nht biu din bi vi trm hm. Phng php da trn
s ch c th dng thit k ln nht cha ti 6000 phn t.
2. Phng php thit k s bng ngn ng m t phn cng
163
Ngn ng m t phn cng gii quyt c nhc im ln nht ca cc phng

php thit k trc y. Nu cc phng php c i hi phi chuyn i t m
t h thng (cc ch tiu v chc nng ca h thng) sang tp hp cc hm logic
bng tay th bc chuyn i hon ton khng cn thit khi dng ngn ng
m phng phn cng. Hu ht cc cng c thit k dng ngn ng m phng
phn cng u cho php s dng biu trng thi (finite-state-machine) cho cc
h thng tun t cng nh cho php s dng bng chn l cho h thng tng hp.
Vic chuyn i t cc biu trng thi v bng chn l sang m ngn ng m
phng phn cng c thc hin t ng. Ngn ng m phng phn cng c
dng nhiu thit k cho cc thit b logic lp trnh c (PLD-Programmable
Logic Device) t loi n gin n cc loi phc tp nh ma trn cng lp trnh
c (Field Programmable Gate Array).
Phng php thit k s bng ngn ng m t phn cng c nhiu u im hn
so vi phng php thit k truyn thng. Hy ly b nhn 16x16 lm v d so
snh. M b nhn thng phc tp v mt sp xp cc b cng v thanh ghi vic
ny yu cu kh nhiu cng. V d ca chng ta c hai u vo 16 bt (A v B)
v u ra 32 bit tng cng c 64 cng vo/ra. Mch ny yu cu c 6000 cng.
Thc hin theo s mch cc cng s phi c ly ra, t vo bn v v ni
vi nhau sau ni vi cc cng vo ra. Nh vy s phi mt khong 3 ngy lm
vic.
Design Specification Multiplier.
164
Vic thc hin bng HDL, cng vi khong 6000 cng, cn 8 dng lnh v c
th thc hin trong 3 pht. Tp ny cha tt c nhng thng tin cn thit nh
ngha mt b nhn 16x16. Ngoi vic tit kim thi gian ra, phng php HDL
cn c lp hon ton vi nh cung cp, y cng l mt li th ca HDL.
to ra b nhn 32x32 bn n gin ch cn thay i mt cht xu. i vi
phng php v mch, cn phi c 3 bn sao ca thit k 30 trang trc , tc
l 90 trang cn phi v li, sau nh a ch li cho b rng ng bus ln hn.
iu ny c l phi cn n 4 gi ch bn bng phng php ho. Theo cch
m t bng phng php HDL th vn ch l thay i ung bus t 15 thnh
31 dng th 2 v t 31 thnh 63 dng th 3. Vic ny c l ch mt n 6
giy. Sau y l minh ho ca HDL khi thay i 2 b nhn trn. V d thay i
file HDL:
Before (16 x 16 multiplier):
entity MULT is
port(A,B:in std_logic(15 downto 0);
Y:out std_logic(31 downto 0));
end MULT;
architecture BEHAVE of MULT is
begin
Y <= A * B;
end BEHAVE;
After (32 x 32 multiplier):
entity MULT is
port(A,B:in std_logic(31 downto 0);
Y:out std_logic(63 downto 0));
end MULT;
architecture BEHAVE of MULT is
begin
Y <= A * B;
end BEHAVE;
3. Cc qu trnh thc hin thit k s bng HDL trn FPGA
Cc bc chnh thc hin thit k s dng ngn ng m t phn cng trn
FPGA c m t trn hnh v.
165
Quy trnh thit k FPGA.

Qu trnh 1: M t ban u v thit k (Specification). Khi xy dng mt chip
kh trnh (FPGA) vi ngha dnh cho mt ng dng ring bit, v xut pht t
mi ng dng trong thc tin cuc sng, s t ra yu cu phi thit k IC thc
hin ti u nht nhng ng dng . Bc u tin ca quy trnh thit k ny c
nhim v tip nhn cc yu cu ca thit k v xy dng nn kin trc tng qut
ca thit k. Cc bc gm:
1. M t thit k(Design Specification): Trong bc ny, t nhng yu cu
ca thit k v da trn kh nng ca cng ngh hin c, ngi thit k kin
166
trc s xy dng nn ton b kin trc tng quan cho thit k. Ngha l trong
bc ny ngi thit k kin trc phi m t c nhng vn sau:
- Thit k c nhng khi no?
- Mi khi c chc nng g?
- Hot ng ca thit k v ca mi khi ra sao ?
- Phn tch cc k thut s dng trong thit k v cc cng c, phn
mm h tr thit k.
Mt thit k c th c m t s dng ngn ng m t phn cng, nh
VHDL hay Verilog HDL hoc c th m t qua bn v mch (schematic
capture). Mt thit k c th va bao gm bn v mch m t s khi
chung, va c th dng ngn ng HDL m t chi tit cho cc khi trong
s .
2. M phng chc nng (Function simulation): Sau khi m t thit k, ngi
thit k cn m phng tng th thit k v mt chc nng kim tra thit k
c hot ng ng vi cc chc nng yu cu.
3. Tng hp logic (Logic Synthesis): Tng hp logic l qu trnh tng hp
cc m t thit k thnh s b tr mch (netlist). Qu trnh chia thnh 2
bc: chuyn i cc m RTL, m HDL thnh m t di dng cc biu thc
i s Boolean v da trn cc biu thc ny kt hp vi th vin t bo
chun sn c tng hp nn mt thit k ti u.
Logic Synthesis
VHDL description
Circuit netlist
architecture MLU_DATAFLOW of MLU is

signal A1:STD_LOGIC;
signal B1:STD_LOGIC;
signal Y1:STD_LOGIC;
signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;
begin
A1<=A when (NEG_A='0') else
not A;
B1<=B when (NEG_B='0') else
not B;
Y<=Y1 when (NEG_Y='0') else
not Y1;
MUX_0<=A1 and B1;
MUX_1<=A1 or B1;
MUX_2<=A1 xor B1;
MUX_3<=A1 xnor B1;
with (L1 & L0) select
Y1<=MUX_0 when "00",
MUX_1 when "01",
MUX_2 when "10",
MUX_3 when others;
end MLU_DATAFLOW;
ECE 545 Introduction to VHDL
57
Logic Synthesis.
167
II. Hiu chnh cc kt ni (Datapath Schematic): Nhp netlist v cc

rng buc v thi gian vo mt cng c phn tch thi gian (timing
analysic). Cng c phn tch ny s tch ri tt c cc kt ni ca thit
k, tnh thi gian tr ca cc kt ni da trn cc rng buc. Da trn
kt qu phn tch (report) ca cng c phn tch, xc nh cc kt ni
khng tha mn v thi gian. Ty theo nguyn nhn dn n khng
tha mn m ta c th vit li m v tin hnh li tng hp logic hoc
hiu chnh li cc rng buc.
Qu trnh 2: Thc thi (Implementation). Ta c s b tr netlist m t tng
th thit k ti mc cng (ch gm cc cng logic c bn v cc mch logic khc
nh: MUX). Qu trnh ny s t s netlist ny ln chip, gi l qu trnh thc
thi (Device Implementation). Qu trnh ny gm cc bc:
III. nh x (mapping hay cn gi fitting - n khp): Chun b d liu
u vo, xc nh kch thc cc khi. Cc khi ny s phi ph hp
vi cu trc ca 1 t bo c bn ca FPGA. (gm nhiu cng logic) v
t chng vo cc v tr ti u cho vic chy dy.
Mapping
LUT0
LUT4
LUT1
FF1
LUT5
LUT2
FF2
LUT3
63
Mapping.
IV.t khi v nh tuyn (Place & Route):
t khi tc l t cc khi nh x vo cc t bo (cell) v tr ti u cho vic
chy dy.
168
Placing
FPGA
CLB SLICES
64
Placing.
nh tuyn tc l thc hin vic ni dy cc t bo.
Routing
FPGA
Programmable Connections
65
Routing.
169
thc hin vic ny, chng ta cn c cc thng tin sau:

- Cc thng tin vt l v th vin t bo, v d kch thc t bo, cc im
kt ni, nh thi, cc tr ngi trong khi i dy.
- Mt netlist c tng hp s ch ra chi tit cc instance v mi quan h
kt ni bao gm c cc ng dn b hn ch trong thit k.
- Tt c cc yu cu ca tin trnh cho cc lp kt ni, bao gm cc lut
thit k cho cc lp chy dy, tr khng v in dung, tiu th nng lng,
cc lut v s dn in trong mi lp.
Qu trnh 3: Np (download) v lp trnh (program). Sau qu trnh thc hin,
thit k cn c np vo FPGA di dng dng bit (bit stream). Qu trnh np
thit k (download) vo FPGA thng np vo b nh bay hi, v d nh
SRAM. Thng tin cu hnh s c np vo b nh. Dng bit c truyn lc
ny s mang thng tin nh ngha cc khi logic cng nh kt ni ca thit k.
Tuy nhin, lu rng, SRAM s mt d liu khi mt ngun nn thit k s khng
lu c n phin lm vic k tip.
Lp trnh (program) l thut ng m t qu trnh np chng trnh cho cc b
nh khng bay hi, v d nh PROM. Nh vy, thng tin cu hnh vn s c
lu tr khi mt ngun.
4. Ngn ng m t phn cng VHDL
4.1. Gii thiu
VHDL l vit tt ca cm t Very High Speed Intergrated Circuit Hardware
Description Language - ngn ng m t phn cng cho cc mch tch hp tc
rt cao. VHDL l ngn ng m phng phn cng c pht trin dng cho
chng trnh VHSIC (Very High Speed Intergrated Circuit) ca b quc phng
M.Mc tiu ca vic pht trin VHDL l c c mt ngn ng m phng phn
cng tiu chun v thng nht cho php pht trin th nghim cc h thng s
nhanh hn cng nh cho php d dng a cc h thng vo ng dng trong
thc t. Ngn ng VHDL c ba cng ty Intermetics, IBM v Texas
Instruments bt u nghin cu pht trin vo 7/1983. Phin bn u tin c
cng b vo 8/1985. Sau VHDL c xut t chc IEEE xem xt thnh
mt tiu chun. Nm 1987, a ra tiu chun v VHDL tiu chun IEEE1076-1987.
VHDL c pht trin gii quyt cc kh khn trong vic pht trin, thay i
v lp ti liu cho cc h thng s. Nh ta bit, mt h thng s c rt nhiu
170
ti liu m t. c th vn hnh bo tr sa cha mt h thng ta cn tm hiu

ti liu k lng. Vi mt ngn ng m phng phn cng tt vic xem xt cc
ti liu m t tr nn d dng hn v b ti liu c th c thc thi m
phng hot ng ca h thng. Nh th ta c th xem xt ton b cc phn t ca
h thng hot ng trong mt m hnh thng nht.
Trc khi VHDL ra i, c nhiu ngn ng m phng phn cng c s dng
nhng khng c mt tiu chun thng nht. Cc ngn ng m phng phn cng
c pht trin phc v cc b m phng chy chng. V cc ngn ng m
phng phn cng c cc nh cung cp thit b pht trin, nn mang cc c
trng gn vi cc thit b ca nh cung cp v thuc s hu ca nh cung cp.
Trong khi , VHDL c pht trin nh mt ngn ng c lp khng gn vi
bt k mt phng php thit k, b m phng hay cng ngh phn cng no.
Ngi thit k c th t do la chn cng ngh, phng php thit k trong khi
vn s dng mt ngn ng duy nht.
VHDL c mt s u im hn hn cc ngn ng m t phn cng khc l:
Tnh cng cng: VHDL c pht trin di s bo tr ca chnh
ph M v hin nay l mt tiu chun ca IEEE, VHDL khng thuc s

hu ca bt k c nhn hay t chc no. Do VHDL c h tr ca
nhiu nh sn xut thit b cng nh nhiu nh cung cp cng c thit k
m phng h thng. y l mt u im ni bt ca VHDL, gip VHDL
tr nn ngy cng ph bin.
Kh nng h tr nhiu cng ngh v phng php thit k: VHDL
cho php thit k bng nhiu phng php nh phng php thit k t
trn xung, hay t di ln da vo cc th vin c sn. VHDL cng h
tr cho nhiu loi cng ngh xy dng mch nh s dng cng ngh ng
b hay khng ng b, s dng ma trn lp trnh c hay s dng mng
logic ngu nhin. Nh vy VHDL c th phc v tt cho nhiu mc ch
thit k khc nhau, t vic thit k cc phn t ph bin n vic thit k
cc IC ng dng c bit (Application Specified IC).
c lp vi cng ngh: VHDL hon ton c lp vi cng ngh
ch to phn cng. Mt m t h thng dng VHDL thit k mc cng

c th c chuyn thnh cc bn tng hp mch khc nhau tu thuc vo
cng ngh ch to phn cng no c s dng (dng CMOS, nMOS,
hay GaAs). y cng l mt u im quan trong ca VHDL n cho php
ngi thit k khng cn quan tm n cng ngh phn cng khi thit k
171
h thng, nh th khi c mt cng ngh ch to phn cng mi ra i n

c th c p dng ngay cho cc h thng thit k.
Kh nng m t m rng: VHDL cho php m t hot ng ca
phn cng t mc h thng s (hp en) cho n mc cng. VHDL c

kh nng m t hot ng ca h thng trn nhiu mc nhng ch s dng
mt c php cht ch thng nht cho mi mc. Nh th ta c th m
phng mt bn thit k bao gm c cc h con c m t mc cao v
cc h con c m t chi tit.
Kh nng trao i kt qu: V VHDL l mt tiu chun c chp
nhn, nn mt m hnh VHDL c th chy trn mi b m phng p ng

c tiu chun VHDL-cc kt qu m t h thng c th c trao i
gia cc nh thit k s dng cng c thit k khc nhau nhng cng tun
theo chun VHDL. Cng nh, mt nhm thit k c th trao i m t
mc cao ca cc h thng con trong mt h thng; trong khi cc h con
c thit k c lp.
Kh nng h tr thit k mc ln v kh nng s dng li cc thit
k: VHDL c pht trin nh mt ngn ng lp trnh bc cao, v vy n

c th s dng thit k mt h thng ln vi s tham gia ca mt nhm
nhiu ngi. Bn trong ngn ng VHDL c nhiu tnh nng h tr vic
qun l, th nghim v chi s thit k. VHDL cng cho php dng li cc
phn c sn.
4.2. Cu trc mt m hnh h thng m t bng VHDL
Thng thng mt m hnh VHDL bao gm ba phn: thc th, kin trc v cc
cu hnh. Trong mt s trng hp m hnh cn c thm phn cc mi trng
kim tra.
4.2.1. Thc th (Entity)
Khai bo thc th trong VHDL l cu lnh nh ngha cc ch tiu pha ngoi ca
mt phn t hay mt h thng. Cc thng tin c trong phn khai bo thc th cho
php kt ni phn t (h thng) m thc th i din vi cc phn t (h
thng) khc. Thc cht vic khai bo thc th chnh l khai bo giao din ca h
thng vi bn ngoi. Hot ng thc cht ca h thng khng c m t trong
khai bo thc th. Di y l mt v d khai bo thc th cho mt cng NAND.
172
LIBRARY IEEE;
USE
IEEE.std_logic_1164.ALL;
ENTITY
nand IS
GENERIC
(delay : = 5 ns);
PORT
(a
: IN
std_logic;
: IN
std_logic;
: OUT std_logic);
END nand;
Khai bo mt thc th NAND.
Cu lnh LIBRARY IEEE v USE IEEE.std_logic_1164.ALL cho php thc th
s dng cc nh ngha trong th vin v cc tiu chun ca IEEE. Khai bo thc
th bao gm tn ca thc th v mt tp cc cng v phn chung. Trong phn
chung GENERIC l cc hng s c truyn cho phn t (h thng). Phn chung
c th coi l cc tham s nh trc ca phn t, chng hn nh tr. Cc cng
l phn giao din vo ra ca phn t. Cc cng c th tng ng vi cc chn IC,
hay cc u ni trn bng mch. Cc cng c khai bo l cng vo, cng ra,
cng hai chiu hay b m.
4.2.2. Kin trc (Architecture)
Mt khai bo thc th u phi i km vi t nht mt kin trc tng ng.
VHDL cho php khai bo nhiu kin trc cho mt thc th. Mt khai bo kin
trc c th bao gm cc khai bo v cc tn hiu bn trong, cc phn t bn trong
h thng, hay cc hm v th tc m t hot ng ca h thng. C hai cch m
t kin trc ca mt phn t (h thng) l m t theo m hnh hot ng hay
m t theo m hnh cu trc. Tuy nhin mt h thng c th bao gm c m t
theo m hnh hot ng v m t theo m hnh cu trc.
a, M t kin trc theo m hnh hot ng
173
M hnh hot ng m t cc hot ng ca h thng (h thng p ng vi cc

tn hiu vo nh th no v a cc kt qu g ra u ra) di dng cc cu lnh
cu ngn ng lp trnh bc cao. Cc cu lnh c th l PROCESS, WAIT, IF,
CASE, FOR-LOOP...V d, kin trc ca cng NAND ni trn c th m t theo
m hnh hot ng nh sau.
ARCHITECTURE
behaviour
OF
IS
BEGIN
c
<=
NOT(a AND b) AFTER
delay;
END behavour;
Ta thy kin trc ca phn t NAND c mt lnh gn tn hiu m t chc nng
ca phn t. Cu lnh ny c thc thi khi mt trong hai cng a,b thay i gi
tr. V cu lnh gn c tr, tc l tn hiu bn v tri s thay i tng ng
sau thi gian tr.
b, M t kin trc theo m hnh cu trc
M hnh cu trc ca mt phn t (h thng) c th bao gm nhiu cp cu trc
bt u t mt cng logic n gin xy dng m t cho mt h thng hon
thin. Thc cht ca vic m t theo m hnh cu trc l m t cc phn t con
bn trong h thng v s kt ni ca cc phn t con . Nh vi v d m t m
hnh cu trc mt flip-flop RS gm hai cng NAND nh sau.
M t kin trc Flip Flop RS theo m hnh cu trc.
174
4.2.3. Cu hnh
Vic khai bo cu hnh tng t nh vic lit k cc phn ca bn thit k. Khai
bo cu hnh thc cht l ch ra kin trc no c gn vi thc th no. Nh vy
cc kin trc khc nhau c th cng c gc vi mt thc th. iu ny cho
php thay i bn m t thi im m phng hay tng hp h thng. Vic khai
bo cu hnh l tu chn, cng c th s dng cu hnh mc nh do VHDL cung
cp-khi kin trc c khai bo cui cng cho mt thc th s c gn vi
thc th .
4.2.4. Mi trng kim tra
Mt trong cc nhim v rt quan trng l kim tra bn m t thit k. Kim tra
mt m hnh VHDL c thc hin bng cch quan st hot ng ca n trong
khi m phng. Thng thng cc b m phng c cung cp kh nng kim tra,
nhng cng c th xy dng mt mi trng kim tra VHDL. Mi trng kim
tra c th hiu nh mt mch kim tra o. Mi trng kim tra sinh ra cc tc
ng ln bn thit k v cho php quan st hoc so snh kt qu hot ng ca
bn m t thit k.
Minh ha mt mi trng kim tra o bng VHDL.
175
Phn II: Thc hnh

Bi 1: Lm quen vi phng php thit k s bng VHDL trn phn mm ISE
ca Xilinx
1. Mc ch
- Lm quen vi phng php thit k s s dng ngn ng m t phn cng.
- Lm quen vi phn mm thit k ISE ca Xilinx.
- Thc hnh thit k s bng VHDL.
2. Thit b s dng
- My tnh PC ci t phn mm ISE ca Xilinx.
3. Ni dung thc hnh
- Thc hin cc phng php thit k s vi phn mm ISE ca Xilinx.
3.1. To d n mi
- Khi ng ISE WebPACK, la chn:
Start Programs Xilinx ISE 8 Project Navigator
- To d n mi:
-
Chn: File New Project.
bn.
Gi tn project ny l traffic v t n trong th mc thit k ca
Click Next.
in vo nh sau trong hp thoi New Project.

176
Device Family: CoolRunner-II

Device: xc2c256
Package: TQ144
Speed Grade:- -7
Synthesis Tool: XST (VHDL/Verilog)
Simulator:I ISE Simulator (VHDL/Verilog)
Click next.
Thm file ngun mi vo d n: Bm new source.
Thm VHDL module v gi l counter.
177
Click Next.
To b m 4 bit nh hnh di.
Khai bo cc cng.
- Kch next cho n finish, click finish: Mt thc th s t ng c to ra

trong mt module VHDL tn l counter.vhd v c thm vo d n.
178
M ngun s t ng m ra, nu n khng m bn c th kich p vo biu

tng trong ca s bn trn.
179
3.2. Bin son HDL

Kch p vo bt c ca file ngun no trong ca s ngun file s c hin
th trong ca s bin son chnh.
M ngun mu
Bin son module counter
Chn on m sau y vo gia begin v end sau architecture
process (clock, reset)
begin
if reset='1' then
count <= "0000";
elsif clock='1' and clock'event then
count <= count + 1;
end if;
end process;
Module s nh hnh di y
180
Mt module gm nhng khai bo th vin, entity, architecture. Nhng th vin

c khai bo ni vi trnh bin dch gi no c s dng. Entity khai bo
tt c nhng cng lin quan n thit k. Count (3 down to 0) ngha l vector
logic 4 bit.
Thit k ny c hai u vo clock v reset. Chc nng ca thit k c m t
sau dng architecture.
Lu module Counter
By gi bn c th m phng module m ca thit k. Khi module counter.vhd
c chn sng trong ca Source, ca s Process s hin th tt c nhng hnh
ng v ang din ra ca n. Mt file VHDL c th c tng hp sau to
ra bitstream. Thng thng mt thit k bao gm mt vi module mc thp ni
vi nhau bng mt file mc nh. Thit k ny hin ti ch c duy nht mt
module c th c m phng.
M phng chc nng
m phng file VHDL trc tin bn phi to file testbench
1. T menu project chn new source
2. Chn testbench waveform v t tn nh hnh di
3. Chn Next
4.
Testbench s m phng module counter do vy n s hi bn s
gn file ngun no cho file ngun ny, chon counter v click next
5.
Xem li thng tin tm tt v click Finish

181
6.
By gi cng c testbench HDL c trong thit k. Hp Initialize
timing thit lp tn s ca xung nhp h thng, nhng yu cu thit lp v
tr u ra. Board demo CPLD Design Kit c b dao ng 1.842MHz. Do
vy chng ta s nhp vo 540ns cho chu k hay l 270ns cho Clock High
Time v Clock Low Time nh hnh di.
7.
Click Finish
182
8.
Click chut vo dng reset thay i 0 1 nh hnh di y
9.
m phng trong ISE, Chn behavioral simulation trong menu
th xung ca ca s source.
10.
Kim tra counter vn c chn sng v tap process c la chn,
click p vo simulate behavioral model trong ca s process (phi click
vo du cng bn cnh Xilinx ISE Simulator m n ra).
183
11.
M phng t ng c to ra
12.
Hot ng ca mch ging nh nhng g chng ta mong i, n
tng tn hiu m ln mt sau mi sn ln ca clock, do vy chng ta c
th tip tc xy dng thit k ca chng ta. Trc tin chng ta s thc hin
snapshot chng ta c th quay li thi im ny ca tin trnh thit k khi
cn.
Chn Project Take Snapshot.
184
Thc hin snapshot s lu trng thi hin ti ca project vo mt th mc con do

vy sau ny chng ta c th quay li. Chng ta c th xem snapshot bng cch
la chn ca s Source. Nu nh thit k ch c mt module (phn cp mt
mc), th phase thc thi s l bc tip theo. Tuy nhin thit k ny c thm mt
module na.
3.3. Bin son lu trng thi
i vi thit k n giao thng ca chng ta b m hnh ng nh l mt b
nh thi gian chuyn trng thi. Lu s chuyn i qua 4 trng thi, mi mt
trng thi iu khin t hp 3 n.
1.
Trng thi 1: n
2.
Trng thi 2: n v Vng
3.
Trng thi 3: n Xanh
4.
Trng thi 4: n Vng
m trnh bin tp trng thi:

a.
Chn New Source
b.
Chn State Diagram v t tn stat_mac
c.
click next, sau l finish
185
d.
M state machine wizard bng cch click vo nut
Machine Wizard s xut hin
e.
State
Thit lp s trng thi l 4, bm next
186
f.
Bn s thy mt hp thoi la chn ch khi ng li. Kim
tra thy synchronous c chn, sau chn next.
g.
Tip theo bn s thy hp thoi Setup Transitions. G TIMER vo
trng tip theo.
h.
Click Finish v th lu trng thi ny vo bn v bng cch bm
vo bt c u trn trang bn v.
i.
Click vo trng thi khi ng (hnh ovan mu vng) v i tn
thnh RED.
187
j.
Bm vo nut Output Wizard
Thit k ny c 3 u ra t tn l RD, AMB, v GRN

k.
Trong trng DOUT, g vo RD khai bo mt u ra. Thit lp
cho RD gi tr l 1 vi u ra ng k, nh hnh di:
l.
Chn OK chn OK ti hp thoi Edit State
m.
Tng t nh th , bin son cc trng thi khc:
i tn States1 thnh REDAMB v s dng Output Wizard
thit lp RD=1, v mt u ra mi AMD = 1 vi mt u ra ng k.

Ta phi lp li Output Wizard hai ln nhn c hai gi tr u ra.
i tn States2 thnh GREEN v s dng Output Wizard thit
lp GRN l 1 vi u ra ng k.
i tn States3 thnh AMBER v s dng Output Wizard
thit lp u ra AMB l 1.
188
Lu trng thi s trng ging nh hnh di:
n.
Click vo ng chuyn trng thi gia trng thi RED v
REDAMB.
o.
Hp thoi Edit Condition s xut hin. Ti ca s ny, thit lp s
chuyn trng thi khi b timer bng 1111 bng cch thit TIMER=1111 ti
trng Condition.
p.
q.
Lp li cho cc ng truyn khc:
ng truyn REDAMB ti GREEN, TIMER = 0100.
ng truyn GREEN ti AMBER, TIMER = 0011.
ng truyn AMBER ti RED, TIMER = 0000.
Cui cng, khai bo vevtor TIMER bng cch chn nt:
189
r.
Th marker vo trang, click p v nhp tn l TIMER v rng
l 4 bit (trong phm vi t 3:0).
s.
Chn OK. Lu trng thi trng nh hnh di.
t.
Chn nt lnh Generate HDL
ti thanh cng c.
u.
Ca s Results xut hin dng Compliled Perfectly. ng hp
thoi li, ca s HDL Browser hin ra.
190
v.
Khi chn nt lnh Close, mt danh sch VHDL cho lu trng
thi c m trong hp thoi StateCAD HDL Browser.
w.
Lu danh sch v ng ca s.
Lu trng thi s c thm vo u ca s Source. (nhy p vo tn file s

m ra biu trng thi trong StateCAD)
191
3.4. Thit k VHDL mc nh

khu ny trong lung thit k hai module s c kt ni vi nhau bng mt
file mc nh. Mt s ngi thit k thch to s nguyn l cho mc nh,
trong khi s khc li thch gi thit k ny bng bng m lnh. V phn ny s
tho lun sau, do b m v lu trng thi s c ni bng file top.vhd.
to ra file VHDL mc nh:
o
Lu li nhng g bn lm bng cch thc hin snapshot project
Chn new source, v to module VHDL c tn l top
192
Bm next v in vo Wizard nh bn di.
Bm next, sau bm finish, s c file top.vhd nh di y
193
Trong ca s source, chn sng module counter.vhd. Trong ca s
Precesses bm chut phi vo View HDL Instantiation Template. T phn

Design Utilities chn Properties v thay i Target Language to VHDL. Click
Ok sau click p vo vo View HDL Instantiation Template.
o
Bi en v chp phn khai bo i tng v instantiation.
Dn phn khai bo v nguyn instantiation vo file top.vhd
Sp xp li phn khai bo sao cho n nm sau mnh begin trong
architecture. Sp xp li instantiation n nm gia mnh begin v end.

194
By gi chng ta cn nhp bng tay cc khai bo thnh phn v cc
instantiation cho lu trng thi nh sau. Bn di phn khai bo cc thnh

phn ca Counter nhp vo nh sau
COMPONENT stat_mac
PORT(
timer : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
reset : IN std_logic;
amb : OUT std_logic;
rd : OUT std_logic;
grn : OUT std_logic
);
END COMPONENT;
o
Tip theo l phn instantiation ca module lu trng thi. Nhp
vo di phn instantiation ca Counter on text sau y :

Inst_stat_mac: stat_mac PORT MAP(
195
timer => ,
clk => ,
reset => ,
amb => ,
grn => ,
rd =>
);
o
Khai bo mt tn hiu l timer bng cch thm vo bn trn ca
phn khai bo thnh phn bn trong architecture dng sau y:

signal timer : std_logic_vector(3 downto 0);
o
Vic kt ni counter v lu trng thi minh ho cc module,
do vy file top.vhd ca bn trng s nh bn di y
196
197
Kt ni cc tn hiu bng cch thm tn ca chng vo PORT MAP
nh sau:
198
Khi bn lu file top.vhd, lu thy cc ca s Source t ng
qun l phn cp ton b thit k, i vi hai file counter.vhd v

stat_mac.dia s l hai module con file top.vhd ngay sau c hin th l
biu tng mc nh.
o
By gi l lc thm vo VHDL to ra vo trong d n n c
th c thc thi v m phng. Click vo tap Libraries y ca ca s

source, m rng cy, click chut phi vo file STAT_MAC.vhd v chn
properties (Source - > properties). Thay i s lin kt ca hai file
STAT_MAC Behavior v SHELL_STAT_MAC BEHAVIOR t None
thnh Synthesis/Imp + Simulation nh di y.
Click OK chp nhn s thay i v khi tr li tap Source n
trng s th ny
199
Snapshot thit k nh trc (project - > take snapshot ) ln ny
t tn l snap3 v g vo VHDL top trong ca s gi

M phng thit k
Bn c th m phng thit k ban u ca bn
Thm file ngun testbench waveform nh trc , nhng ln ny gn n
vi module top. t tn file ny l Simulate_top.
Hp thoi ngun lin kt xut hin, m bo l Top c chn sng, v

click Next, sau click Finish hp thoi tip theo.
Trong hp thoi khi to thi gian thit lp thi gian xung clock trng thi
cao v trng thi thp l 270 ns nh trc v i di (length) l
100000 chu k. Click OK
200
Trong gin sng a vo mt kch thch u vo nh di y
Lu thi im kt thc l 100000 ns s to ra gin sng xt nhau hn. Hy

kch chut phi vo mt trong nhng khong thi gian (v d 2430 ns) v chn
Rescale Timing chnh t l nh bn trn. Thit lp timing l 10000 ns c t
l tng t bn trn. Bn phi rescale timing ln na c c t l nh hnh
di y.
Click biu tng save
201
File top_tb.tbw gi c gn vi module mc nh VHDL khi xem cc file

trong khung Behavioral Simulation.
Kch p vo Simulation Behavioral Model trong ca s Process
Nu nh m phng lm vic ng, bn s thy nh hnh trn.

3.5. Thit k s nguyn l mc nh
ECS hint.
To thit k s nguyn l mc nh.
I/O Marker.
M phng thit k s nguyn l mc nh.
i khi thit k trc quan s d hn khi c mc nh l s nguyn l vi

nhng thuyt minh l nhng khi HDL ring bit. Cc khi c th c ni vi
nhau theo cch c truyn. i vi nhng thit k trong cng c ISE, d n ban
u c th thit k da trn s .
Phn ny s tho lun v phng php kt ni cc module VHDL qua cng c
ECS. Nu bn lm vic ht cc phn trc , th trc ht bn phi b
(remove) file VHDL mc nh top.vhd ra khi d n. lm nh th, bn hy
file trong source khung Systhesis/Implementation, click chut phi v chn
remove sau click yes trong hp thoi. Sau b n ra khi ca s nhn bng
cch chn tap Top v Window - > close. Bn c th b nhng tab simulation
bng cch tng t nh th.
Hnh ng ny s a bn tr li trng thi trong lung thit k m ch c file
counter.vhd v stat_mac.vhd. Ca s source gi trng s nh di y
202
ECS hint
Chng trnh v s mch in ECS c thit k bn c th la chn
nhng hnh ng m bn mun cho php bi nhng i tng m bn mun
thc hin trn . Thng thng i vi nhng ng dng ca s hot ng kiu
la chn i tng sau tc ng trn cc i tng . Hiu c nguyn l
hot ng cn bn s lm cho vic hc ECS s n gin v th v hn.
To thit k s nguyn l mc nh
T trnh n Project, chn lu source -> Schematic v t tn l top_sch.
Click Next, Finish. Ca s ECS Schematic Editor s xut hin. S
c nhng tu chn trong ca s Processes
Trong ca s Source chn sng counter.vhd. Nu bn khng thy
counter.vhd hy kim tra Synthesis/Imlementation hin th v tap source

c chn
203
Trong ca s processes chn tap Processes v kich p vo Create
Schematic Symbol t phn con Design Utilities (bn phi kch vo du cng
thy n). N s to ra mt biu tng s nguyn l v thm vo trong
th vin trong trnh bin tp s nguyn l.
To mt biu tng khc cho lu trng thi bng cch chn
vo stat_mac.vhd v click p vo Create schematic symbol.
Tr li trnh v s nguyn l, nhng th vin biu tng c th
thy di tap Symbol bn phi tap trong ca s source (bn cn m rng

ca s thy r hn)
Thm b m v lu trng thi bng cch click vo new library
(C/Design/Traffic) trong ca s Categories sau l chn counter. Di

chuyn con tr vo bn v v th biu tng bng cch click vo v tr mun
t. Dich chuyn con tr tr li ca s Categories v t biu tng
Stat_mac vo bn v.
Phng ln ln
204
Chn cng c add wire trong thanh cng c v
thm dy ni gia hai chn click mt ci vo chn ny ri mt
ci vo chn kia. ECS s bn quyt nh s dng i dy t ng hay t

cc ng tn hiu bng tay trn trang bn v. thm cc dy cheo (dy
b cheo mt u), bn click mt ci vo biu tng chn ri click p vo
ch bn mun kt thc.
Ni dy cho lu trng thi v b m nh hnh di y:
205
Chn cng c Add net names t thanh cng c v
G clock vo name ca tap Options (ca s Processes) sau
click vo net trong bn v.
Thm cc tn net cho cc dy s c ni ti cc u vo/ra ca
FPGA/CPLD ca bn, t net name vo u b trng ca dy cheo. Kt

thc bng cch thm cc tn nt reset, amber_light, green_light, v
red_light. ECS tha nhn count(3:0) v TIMER(0:3) l cc bus v do vy
cc kt ni chng vi nhau bng bus th tt hn l mt nt n.
nh du cng vo ra
Chn cng c Add I/O marker t thanh cng c v
i vi kiu u vo c chn, click v r quanh u vo m
mun thm nh du u vo cho n. Lp li nh th vi cc u ra, la

chn kiu u ra.
Bn v hon chnh ca bn trng s ging hnh di. Chu rng khi thm cc
biu tng nh du u vo/ra cc ty chn s thay i. Bn la chn Add an
input Marker cho cc u vo v Add an output marker cho cc u ra
206
Lu thit k (file -> save). Kim tra ca s source, tap source (m
rng du cng nu cn), bn s thy phn mm ISE t ng cng nhn file

s nguyn l l file mc nh v do cng nhn thit k. Chn sau
click chut ph vo top_sch.sch v chn set as top module. Trong cy tin
trnh bn c th xem VHDL c to t s nguyn l khi top_sch c
chn trong ca s source. Kch p vo View VHDL Functional Model
cng c tng hp s lm vic t file ny
207
M phng thit k s nguyn l mc nh

Bn c th m phng thit k ban u ca bn
X.
Chn sng top_sch.sch trong ca s source
208
XI. Thm source testbench wave form mi bng cch click vo

top_sch.sch sau chn new source, chn testbench wave form v t tn l
top_sch_tb
XII. Click next v gn n vi top ri click finish

XIII. Khi to thi gian nh trc
209
XIV.Thm tc nhn kich thch bn ngoi nh di y
XV. File -> save

XVI.Chn top_sch_tb.tbw trong ca s source, click p vo Simulate
Behavioral Model trong ca s Process
210
Vic m phng s hin ra nh di y
By gi bn sn sng cho cng on thc thi thit k (implementation)

4. Cc bi thc hnh nng cao
- Module b ghp knh thit k bng VHDL(8 u vo TK mch s Tng Vn
On)
- Module iu khin ng c bc thit k bng VHDL(File hng dn ca
Xilinx)
- Module b gii m BCD(4bit) sang Led 7 on thit k bng VHDL.
- Module chia xung clock cho 16 thit k bng VHDL(TK mch s Tng Vn
On)
- Module gii m a ch 4 bit thit k bng VHDL(TK mch s Tng Vn On)
- Module ALU thit k bng VHDL(TK mch s Tng Vn On)
- Module mch dch bit t hp 6 bit thit k bng VHDL (TK mch s Tng
Vn On).
211
Bi 2: Tm hiu v cu trc phn cng X-Board
1. Mc ch
- Lm quen vi CPLD.
- Tm hiu v cu trc phn cng CoolRunner2 Starter Kit X_Board.
2. Thit b s dng
- Kit th nghim: CoolRunner2 Starter Kit X_Board.
- PC.
- Dy cp tn hiu.
3. Ni dung thc hnh
X- Board l mt mch in hon chnh lm nn pht trin cho Xilinx
CoolRunner II CPLD. N cung cp cc mch in h tr cn thit cho Cool
Runnner II, v th ngui s dng c th tp trung vo vic to ra v download cc
thit k mi. Mt cng USB 2 trn mch cung cp ngun cho bo mch v cung
cp cc cng d liu cho vic cu hnh CPLD cng nh l truyn d liu.
Hn 75 tn hiu CPLD c ni ti nhng kt ni m rng, v vy thit k d
dng c m rng. 32 tn hiu c ni ti cc b kt ni 6 chn, v th n c
th cung cp cho cc modul vo ra Pmod ca Diligent.PMod l bo mch nh
vi cc thit b c chi ph thp cung cp cc mch in nh b chuyn i A/D
v D/A, cc cng vo ra khc nhau v cung cp cc dng in ln cho ng
c.
Cc c trng ca X-board gm:
2.
C 256 macrocell CoolRunner-CPLD trong mt b TQ-144
3.
Mt cng USB2 trn mch dnh cho lp trnh JTAG v truyn d
liu ngi s dng.
4.
Mt b bin i A/D 16 bit trn mch cho php o c dng CPLD
trong sut qu trnh hot ng ca board ( d liu qua dy cm USBc
gi ti PC hin th)
5.
Mt b dao ng Silic c th thit lp tn s bi ngi dng
(1000/100/10KHz) thm vo to nn b dao ng thch anh th hai
6.
12 LED v 2 cng tc cho cng I/O trn mch.
M t chc nng
212
X- Board cung cp mt nn mnh, r, d s dng ngii dng c th tng kinh

nghim vi thit b CPLD tin tin nht v cc phng php thit k hin i.
Trung tm ca mch l CPLD CoolRunner II v n cng cha cc mch mch
in h tr cn thit thit k c th c thc hin v hot ng nhanh chng.
X- Board l mt nn l tng cho th nghim vi nhng thit k mi hoc nhng
kin thc v CPLDs v cng c CAD. Mt tp hp cc kt ni m rng cho php
thit k c pht trin rng hn gm cc mch ngi s dng thit k hoc cc
mch hn v cc modul thit b u cui (PMod) a ra bi Digilent.
Ci t phn mm
Khuyn ngh s dng ci t phn mm Digilent Adept trc khi kt ni bo
mch vi PC. iu ny cho php cc driver c ci t cho php Windows XP
nhn ra cc thit b. Ti thi im ny, Windows l h iu hnh duy nht h tr
phn mm Adept. C th s dng cc h iu hnh khc vi bo mch nhng
khng c kh nng s dng c tnh cng sut v dng in thc ca cng c XMeter.
Khi m bo mch, c th d dng kim tra cc chc nng c bn bng vic thc
hin cc cng vic sau:
Chn a Resource CD v ci t phn mm Adept.
Cm dy cm USB vi my tnh v X-Board. Hai n LED nh
mu vng bn cnh u kt ni USB trn X- Board s sng chng t rng

ngun ni vi bo mch.
Kt ni modul Switch vi cng J8.
Kt ni modul PS/2 vi cng J7. Kt ni bn phm PS/2 nu c.
Kt ni modul hin th LED 7 thanh ti cng J3/J4.
Nhn phm BTN0 khi ng cc thit k trn CPLD.
Lt SW4 trn modul chuyn mch thay i hin th t b m
ti m qut bn phm.
Theo gi ca Windows ci t cc driver.
Nhn nt Start quan st s tiu th cng sut ca thit b.
lp trnh vi CPLD, phn mm ISE WebPACK cng phi oc ci t.

1.
Chn a WebPACK CD v chy chng trnh ci t.
2.
Khi ng li my tnh
213
3.
m bo rng X-Board th oc kt ni vi my tnh.
4.
Khi ng chng trnh ExPort t Start -> Programs-> Digilent ->
Adept -> ExPort
5.
t SW1 trn X- Board thnh PROG
6.
Nhn nt Initialize Chain trong Export v thit b s t ng
c d tm. Nu khng, nhy n phn Trouble Shooting ca hng dn
ny.
7.
Nhn nt Browse v nh v file JED mong mun ( File Jedec c
trn a CD Resource).
8.
Kch phi chut vo biu tng CPLD v la chn Program
Device lp trnh CPLD vi file Jedec (Xo s xut hin mt cch t
ng v khng cn phi thc hin trc khi lp trnh).
Cu hnh
CPLD trn X-Board phi c cu hnh (hoc lp trnh) bi ngi
s dng trc khi n thc hin bt k chc nng no. File cu hnh c th
c to ra t s schematic hoc t cc cc file ngun HDL s dng
phn mm ISE WebPack min ph ca Xilinx. Cc file cu hnh c th
c truyn ti cc X-Board s dng dy cp USB v phn mm Adept
Export ca Digilent, hoc s dng cp lp trnh ( khng oc cung cp bi
Xilinx) v phn mm iMPACK ca Xilinx. Khi c cu hnh, CPLD
s t c trng thi ca n mt cch v hn.
Khi bo mch X- Board oc bt, cu hnh CPLD c load gn
y nht s xut hin tc th. Mt cu hnh mi c th uc load bt c

thi im no, v min l khi cu hnh mi c load, n s nh ngha
cch hot ng ca CPLD.
cu hnh CPLD s dng phn mm Adept Export ca Digilent,
gn dy cp USB ti my tnh v ti X-Board. Khi ng Adept Export,

v cho php n d t ng thit b USB trn X-Board bng vic kch vo
Initialize Chain. Khi CPLD c d, s nhn thy hnh nh ca CPLD
v hp thoi xung c th la chn file cu hnh. La chn cc
file cu hnh .jed v sau kch phi chut trn biu tng ca CPLD v
chn Program.
X- Meter
214
X-Board bao gm mt b o dng nm trm bo mch, c th o
dng ca li CPLD mt cch lin tc. X-Meter c xy dng da vo b

bin i sigma delta 16 bit LTC2480 cng ngh tuyn tnh. LTC 2480
s dng mt cng SPI gi d liu mu ti my tnh v cng SPI s chia
s cng chn nh l cng lp trnh JTAG. SW1 la chn gia X-Meter v
cng lp trnh JTAG.X-Meter l mt ng dng o c dng in da trn
PC, pht trin cho X-Board. X-Board vi nn tng c s l CPLD
CoolRunner II, cha b bin i A/D LTC 2480 cng ngh tuyn tnh,
dng o dng v nhit . X-Meter thu nhn d liu t LTC2480 s dng
cng USB2 trn X-Board v hin th d liu trn my tnh.
s dng X- Meter, ni X-Board ti my tnh, t SW1 ch
Meter v m bo rng JP1 c t ti REG. Khi ng ng dng XMeter t menu Window Start, kch chut vo nt Start trn X- Meter.
X-Meter s t c mt nhit v chn dng mu trong khong
chu k 2s v truyn d liu n b m d liu trn PC qua cp USB. XMeter v biu d liu bng mt th dng sng ch ra d liu ln nht
v nh nht t c. thay i t l ca dng sng, kch vo s o
dng in mong mun / nt phn chia.
D liu v nhit th ch c hin th khi kch hot check box
khi Temperature Measurement c check. Nt Calibrate c s

dng nh c sensor nhit ti mt gi tr ng n. N ch cn thc
hin mt ln.
Nt Stop dng dng vic nhn d liu mi v nt Clear dng
dng thu nhn d liu, lm sch b m v xo dng sng hin th. \
Save gi tr d liu trong b m ti CSV file (Comma
Seperated Value), kch chn nt Save Buffer As ... v nh r tn file

(ch gi tr nhit s ch c save nu check box di Temperature
Measurement c check.
Ngun cung cp
X- Board c th c cp ngun ton b t cng USB, hoc t
ngun cung cp bn ngoi gn vo u ni JP3. Jc JP2 s la chn khi

no bo mch s dng ngun USB hoc ngun ngoi.
Nu ngun USB c s dng, jm J2 s c thit t ln REG
v dy cp USB USB s kt ni gia my tnh v u cm USB nh trn

215
mch X-Board. Nu X-Board nhn ngun t my tnh, hai n LED mu

vng bn cnh ca u cm USB trn mch s sng r.
Ngun cung cp bn ngoi c cp qua b iu chnh tuyn tnh.
in p t vo chn ngun th c cp qua b iu chnh in p c tc

dng cung cp ngun cho mch. s dng ngun pin bn ngoi, Jm J2
phi c thit lp BAT v ngun t vo chn J3 ( xem s mch in).
B iu chnh s iu chnh in p t 3.6 9V. Nu s dng pin AA,
cn p dng 3 pin mc ni tip nhau.
X-Board s dng mt mch in 4 lp, cc lp bn trong dnh cho
Vcc v GND. CPLD v cc IC khc trn board mch cn c b sung ca

cc t r ngang t gn vi mi chn Vcc. B iu chnh tuyn tnh, cng
vi vic cp ngun cp tt v nhiu cc t r s to ra mt mt ngun
cung cp sch v nhiu thp.
B dao ng
X-Board bao gm b dao ng Silic c kh nng thit lp bi
ngi s dng. N c th to ra cc tn hiu xung nhp tn s 1MHz,

100KHz hoc 10KHz da trn v tr ca xung nhp la chn Jm J11 ( J11
c ghi nhn bn di ca bo mch). u ra dao ng chnh, c ghi
l PCLK trong schematic, th c ni ti chn GCLK2 ca CPLD (
P38) m c th c ni ti b phn chia tn s bn trong. Pads cho
mt b dao ng SMT tiu chun cng c cung cp ti xung nhp IC4
A 48MHz th cng c hin th trn P30.
D liu vo ra ngi dng
Nt nhn to ra mt con s 1 ti CPLD. Nt nhn chuyn mch
u vo s dng mt in tr ni tip bo v khi b ngn mch (ngn

mch s xy ra nu mt chn CPLD c phn cng ti mt nt nhn
trc c nh ngha mt cch v nh l mt u ra)
Cc n LED
216
12 n LED mu c cung cp cho mch ch dn, v c kh
nng cu hnh s dng. Hai n LED mu vng ch ra trng thi kt ni

ngun USB (LD13) v ngun 3.3V (LD14). Hai n l c nh v
khng th thay i c.
B kt ni tp trung 6 chn
X- Board cung cp 8 modul kt ni u cui 6 chn. Mi b kt ni
cung cp VDD, GND v bn tn hiu c trng CPLD.
Mt vi mch modul 6 chn c th gn vo cc b kt ni c
cung cp bi Digilent bao gm mch speaker, mch cu H, mch

sensor, ...
Xem s thit k mch cho thit k cc chn.
Modul ngoi vi
B mch ny bao gm 3 modul ngoi vi: PS/2, Switches, v hai b
hin th LED 7 thanh.
Thit k Demo.
Thit k trc khi lp trnh trn CPLD cha mt s chc nng c
th quan st khi cc modul ngoi vi c cung cp c t vo cc cng

thch hp.
Modul Switches - > cng J8
217
Modul PS/2 - > cng J7

Modul LED 7 thanh - > cng J5/J6.
D nhin l cc thit k c th thay i s dng cc cng khc
nhau, nhng y l cc cng dng cho thit k mu.
CPLD thc hin c b m cng nh l b gii m bn phm PS/2.
Hin th thay i gia hai phn ny da trn gi tr ca SW4. SW1, 2 v 3

khng c s dng trong thit k. BTN0 l khi to hn thng cho thit
k. Tn s xung nhp l tng cho thit k l 100Hz, s dng gim b
nhy cho J11.
Khi SW4 c la chn b gii m PS/2, u ra trn hin th l m
qut cho cc k t. Di y l mt s m qut, nhng m cn li c th

tm trn Internet.
Khuyn ngh thit k

1.
B iu chnh cung cp ngun 3,3V, v th t chun mc nh vo
ra mt cch thch hp.
2.
Cc chn vo ra khng s dng c th t xung GND gim
thiu cng sut.
3.
u vo nn t Keeper gim thiu cng sut tiu th chn bt
k cc chn u vo c in th thay i.
4. Yu cu sau bui thc hnh
- Da vo Kit th nghim: CoolRunner2 Starter Kit X_Board.
- Da vo ti liu hng dn s dng trn PC.
- Yu cu vit bo co v cu trc phn cng ca X_Board.
- Bo co c np cho GVHD sau bui thc hnh.
218
Bi 3: Thc hnh vi Project mu trn X-Board

1. Mc ch
- Lm quen vi phng php thit k s bng VHDL.
- Phn tch mt thit k mu.
- Nm c cc quy trnh thit k s trn CPLD.
2. Thit b thc hnh
- Kit th nghim: CoolRunner2 Starter Kit X_Board.
- PC.
- Dy cp tn hiu.
3. Ni dung thc hnh
Tng quan
Demo thit k tham kho ca module Digilent X-Board trn PModAMP1 s
dng Module ngoi vi PModeAMP1 vi X-Board to ra m Audio trn loa
hoc trn Headphone. Thit k tham kho ny s dng cc xung vung to cc
m Audio nhng cc dng sng phc tp hn cng c th d dng c tng
hp.
219
X-Board l mt board thc hnh cho CPLD da vo CPLD CoolRunner-2 ca

Xilinx. PModAMP l mt Module ngoi vi ca Digilent cha mt b khuch i
Audio LM4838 2W ca National Semiconductor. PModAMP1 c hai Jack
Audio, Jack ny c th cm vo Speaker hoc HeadPhone.
Phn mm Adept ca Digilent c dng lp trnh cc thit k tham kho vo
CPLD v truyn d liu vo CPLD la chn tn s Audio.
Cc ti liu tham kho thm
Digilent X-Board Reference Manual Schematic
Digilent PModAMP1 Reference Manual and Schematic
Digilent Adept Reference Manual
Digilent Application Note AN0040 Digilent Asynchronous Parallel
Interface.
National Semiconductor LM4838 Datasheet
Xilink CoolRunnerII Datasheet
Cc thit b ci t
Thit k tham kho ny cn mt PC ci phn mm ISE ca Xilinx. Phn mm
Digilent Adept, mt X-Board, mt module ngoi vi PModAMP1, Speaker hoc
220
HeadPhone. Thit lp tn s xung nhp la chn Jump J11 trn X-Board v t

100Khz.
M t
Thit k tham kho ny c chia lm hai khi chnh.
Mt giao din USB (EPP Controller) to ra cc thanh ghi trn CPLD m phn
mm Adept c th c v ghi thanh ghi , v mt b to xung vung c th lp
trnh c to ra tn s Audio. Mt Bus iu khin 8 bit n gin (y l bus
giao din song song khng ng b ca Digilent) c s dng chuyn d
liu bn trong gia hai khi.
Cc khi giao din USB lm vic vi Firmware trong b iu khin USB thc
hin cc thanh ghi trong CPLD m cc thanh ghi ny c th truy cp t phn
mm Adept c ci t trn my tnh. Cc thanh ghi CPLD c th c v ghi
trn ng dng Transport ca Adept.
Trong thit k ny c hai thanh ghi 8 bit c s dng, mt thanh ghi a ch v
mt thanh ghi d liu. Bi v ch cn c hai gi tr d liu, thit k ny minh ho
rng c thanh ghi d liu v thanh ghi a ch u c s dng lu tr d liu
(thay v cch tip cn in hnh ca vic thit k hai thanh ghi d liu hai a
ch khc nhau nh trong hu ht cc thit k khc). Mt gi tr m oc ghi vo
mt thanh ghi a ch no s nh ngha mt khong thi gian ca tn hiu
audio thnh m.20us. V mt gi tr n ghi vo mt thanh ghi d liu no s
nh ngha khong thi gian tn ti ca tn hiu bng n.10ms. V d, to ra
tn s 1KHz trong 1s, ghi con s 50 vo thanh ghi a ch v con s 100 vo
thanh ghi d liu.
221
Cc bc thc hnh
1. Gn PModAMP1 vo J1 trn X-Board, gn speaker hoc Headphone vo
PModAMP1.
2. Np file X-Board_PModAMP1.jed bng phn mm Digilent Export ca
Adept.
3. Chy ng dng Digilent Transport
La chon Tab Register I/O
nh con s tng ng vi tn s vo bt k mt box thanh ghi a ch no
v con s nh ngha khong thi gian ca tin hiu audio trong mt box thanh ghi
d liu no .
Kch chut vo nt Write bn cnh d liu. Khi tn hiu audio s c
pht ra.
222
4. Yu cu sau bui thc hnh

Sinh vin vit 1 bo co v module thc hnh. Ni dung bo co:
Mc ch ca bi thc hnh
Phn tch on m trong bi thc hnh mu
Cc bc chnh thc hin mt thit k trn CPLD.
Tr li cc cu hi ca GVHD.
223

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Giao Trinh Thuc Hanh Vi Dieu Khien Va Vi Xu Ly

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KHOA CNG NGH THNG TIN

THC HNH VI IU KHIN & VI X LY

Ngi bin soan: ThS.VU THANH VINH

THAI NGUYN, NM 2010

BI 5: KHO ST MODULE HIN TH 16x32 IM MT MU......................38

Lm quen vi cc linh kin chc nng

Cc im kim tra (test point)

Phn cp t c bn n nng cao

Phn chia thnh nhiu module

Kho st phng php qut hng, qut ct

Cc thnh phn h thng

II. Module LMD01

Ma trn LED 8x8 pixel, n sc ()

Khi m Kathode ULN2803

Khi m Anode 74LS574

Khi m d liu hng 74LS164

Khi cht d liu hng 74LS573

Khi qut hng 74LS164

Module c cht cm ngun 5V, jack ni tn hiu iu khin kt ni vi

Hnh 1. S nguyn l LMD01

III. Module LMD02

Ma trn LED 8x8 pixel, n sc ()

Khi m Kathode ULN2803

Khi m Anode 74LS574

Khi m d liu ct 74LS164

Khi cht d liu ct 74LS573

Khi qut ct 74LS164

Module c cht cm ngun 5V , jack ni tn hiu iu khin kt ni vi

Hnh 2. S nguyn l LMD02

Ma trn LED 8x8 pixel, 2 mu xanh/

Khi m cht d liu mu xanh 74LS595

Khi m cht d liu mu 74LS595

Khi m Anode 74LS574

Khi qut hng 74LS164

Module c cht cm ngun 5V, jack ni tn hiu iu khin kt ni vi

Hnh 3. S nguyn l LMD03

Ma trn LED 8x8 pixel, 2 mu xanh/

Khi m mu xanh ULN2803

Khi qut ct 74LS164

Khi m cht d liu ct 74LS595

Module c cht cm ngun 5V, jack ni tn hiu iu khin kt ni vi

Hnh 4. S nguyn l LMD04

Ma trn LED 16x32 pixel, 1 mu

Khi m d liu hng 4 IC 74LS574

Khi cht d liu hng 4 IC 74LS574

Khi m Anode 4 IC ULN2803

Jack tn hiu vo, jack tn hiu ra

Module c cht cm ngun 5V, jack ni tn hiu iu khin kt ni vi

Hnh 5. S nguyn l LMD05

LMD06 l mt module hin th 16x32 pixel hai mu xanh v , trn c cc

Ma trn LED 16x32 pixel, 2 mu xanh/

Khi m cht d liu hng 16 IC 74LS574

Khi m Anode 4 IC ULN2803

Jack tn hiu vo, jack tn hiu ra

Module c cht cm ngun 5V, jack ni tn hiu iu khin kt ni vi

Hnh 6. S nguyn l LMD06

Hnh 7. LMD07 Bng tin in t 16x96 pixel n sc (xanh/)

MCU AT89S52, 8k flash ROM

Giao din truyn thng RS232

S dng ngun 220VAC

LMD09 l h vi iu khin cha cc cc thnh phn phc v cho cc bi thc

MCU PIC AT89S52

Giao din RS232

Giao din ISP