GII THIU V VI X L dsPIC30F3012

1.1. Tng quan v dsPIC

c sn xut bi Hng cng ngh Microchip Technology Inc. nh sn xut ng u v doanh thu trn th gii v cc sn phm vi x l 8 bit, tuy nhin dng sn phm dsPIC cng ngy cng chim lnh v tr cao trong th phn vi x l 16 bit. Vi x l dsPIC ngoi chc nng ca mt vi iu khin thng thng vi b x l mang sc mnh 16 bit (c kh nng x l d liu c di 16 bit). Vi tc tnh ton cao da trn kin trc RISC, kt hp cc chc nng iu khin tin ch ca mt b vi iu khin hiu nng cao 16-bit (high-performance 16-bit microcontroller), c th thc hin chc nng ca mt b x l tn hiu s (DSP) nn dsPIC cn c th c xem l mt b iu khin tn hiu s (Digital Signal Controller DSC). C th thy nh sn xut a ra mt cp gii php gn b: n chip n ch dn cho thit k h thng nhng. Cc thit b dsPIC c th t ti tc x l 40 MIPS (Mega Instruction Per Second - triu lnh trn mt giy), thch hp vi ngn ng lp trnh C, tch hp b nh Flash, b nh d liu EEPROM, cc ngoi vi hiu nng cao v rt a dng cc th vin phn mm cho php thc hin cc gii thut nhng vi hiu sut cao mt cch d dng trong mt khong thi gian ngn. Vi cc kin trc vi iu khin quen thuc, cc b iu khin tn hiu s dsPIC (dsPIC DSCs) c th c s dng rng ri trong cc ng dng nh: iu khin motor v bin i ngun, cc sensor tc cao, ting ni v m thanh, internet v cc modem kt ni, vin thng, m ho v t ng ho v.v.. Cu trc vi x l dsPIC30F3012 dsPIC30F3012 l mt loi vi x l 16-bit nh gn, 18 chn, nhng do mang chc nng x l tn hiu s nn n c tch hp b nh chng trnh ln (Flash, SRAM, EEPROM), cc ngoi vi mnh (ADC 12-bit 8 knh, Timer 32-bit ), tc x l cao (c th ln ti 40 MIPS).

Hnh 3.1: Cu trc ca dsPIC30F3012

1.2 c im chnh ca dsPIC30F3012

1.2.1. c im ca mt CPU kin trc RISC Tp lnh c bn gm 84 lnh Ch nh a ch linh hot di lnh 24-bit, di d liu 16-bit B nh chng trnh Flash 24 Kbytes B nh RAM ln 1Kbytes B nh EEPRO Mng 16 thanh ghi lm vic 16-bit Tc lm vic ln ti 40 MIPS 1.2.2 c im ca b x l tn hiu s Np d liu song song Hai thanh ghi cha 40-bit c h tr bo ho logic Thc hin php nhn hai s 17 bit trong mt chu k my Tt c cc lnh DSP u thc hin trong mt chu k my Dch tri dch phi 16 bit trong mt chu k my 1.2.3. Cc ngoi vi c trng Dng ra, vo cc chn I/O ln: 25mA Timer 16 bit, c th ghp 2 Timer 16 bit thnh mt Timer 32 bit.

Chc nng Capture 16 bit Cc b so snh PWM 16 bit Module SPI 3 dy (h tr ch Frame) Module I2C, h tr ch a ch t, a ch t 7 bit n 10 bit UART c kh nng a ch ha, h tr b m FIFO. 1.2.4. Cc c trng Analog B chuyn i tng t s (ADC) 12bit Tc ly mu ti a 100 Ksps( kilo samples per second) Ti a 10 knh ADC li vo Thc hin bin i c trong ch Sleep v Idle Ch nhn bit in th thp kh trnh To Reset bng nhn in p kh trnh Cc c trng ca mt vi iu khin B nh Flash: ghi/ xa ln ti 10000 ln (iu kin cng nghip) v 100 000 ln (thng thng). Kh nng t np chng trnh di s iu khin ca sofware Watch Dog Timer mm do vi b to dao ng RC ngun thp trn chip. Ch bo v fimware kh lp trnh Kh nng t lp trnh ni tip trn mch in C th la chn cc ch qun l ngun : Sleep hoc Idle

1.3. Cng c DSP

Cng c DSP bao gm mt b nhn tc cao hai s 17-bit, mt b dch, v mt b tng/hiu 40-bit (vi hai thanh cha) Cng c DSP cng c kh nng thc hin di chuyn ni dung t thanh cha ti thanh cha m khng cn d liu thm vo. Cc lnh ny l ADD, SUB v NEG.

Vi x l dsPIC30F c thit k theo kin trc lnh thc hin trong mt chu k do khng th hot ng ng thi cng c DSP vi cc lnh ca MCU. Tuy nhin ti nguyn ca mt vi khi s hc v logic ca MCU c th c s dng ng thi bi nhng lnh tng t nhau (v d lnh ED v EDAC). Cng c DSP c nhng la chn c xc nh bng vic thay i cc bit ca thanh ghi CORCON (CPU Core Configuration register) c lit k di y: Thc hin php nhn DSP phn s hoc s nguyn (bit IF). Thc hin php nhn DSP s c du hoc khng du (bit US) T ng bt tt ch bo ho thanh ghi AccA (bit SATA) T ng bt tt ch bo ho thanh ghi AccB (bit SATB) T ng bt tt ch bo ho cho vic ghi vo b nh d liu (bit SATDW) La chn ch bo ho cho thanh cha (ACCSAT) T chc b nh ca dsPIC30F3012 Khng gian a ch chng trnh c ln 4M t lnh. Bn khng gian b nh chng ca dsPIC30F3012 c ch ra trong hnh 3.4. B nh chng trnh c th c a ch ho bi mt gi tr 24-bit bi b m chng trnh (PC), hoc bng lnh a ch hiu dng (EA), hoc khng gian d liu EA khi khng gian chng trnh c sp xp v a ch ho. Ch rng, a ch khng gian chng trnh c tng ln vi bc l 2 gia cc t chng trnh to ra s tng thch vi vic a ch ho khng gian d liu. Truy cp khng gian chng trnh ngi s dng b gii hn trong di 4M a ch ca t lnh (t 0x000000 ti 0x7FFFFE) vi tt c cc lnh truy cp, tr hai lnh TBLRD/TBLWT - s dng bit 7 ca thanh ghi TBLPAG xc nh ngi s dng hoc thit lp cu hnh truy cp b nh. Kin trc ca dsPIC cho php np d liu rng 24-bit ti b nh chng trnh, do cc lnh lun lun c xp hng tuy nhin kin trc ca n c ci tin so vi kin trc my tnh Hadvard nn d liu cng c th c a ra trong khng gian chng trnh.

1.4. Cc b nh thi Timer

Trong vi x l dsPIC30F3012 c ti ba b nh thi (Timer) 16-bit. Trong cc Timer c th hot ng ring bit, ring hai Timer 2 v 3 c th kt hp vi nhau tr thnh mt Timer 32 bit. V cu trc cc Timer ny khc nhau v hai Timer 2 v 3 c th kt hp cn Timer 1 th khng. Timer 1 c cu trc kiu A Timer 2 kiu B v Timer 3 kiu C. V hot ng cc Timer c hot ng gn ging nhau do ch trnh by v Timer 1. Timer 1 c th hot ng vi ngun to dao ng tn s thp 32KHz, v ch khng ng b vi ngun to dao ng ngoi. c im ring bit ca Timer 1 l c th dng trong cc ng dng thi gian thc. Phn tip theo s m t chi tit cch thit lp v s dng Timer 1 vi ba ch : Timer16-bit Trong ch ny, timer s tng sau mi chu k lnh n khigi tr ca timer bng gi tr ca thanh ghi chu k PR1 (Period Register) th s reset v 0 v tip tc m. Counter ng b 16-bit. Trong ch ny, timer s tng mi sn ln ca ca xung nhp ngoi m c ng b vi pha ca cc xung nhp trong. Timer tng n gi tr nm trong thanh ghi PR1 th dng v reset timer v 0 ri tip tc m ln. Counter khng ng b 16-bit. Khi hot ng trong ch ny, timer s tng dn sau mi sn ln ca xung nhp bn ngoi tc ng vo. Timer s tng dn n khi gi tr ca n bng thanh ghi PR1 th b reset v 0 ri li tip tc m ln. H s chia tn ca b nh thi Xung nhp u vo (Fosc/4 hoc xung nhp ngoi) a vo Timer 16-bit v c th c chia tn s theo cc t l sau: 1:1, 1:8, 1:64, 1:256 c xc nh bi cc bit TCKPS<1:0> ca thanh ghi T1CON. H s chia tn ny (prescaler) c th b xo khi xy ra mt trong cc iu kin sau: Ghi vo TMR Ghi vo thanh ghi T1CON (tr vic ghi vo bit T1ON) Reset thit b, nh POR v BOR

1.5. B chuyn i tng t s ADC

B chuyn i tng t s 12-bit cho php bin i tn hiu tng t u vo sang s di 12-bit. Module ny da trn thanh ghi SAR (Successive Approximation Register thanh ghi xp x) v cung cp tc ly mu ti a ln ti 100 ksps. ADC ca dsPIC30F3012 c ti 10 knh tng t li vo c kt hp c ly mu v gi mu. Li ra ca b ly v gi mu l li vo ca b chuyn i - to ra kt qu bin i. in th tng t chun c th l in th ngun cung cp (AVDD/AVSS) hoc mc in th ca cc chn VREF+/VREF-. B bin i ADC ca dsPIC bao gm 6 thanh ghi: Ba thanh ghi iu khin A/D: ADCON1, ADCON2, ADCON3 Chc nng iu khin hot ng ca ADC. Thanh ghi la chn li vo: ADCHS La chn knh vo bin i. Thanh ghi cu hnh cng ADPCFG Cu hnh cng tr thnh li vo tng t hoc vo ra s. Thanh ghi la chn qut

Hnh 3.2. S khi c bn ca ADC 12-bit

1.6. Cc bc thc hin bin i A/D

Thit lp cu hnh cho module A/D Cu hnh cc chn l li vo tng t, in th chun v vo ra s. Chn cc knh li vo cn bin i. Chn xung nhp cho bin i. Cho php module ADC c th hot ng. Cu hnh cho ngt ADC nu cn. Xa c ngt ADIF. La chn mc u tin ngt cho bin i A/D. Bt u ly mu. i thi gian cn thit hon thnh Kt thc ly mu, bt u bin i. i bin i kt thc bi mt trong hai iu kin sau: i ngt t ADC. i bit DONE c set.. c kt qu t b m bin i A/D v xa bit ADIF nu cn.