Each pin in ports P1 and P2 have interrupt capability.

Each PxIFGx bit is the interrupt flag for its corresponding I/O pin and is set when the selected input signal edge occurs at the pin. Each PxIFG port interrupt flag must be reset with software. Example: Port pin P1.5 is configured as I/O function, input direction and the port interrupt is enabled along with the appropriate port interrupt edge select (low-to-high or high-to-low transition). The device is placed in LPM while waiting for the Port1 interrupt. The appropriate signal edge on P1.5 pin triggers the port interrupt and the Port1 interrupt service routine is used to handle this event in user firmware. Grace Configuration: In the GPIO module select Pinout View of applicable device package From the drop down box of P1.5, select GPIO Input option In the "P1 / P2" register view, check box for Bit 5 of the "Interrupt Enable Register" for PORT 1 and specify an appropriate name for the Interrupt Handler (for e.g. Port1ISRHandler) User Code:

// Enter LPM with global interrupt enabled __bis_SR_register(LPM0_bits + GIE); // On P1.5 rising edge capture event, device wakes up to service Port ISR // >>>>>>>> Fill-in user code here <<<<<<<< // Port1 Interrupt Handler void Port1ISRHandler(void) { // Rising edge captured on P1.5 input pin P1IFG &= ~BIT5; // Clear P1.5 IFG // >>>>>>>> Fill-in user code here <<<<<<<< }