I2C Project

Introduction and Guide

Assignments
1. Create Verilog Model of I2C circuit Turn in verilog files and screens of simulation 2. Create Schematic of I2C circuit (add verilog models for simulation) Turn in pdfs of schematics Screens of block simulations 3. Create Layout of I2C circuit Turn in pdfs of Layout All are due last day of finals.
However I would suggest this schedule. Verilog Done Sept. 30 Schematic Done After Thanksgiving Break Layout Done right before finals. (That way you can study for your finals)

I2C Protocol
Inter IC bus or I2C bus or I2C bus 2 Wire Bi-directional Bus Utilizes Master and Slave Circuits Developed By Philips Now Owned By NXP

Communication

Data changes inbetween high edges of clock

Control Sequence

Start (S) Data goes low when clock is high Stop (P) Data goes high when clock is high Otherwise data must change when clock is low.

Acknowledge (Extra Credit)

After Every 8 bits the Circut Should Acknowledge the exchange Used to determine if device is on bus.

I2C Pattern

Data is organized with a device address first. The 8th bit of the address data is the R/W(bar) bit. A 1 is a read while a 0 is a write

I2C Write Exchange

Start Bit Device Addres R/W bit (0) Ack Reg Address Ack Data Ack Data (Auto Increment) Ack Data (Auto Increment) Ack ... Stop Bit

I2C Read Exchange

Start Device Address Write Bit Ack Register Address Ack Start Device Address Read Bit Ack Receive Data Ack Receive Data ... NAck Stop

I2C Slave Blocks (Simplified)

Watch Clocks and Clock Bars

Start And Stop Bits

Start
Data is the clock to the flip flop Clock is the data to the flip flop Asynchronous reset with clock

Start
Data is the clock to the flip flop Clock is the data to the flip flop Asynchronous reset with clock

always @(negedge sda or negedge scl) if (~scl) startbit <= 1'b0; else startbit <= scl;

Shift Register
always @(posedge scl) //can do a parallel load with an "if" statement shiftData <= {shiftData[6:0], sda};

The State Machine

Start bit always returns to dev address Stop bit always returns to idle Dev Address shifts in the device address and checks against local device address WR Address shifts in the register address for the data mux

The State Machine (cont)

WR Data shifts in the data and sends it to the data registers RD Data shifts out (on negedge scl) the data from the data registers

Data Register
Use a case statement to read and write the data register case (dataReg) 3'b0000: //data0 3'b0001: //data1 endcase

Ack Logic
We will not send acks or check acks. However if you implement it you will receive extra credit