THI GIA K

Thit k VLSI
THI GIAN LM BI: 90 pht
------------------------------------------------------------------------------------------------------1. V s mch mc transistor cho mch CMOS 1 tng cho hm sau:
(s
dng s transistor b nht) V layout mch . Tnh kch thc.
2. Cng ngh 180nm c in dung chuyn mch trung bnh (average switching capacitance) l 150
pF/mm2. Tnh cng sut tiu th ca chip nu din tch chip l 70 mm2, chy tn s 450 MHz, Vdd =
0.9V v h s hot ng (activity factor) l 0,1.
3. Tnh logical effort ca mch 2 u vo XOR
4. Cho 4 thit k mch 6 u vo AND gate nh hnh v. Tm tr ca mch b, c nu path electrical
effort l H. Tnh chi tit vi H=1, H=5, H=20.

(Sinh vin c s dng ti liu)

THI GIA K
Thit k VLSI
THI GIAN LM BI: 90 pht
------------------------------------------------------------------------------------------------------1. V s mch mc transistor cho mch CMOS 1 tng cho hm sau:
. V
layout mch. Tnh kch thc.
2. Cng ngh 130nm c in dung chuyn mch trung bnh (average switching capacitance) l 180
pF/mm2. Tnh cng sut tiu th ca chip nu din tch chip l 100 mm2, chy tn s 450 MHz, Vdd
= 0.9V v h s hot ng (activity factor) l 0,1.
3. Tnh logical effort ca mch 2 u vo NAND
4. Cho 4 thit k mch 6 u vo AND gate nh hnh v. Tm tr ca mch a, d nu path electrical
effort l H. Tnh chi tit vi H=1, H=5, H=20.

(Sinh vin c s dng ti liu)