LI NI U

Trong thi i cng ngh thng tin pht trin chng mt, vi nhng ng dng thc t em li hiu qu v li ch cho con ngi ngi cng ngh thng tin v ang dn thay th sc lao ng ng thi nng cao hiu qu hot ng trong cc lnh vc ca cuc sng. Nhc n Cng ngh FPGA c l khng cn xa l g i vi chng ta, bi l cc ng dng ca n trn ngp khp mi ngc ngch trong cuc sng, k c nhng lnh vc con ngi kh hoc khng th tip xc nh lnh vc nghin cu, ch to chp. Nghin cu v ch to chp l vic lm ht sc cn thit trong giai on cng nghip ha hin nay. ch to ra nhng loi chp c tc dng ng nh mong mun, i hi ca con ngi v ca s pht trin, c nhiu ng dng trong i sng, nghin cu cng nh khoa hc. V thnh phn quan trng nht ca chp chnh l CPU. CPU vit tt ca ch Central Processing Unit : n v x l trung tm. CPU c th c xem nh no b, mt trong nhng phn t ct li nht ca chp. Nhim v chnh ca CPU l x l cc chng trnh vi tnh v d kin. V vy trong ti 5 chng em Nghin cu v ch to CPU 8 bit bng lp trnh FPGA Chng em xin chn thnh cm n thy H Khnh Lm v thy Phm Ngc Hng cng cc thy gio trong b mn KTMT to iu kin gip chng em hon thnh ti mt cch thun li. Hng Yn, thng 12 nm 2011 Nhm sinh vin thc hin : 1: Bi Anh Tun 2: L Th Kim Oanh 3: Dng Hu Thi 4: Nguyn Vn Phong

CHNG I: GII THIU V FPGA

1.1. Cu trc chung ca FPGA Trong khi tn ti s pht trin cng ngh t PAL ln GAL v CPLD, c mt xu hng pht trin khc da trn cng ngh mng cng, l mng cng c th lp trnh c dng trng, FPGA (Field-Programmable Gate Array). T 1980, cc cng ty sn xut PLD hng u y mnh qu trnh nghin cu v FPGA v nhanh chng cho ra cc th h FPGA vi s lng cng v tc ngy cng cao.cc FPGA hin nay c s lng cng ln c th thay th c mt h thng bao gm li CPU, B iu khin b nh (Memory Controller), cc ngoi vi nh SPI,Timer, I2C, GPIO, PWM, Video/Audio Controller (ngha l tng ng vi cc SoC hin i).
Configura ble Logic

I/O Block Programma ble I/O BLOCK RAMS BLOCK RAMS Hnh 1.1: S khi ca FPGA

Hnh 1.2: V tr cc chn tn hiu (pin) ca CLB

FPGA gm c (hnh 1.1): CLBs (configurable Logic Blocks): cc khi logic c th cu hnh c, l cc thnh phn tiu chun. Trong hu ht cc FPGA, mi mt CLB cha mt s cc mnh, m mi mnh li cha mt s (thng l 2 hoc 4) logic (logic cell) vi mt s thnh phn nh (Flip-Flop) hoc b dn knh (Mux) nu khng dng FF. Mi logic c th c cu hnh thc hin cc chc nng logic c bn (nh AND, OR, NOT) trn cc tn hiu s nh s dng bng LUT (look-up Table). Cc CLB lin kt vi nhau qua mng lin kt c th lp trnh c (Programmable Interconnect hay routing). Interconnect hay Routing: mng lin kt hay nh tuyn, l cc ma trn chuyn mch c th lp trnh c - PSM (Programmable Switch Matrix) hnh thnh cc n v thc hin cc chc nng phc tp hn. IOBs (Input/Output Blocks): cc khi vo/ra nm bao xung quanh ca ming FPGA v ni vi cc chn tn hiu vo/ra (I/O pin). Nh vy tng chn I/O ca FPGA c th c lp trnh m bo cc giao tip in cn thit cho kt ni FPGA vi h thng m n l thnh phn (hnh 1.3). Block RAM: khi RAM, l cc bng nh bn trong FPGA. Ngoi ra cc thnh phn trn, FPGA cn cc logic nh khc, nh: MAC (Multiply-accumulate circuits): cc khi logic nhn tch ly, thc hin cc php nhn v cng hiu qu, Cc khi thc hin cc chc nng c bit: x l tn hiu s v tng t, v d cc b bin i tng t-s ADC (Analog-to-Digital Converter) v cc b bin i s-tng t DAC (Digital-to-Analog Converter), cho php FPGA vn hnh nh l mt SoC. Mt FPGA cha t 64 n hng chc ngn khi logic v cc flip-flop. LUT ging nh mt RAM nh, cng c gi l cc b to chc nng, FG (Function generator), c s dng thc hin cc chc nng logic nh ct gi trng thi logic ra ng trong mt vng nh, m trng thi logic ra tng ng vi tng t hp ca cc bin vo. LUT thng c 4 u vo c th thc hin bt k chc nng logic 4u vo. Cc thnh phn nh trong CLB c th c cu hnh hoc thnh cc cc Flip-flop hoc thnh cc mch cht (Latch). Mi CLB thng c b tr cc chn tn hiu vo v hai

chn tn hiu ra, nh ch ra hnh 1.2. Nh vy, c th kt ni chn tn hiu u t cc pha tng ng ca CLB, trong khi chn tn hiu u ra c th kt ni vi cc dy dn nh tuyn c knh pha bn phi v knh pha di ca CLB. Mi mt chn tn hiu u ra ca CLB c th kt ni vi bt k on ni dy no trong cc knh k cn vi n. Tng t, hp m vo/ra (I/Opad) nh ca chip FPGA c th ni vi bt k dy dn no knh nm ngang pha di. Cc nh sn xut c xu hng thit k cc khi logic ca FPGA thc hin cc chc nng ln hn gim lin kt cc b, ng ngha vi s lng chn tn hiu u vo ca khi logic tng ln, v n cng cho php lp trnh cc khi logic linh hot hn. V d, Xilinx c kin trc Virtex-5 FPGA da trn cp LUT 6-u vo vi tng s 64 bits ca khng gian lp trnh v 6 u vo c lp, v logic lin quan m bo u vit trong s dng cc ti nguyn so vi cc kin trc khc. N c th thc hin bt k chc nng no t 6 u vo c lp v cc t hp s ca mt hoc hai chc nng nh. LUT 6u vo cng bao gm c cc b cng (adder) vi logic carry, cc b dn knh (MUX), v flip-flop. N c th c s dng b xung nh l RAM 64-bit hay thanh ghi dch 32 bit (hnh 1.3). Kin trc ca h Altera Stratix FPGA t c hiu nng cao nh a vo module logic thch ng hiu qu vng - ALM (Adaptive logic Module). ALM gm c logic t hp, 2 thanh ghi, v 2 b cng, nh ch ra hnh 1.4. logic t hp c 8 u vo mt bng LUT (Lookup Table).

Hnh 1.3: Xilinx Virtex-5 FPGA LUT- cp FF

Hnh 1.4: Altera Stratix IV FPGA ALM

6-

(a)

54-

(e)

445354-

(b 6(f) (c) 6-

7(d

(g

Hnh 1.5: cu hnh linh hot ca ALM

Bng LUT c th c chia ra 2 ALUT (Adaptive LUT) vi tng s 64 bits ca khng gian lp trnh v 8 u vo chia s. N cng c th thc hin bt k chc nng no ca 6 u vo v cc t hp s ca mt hoc hai chc nng nh. ALM 8-u vo cho php cc kh nng cu hnh khc nhau nh ch ra hnh 1.5. H Stratix ca cc FPGA cng c hiu qu trong nh tuyn thng qua mng lin kt MultiTrackTM . C LUT-6 u vo v ALM u l nhng logic c bn xy dng cc khi ca cc kin trc FPGA v chng tng ng nhau (hnh 1.6).

Hnh 1.6: S thc hin chc nng 5-Input v 3- Input trong Stratix IV ALM v Virtex-5

Cc FPGA khc nhau c s lng cc logic, kch c v s lng cc block RAM, cc MAC khc nhau. Cc FPGA s dng trong cc h thng lai (hybrid system) thng c khong 100K-200K logic, 500KB ca RAM bn trong v 100 MACs. H thng lai c th s dng FPGA vi 1000 khi I/O tng ng vi 1000 I/O pin m bo cc giao tip vi h thng ch, cng nh vi b nh cc b ni trc vi FPGA. Cc FPGA thng c lp trnh sau khi hn gn trn bng mch in, tng t nh cc CPLD ln. Nhng d liu cu hnh trong FPGA b mt khi ngng cp ngun (mt in) ging nh RAM trong my tnh vy. Do , mui ln ngt ngun v bt li th ta phi np li tp cu hnh vo FPGA. Mun lu gi li cu hnh lp trnh cho FPGA th ta phi mc thm PROM hay EPROM ngoi. B nh ngoi ny c nhim v lu tp cu hnh dng nh phn (bitstream hay bit file) v t ng np d liu cu hnh li cho FPGA mi khi bt ngun, nh vy d c ngt ngun FPGA vn khng b mt d liu. Cc phin bn EEPROM c th c th lp trnh c trong h thng (hay trong mch), thng thng qua giao tip JTAG. Tp cu hnh cha cc thit lp cho tng CLB, PSM, MAC, I/O v cc thnh phn c th cu hnh khc ca FPGA. Cc FPGA c s dng trong cc h thng my tnh lai c th c lp trnh li v s ln. Thi gian ti cu hnh mi thng ch cha n 1 giy. Mt s FPGA hin nay c kh nng trong khi ang hot ng chuyn n cu hnh mi c np trc vo thit b. Mt s FPGA cng cho php cu hnh li tng phn ca thit b. FPGA v CPLD c nhng im khc bit l: FPGA bn trong da trn cc bng look-up (LUTs), trong khi cc CPLD hnh thnh cc chc nng logic bng cc nhiu mch cng (v d tng cc tch); FPGA v CPLD u cu to t cc khi logic (cc logic) l s kt hp ca mt khi logic v Flip-Flop. Nhng, FPGA c s lng ln cc khi logic (n hang trm ngn) hn nhiu so vi CPLD; FPGA ging nh RAM, phi np li d liu cu hnh mi khi bt ngun. CPLD ging nh EEPROM ch cn np mt ln v khng b mt chc nng sau khi ngt ngun; Do FPGA c s lng rt ln cc khi logic nn c nhiu ti nguyn thc hin nhiu chc nng ton hc chuyn dng v phc tp.V vy cc FPGA ph hp cho cc thit k phc tp hn so vi CPLD. Nhn chung cc CPLD l s la chn tt cho cc ng dng t hp, trong khi cc FPGA ph hp hn cho cc my trng thi ln (nh cc vi x l). FPGA c cc phn t logic chy theo dng song song. Cn vi iu khin da trn cu trc CPU thc thi theo m lnh theo dng tun t. FPGA dng ngn ng lp trnh phn cng (Verilog, VHDL) v lp trnh trn FPGA gi l lp trnh phn cng. Lp trnh vi iu khin l lp trnh phn mm phn cng c sn. 1.2. nh tuyn trong FPGA Lin kt bn trong tng CLB, lin kt gia cc khi logic vi nhau v vi cc khi I/O FPGA tr thnh mt thit b c chc nng ln phc tp l mt vn then cht nh hng n hiu nng ca FPGA. Bi v cc tr do nh tuyn s l ng k v ln hn so vi tr tng khi logic. Ngoi ra, v cc FPGA ngy cng i vo su ca cc qu

trnh ch to micron nh ca mch tch hp, nn t l ca ton b tr do nh tuyn tng ln vi tng th h ca qu trnh ch to. nh tuyn trong FPGA bao gm cc khi chuyn mch (SB) v cc dy ni. nh tuyn m bo kt ni gia cc khi I/O v cc khi logic v gia cc khi logic vi nhau. Kiu ca kin trc nh tuyn quyt nh vng c nh tuyn v mt cc khi logic. Khi chuyn mch nm giao ca cc knh nh tuyn dc (vertical routing channel) v ngang (horizontal routing channel).

Hnh 1.7: Kt ni trong khi chuyn mch

Ni chung, nh tuyn ca FPGA khng c phn on. Ngha l, tng on dy ni tri rng ch mt khi logic trc khi n kt thc mt khi (hay hp) chuyn mch, m trong mt khi chuyn mch c mt s chuyn mch c th lp trnh c. i vi lin kt tc cao, mt s kin trc ca FPGA s dng cc ng dy di nh tuyn tri n nhiu khi logic. nhng ch giao ca cc tuyn dy dc v ngang u c khi chuyn mch. Khi mt dy dn i vo khi chuyn mch, c ba chuyn mch (trong khi chuyn mch) cho php dy dn ni vi ba dn dn khc cc on knh k cn. Cu hnh ca cc chuyn mch trong khi chuyn mch l mt phng hai chiu. Trong cu hnh ny, cc dy dn rnh s 2 ch ni vi cc dy dn khc trong rnh s 2, v cc dy dn cc rnh khc cng c cch ni nh vy. Hnh 1.7 minh ha cc kt ni trong mt hp chuyn mch. Mt on dy dn (wire segment) l mt lin kt c hai im u cui, m gia hai im ny khng mt chuyn mch c th lp trnh c no. Mt chui ca mt hay nhiu on dy dn trong mt FPGA c xem nh l mt rnh (track). Cc knh nh tuyn ca FPGA gm cc on dy dn thuc mt s loi khc nhau, tu thuc vo nh sn xut. 1. Kin trc nh tuyn ca Xilinx FPGA: Cc nghin cu hn lm s dng mt m hnh kin trc chung n gin ca Xilinx FPGA cho hnh 1.8. Kin trc chung ny ca Xilinx FPGA gm c mt mng hai chiu cc khi logic c th lp trnh c CLB (configurable Logic Block), vi cc knh nh tuyn ngang v dc gia cc hng v cc ct ca cc CLB. Mi CLB c 4 u vo v mt u ra, v tt c cc khi logic l ging nhau.

Hnh 1.8: kin trc n gin ca Xilinx FPGA

Cc ti nguyn ca nh tuyn trong Xilinx FPGA gm: Cc khi kt ni (Connection Block): cc khi kt ni C ni cc dy dn ca knh nh tuyn vi cc chn tn hiu ca cc CLB. C hai c tnh nh hng chnh n kh nng nh tuyn ca thit k: tnh linh hot, Fc, l s dy dn m tng tn hiu ca CLB c th kt ni; v cu hnh, l mu ca cc chuyn mch to lp kt ni (c bit nu gi tr Fc thp).

CL B

CL B

CL B

CL B

CL B

CL B

CL B

CL B

Hnh 1.9: nh tuyn qua cc hp kt ni

V d, trong hnh 1.9, i vi hp C vi Fc=2, cu hnh 1 (topology 1) khng th ni chn A ca mt CLB vi chn B ca CLB khc, trong kh th cu hnh 2 (Topology 2) l c th. Cc khi chuyn mch (Switch Block): cc khi chuyn mch S cho php cc dy dn chuyn mch gia cc dy dc v ngang . Tnh linh hot, Fs, xc nh s lng cc on dy ni m mt on dy ni i vo trong khi S c th kt ni. Cu hnh ca cc khi chuyn mch S l rt quan trng bi v c th chn hai cu hnh khc nhau c cc

kh nng nh tuyn khc nhau vi cng mt gi tr tnh linh hot Fs. V d, hnh 1.12 m t cu hnh 1 (topology 1) c th ni chn tn hiu A ca mt CLB vi chn tn hiu B ca mt CLB khc, trong khi cu hnh 2 (Topology 2) th khng th.

Hnh 1.10: nh tuyn qua cc khi chuyn mch

Cc khi chuyn mch m ch kt ni cc rnh trong cng mt min, chng hn, 00, 1-1, c gi l cc khi chuyn mch ca tp hp con hay phng hai chiu (Subset switch box hay Planar). Cc khi chuyn mch m cho php kt ni vi bt k min no khc, chng hn, 0-3, 1-2, c gi l cc khi chuyn mch Wilton, v chng c s dng rng ri do m bo nh tuyn linh hot hn.

Hnh 1.11: Cc ng dy trong Xilinx FPGA

Cc ng dy di-n (Single-length lines): chng c dng cho cc kt ni tng i ngn gia cc CLB v chng tri rng ch qua mt CLB (hnh 1.11). Cc ng dy di-gp i (Double-length lines): chng tng t nh cc ng dy di-n, ngoi tr mi ng dy y tri rng qua hai CLB. Chng cho cc tr nh tuyn nh i vi kt ni di va phi (hnh 1.11). Cc ng dy di (Long lines): chng ph hp cho cc kt ni di tri rng mt s CLB (hnh 1.11). Hnh 1.12 minh ha cc kt ni nh tuyn cc ma trn chuyn. Khi chuyn mch C c thc hin vi cc transistors dn xut (pass transistor). Cc transistors dn xut cng ngh CMOS cho php thc hin mt chc nng logic vi rt t transistors, do n c u im l lm cho in dung thp. Chui cc transistors dn xut c s dng thit k cc mng logic ln nh ROM, PLA, v c cc b dn knh. V vy vi khi chuyn mch C s dng cc transistors dn xut th khng cn phi dng n cc b dn knh cho cc u vo kt ni. iu ny cho php hai hoc nhiu rnh hn c ht ni in qua chn tn hiu vo nh cc chuyn mch trong khi C.

Hnh 1.12: Ma trn chuyn mch trong Xilinx FPGA

Hnh 1.13 minh ha v nh tuyn trong mt Xilinx FPGA. Cc lin kt ca knh nh tuyn vi khi logic (LB) c to ra thng qua khi kt ni, CB (Connection Block). V cng ngh SRAM c s dng thc hin cc LUT, nn cc pha kt ni l rng. Khi logic c vy quay bi cc khi kt ni c bn pha kt ni. Cc CB ni ni cc chn tn hiu (pin) ca LB vi cc on dy. Cc chn tn hiu ca LB, m chng ni vi cc CB c th sau ni vi bt k s lng ca cc on dy thng qua cc khi chuyn mch, SB (Switch Block). Trong cu hnh ny c bn loi on dy: cc on dy

c mc ch chung (General purpose Interconnect): cc dy li ny i qua cc chuyn mch trong SB; lin kt trc tip (Direct Interconnect): kt ni cc chn tn hiu ca LB vi bn khi kt ni xung quanh LB; ng dy di (Long Line): l cc dy ni thng nht c h s tr phn u ra cao; v cc ng dy nhp ng h (Clock lines): dn tn hiu nhp ng h n tt c cc chip.
CB x : Routing xx x switch x x LB

S B B LB

S LB

General purpose Direct

S B LB S B LB

S B LB

S B LB

S B

S B LB S B

S B LB S B

S B

Routing

Long

Hnh 1.13: Kin trc nh tuyn ca Xilinx FPGA

2. Kin trc nh tuyn ca Actel FPGA: Kin trc ca Actel FPGA rt ging vi phn knh mng cng. Li ca FPGA gm cc module logic, LM (hay khi logic, LB) n gin c s dng thc hin cc cng logic theo yu cu, v cc thnh phn nh. Cc LM c lin kt vi nhau nh cc rnh nh tuyn chia theo cc on (segment). Khng ging cc mng cng, cc di ca cc on dy ni c xc nh trc v c th vi cc thnh phn chuyn mch tr khng thp to ra di nh tuyn chnh xc cho tn hiu lin kt. Xung quanh li logic l giao tip vi cc ming m vo/ra (I/O pad) ca thit b. Cc I/O pad ni vi cc chn tn hiu (pin) ca FPGA. Giao tip ny bao gm cc module vo/ra, I/OM (hay khi, I/OB) thc hin chuyn i v kt ni cc tn hiu logic t li n cc I/O pad.

Hnh 1.14 l s khi ca kin trc Actel FPGA. Cc thnh phn chnh ca kin trc Actel FPGA l cc I/OM, cc ti nguyn nh tuyn (cc knh nh tuyn), cc ti nguyn nhp ng h v tt c cc logic khc. Bn trong cc knh ngang v dc l cc rnh chy ngang v dc tng ng. Mi mt rnh c mt dy. Cc rnh ca knh nh tuyn c phn on (Channel-Oriented segmented Routing Tracks) chy xuyn sui chip theo chiu ngang v ti rng n tt c cc LM, cc I/OM. Theo chiu dc, cc knh tng t chy pha trn LM. iu c bit, c nhiu cc on dy dc theo chiu ngang hn l chiu dc. Cc khi chuyn mch (SB) c phn b thng qua cc knh chiu ngang. Tt c cc rnh chiu dc c th c mt kt ni vi tng rnh chiu ngang lin quan. iu ny cho php mt rnh chiu ngang c th linh hot chuyn mch vo mt rnh chiu dc, nh vy c th thc hin nh nh tuyn chiu ngang v chiu dc cng mt dy ni.Actel.

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O LM LM LM LM

I/O

I/O

I/O

CL

I/O

I/O

I/O

I/O

I/O I/O

Input/Outp ut module Logic modul

LM

LM

LM

LM

LM

LM

LM

LM

LM

I/O I/O

LM

LM

LM

LM

LM

LM

LM

LM

LM

I/O I/O

LM

LM

LM

LM

LM

LM

LM

LM

LM

I/O I/O ChannelOriented segmente d Routing

LM

LM

LM

LM

LM

LM

LM

LM

LM

I/O I/O

I/O

I/O

I/O

CL

I/O

I/O

I/O

I/O

I/O

Hnh 1.14: Kin trc nh tuyn ca Actel FPGA

Hnh 1.15: Cc knh nh tuyn ngang v dc ca ACT 1

Trong s nh tuyn ca h Actel ACT, mt knh nh tuyn chiu ngang (trong ACT 1) c ti 25 rnh, trong c 22 rnh ngang nh tuyn tn hiu vi 3 rnh trc tip dnh cho VDD, GND, v nhp ng h tng GCLK (global clock) (hnh 1.14). Cc on dy chiu ngang c chiu di khc nhau, t 4 ct cc LM ti ton b hng cc LM (hnh 1.15). Actel gi nhng on dy ny l nhng dy di - long lines).

Mi mt LM c 4 u vo cho mt knh nm pha di LM v 4 u vo khc cho mt knh pha trn LM. Nh vy c 8 rnh dc dnh cho 8 u vo ca mt LM. Cc kt ni ny c gi l mt mu vo (input stub). Mt u ra ca LM ni vi mt rnh dc, m rnh dc ny m rng qua 2 knh pha trn LM v qua hai knh pha di LM. l mu ra (output stub). Nh vy, cc u ra ca LM s dng 4 rnh dc cho tng LM (2 rnh pha t cc LM pha di, v 2 rnh t cc LM di v 2 rnh t cc LM pha trn tng knh. Mt rnh dc c gi l rnh dc di, LVT (long vertical track) nu n chy dc sut chiu cao ca chip. Nh vy c 13 rnh dc cho mt ct (mt LM) ca kin trc ACT 1 (8 cho cc u vo, 4 cho cc u ra, v 1 cho LVT). Nhc im ca phng php nh tuyn ny l n cn phi c nhiu chuyn mch trong FPGA, dn n ti in dung cao.

3. Kin trc nh tuyn ca Altera FPGA: Cc thit b FPGA ca lot Altera Stratix a vo lin kt MultiTrack ti a kt ni v hiu nng. Kin trc nh tuyn ca chng m bo lin kt gia cc cm (cluster) khc nhau ca cc khi logic, c gi l cc khi mng logic, LABs (Logic Array Blocks), v c th o bng s hop (bc nhy) cn thit t mt LAB t ti mt LAB khc.

Hnh 1.16: S mt ca kin trc nh tuyn trong Altera Stratix

nh tuyn c t chc nh s cc ng dy theo hng v ct. H Stratix s dng kin trc nh tuyn 3-mt nh cho hnh 1.33. iu ny c ngha l mt LAB c th tip cn vi tt c cc dy ni trn mt knh ngang (H) pha trn LAB v hai knh dc (V) pha bn tri v bn phi ca LAB. Cc knh cha cc dy chiu di 4, 8, 16, v 24, v cc tn hiu c th t ti bt k mt LAB no theo chiu di ca dy ni.

Hnh 1.17: Kt ni cc LAB trong Stratix FPGA

Hnh 1.34 ch ra s lng cc hops cn thit ni vi cc LAB t mt IntraLAB. u im ca kin trc nh tuyn ny l tnh u n ca thit k vt l ca silicon cho php n ng gi tit kim ch trng v hiu qu. Nhc im li l n cn nhiu chuyn mch, dn n ti in dung cao.

1.3. Cc kin trc ca FPGA C hai loi kin trc c bn ca FPGA: kin trc mt tha (Coarse-grained) v kin trc mt cao (fine-grained). Kin trc mt tha: c cc khi logic ln, mi khi logic thng cha hai hoc nhiu bng look-up (LUTs) v hai hoc nhiu flip-flop. Trong hu ht cc FPGA kin trc ny bng LUT 4-u vo (nh l 16x1 ROM) lm thnh mt logic c th. Loi kin trc ny s dng cng ngh cu ch i ngu CMS (anti-fuse CMOS), ch cho php lp trnh mt ln, nhng d liu khng b thay i khi b mt ngun. lp trnh cn phi c thit b lp trnh chuyn dng (thng do nh sn xut hay nh phn phi cung cp). Kin trc mt cao: c s lng ln cc khi logic n gin. Khi logic n gin hoc cha chc nng logic hai u vo hoc b dn knh 4-to-1 v mt flip-flop. Chng s dng cng ngh b nh SRAM, tng t nh cc b vi x l. Nh vy chng c th c lp trnh li khng hn ch trong h thng, nhng i hi phi c b nh PROM. EPROM, EEPROM hay Flash bn ngoi (gi l b nh cu hnh) lu tr chng trnh xc nh cc chc nng nh th no ca tng khi logic, cc khi I/O no l cc cng vo v cc cng ra, v cc khi c lin kt vi nhau nh th no. FPGA hoc l t np b nh cu hnh ca n hoc b x l bn ngoi ti ni dung ca b nh cu hnh vo FPGA. Khi thc hin t np, FPGA a ch cc byte ca b nh cu hnh ging nh b x l a ch b nh PROM lu cu hnh khi to (boot PROM), hoc s dng PROM tun t truy nhp lin tip. Khi b x l ti vo FPGA, FPGA th hin nh l b x l ngoi vi chun. Thi gian cu hnh thng nh hn 200 ms, ph thuc vo kch thc ca FPGA v phng php cu hnh. Bng 1.3 cho danh sch cc nh sn xut FPGA vi cc kin trc tng ng. Bng 1.3. Cc kin trc FPGA, cng ngh v cc nh cung cp Kin trc Static Memory Altera: (FLEX, APEX) Atmel: (AT40K) Mt tha DynaChip (CoarseLucent: (ORCA) grained) Vantis: (VF1) Xilinx: (XC3000,XC4000xx,Spartan,Virtex) Mt cao Actel: (SPGA) (Fine-grained) Atmel: (AT6000) Anti-Fuse Flash

QuickLogic: (pASIC)

Actel: (ACT)

Gatefield

CHNG II: GII THIU V CPU 8BIT

2.1. S khi ca CPU 8bit: Cu trc ca tt c cc vi x l u c cc khi c bn ging nhau nh ALU, cc thanh ghi, khi iu khin l cc mch logic. nm r nguyn l lm vic ca vi x l cn phi kho st nguyn l kt hp cc khi vi nhau x l mt chng trnh. S khi ca vi x l s trnh by cu trc ca mt vi x l. Mi mt vi x l khc nhau s c cu trc khc nhau. V d vi x l 8 bit s c cu trc khc vi vi x l 16 bit... Vi mi vi x l u c mt s cu trc bn trong v c cho trong cc s tay ca nh ch to. S cu trc dng khi rt tin li v d trnh by nguyn l hot ng ca vi x l. Hnh 2-1 trnh by s khi ca vi x l 8 bit:

Hnh 2.1: S cu trc bn trong ca vi x l Trong s khi ca vi x l bao gm cc khi chnh nh sau: khi ALU, cc thanh ghi v khi control logic. Ngoi ra s khi cn trnh by cc ng truyn ti tn hiu t ni ny n ni khc bn trong v bn ngoi h thng.

2.2 : ALU (Arithmetic Logic Unit) : B s hc - logic ALU l khi quan trng nht ca vi x l, khi ALU cha cc mch in t logic chuyn v x l d liu. Khi ALU c 2 ng vo c tn l IN - l cc ng vo d liu cho ALU x l v 1 ng ra c tn l OUT - l ng ra kt qu d liu sau khi ALU x l xong. D liu trc khi vo ALU c cha thanh ghi tm thi (Temporarily Register) c tn l TEMP1 v TEMP2. Bus d liu bn trong vi x l c kt ni vi 2 ng vo IN ca ALU thng qua 2 thanh ghi tm thi. Vic kt ni ny cho php ALU c th ly bt k d liu no trn bus d liu bn trong vi x l. Thng th ALU lun ly d liu t mt thanh ghi c bit c tn l Accumulator (A). Ng ra OUT ca ALU cho php ALU c th gi kt d liu sau khi x l xong ln bus d liu bn trong vi x l, do thit b no kt ni vi bus bn trong u c th nhn d liu ny. Thng th ALU gi d liu sau khi x l xong ti thanh ghi Accumulator. V d khi ALU cng 2 d liu th mt trong 2 d liu c cha trong thanh ghi Accumulator, sau khi php cng c thc hin bi ALU th kt qu s gi tr li thanh ghi Accumulator v lu tr thanh ghi ny. ALU x l mt d liu hay 2 d liu ty thuc vo lnh hay yu cu iu khin, v d khi cng 2 d liu th ALU s x l 2 d liu v dng 2 ng vo IN nhp d liu, khi tng mt d liu no ln 1 n v hay ly b mt d liu, khi ALU ch x l 1 d liu v ch cn mt ng vo IN. Khi ALU c th thc hin cc php ton x l nh sau: Add Complement OR Exclusive OR Subtract Shift right Increment AND Shift left Decrement Tm Tt: Chc nng chnh ca khi ALU l lm thay i d liu hay chuyn v x l d liu nhng khng lu tr d liu. hiu r thm chc nng c bit ca ALU cn phi kho st mt vi x l c th. 2.3. Thanh ghi 2.3.1. Cc thanh ghi bn trong ca vi x l: Cc thanh ghi bn trong c chc nng lu tr tm thi cc d liu khi x l. Trong s cc thanh ghi c mt vi thanh ghi c bit thc hin cc lnh c bit hay cc chc nng c bit, cc thanh ghi cn li gi l cc thanh ghi thng dng. Vi s khi minh ha trn, cc thanh ghi thng dng c tn Reg B, Reg C, Reg D, Reg E. Cc thanh ghi thng dng rt hu dng cho ngi lp trnh dng lu tr d liu phc v cho cng vic x l d liu v iu khin, khi vit chng trnh chng ta lun s dng cc thanh ghi ny. S lng cc thanh ghi thng dng thay i ty thuc vo tng vi x l.

S lng v cch s dng cc thanh ghi thng dng ty thuc vo cu trc ca tng vi x l, nhng chng c mt vi im c bn ging nhau. Cng nhiu thanh ghi thng dng th vn lp trnh cng tr nn n gin. Cc thanh ghi c bn lun c trong mt vi x l l thanh ghi A (Accumulator Register), thanh ghi b m chng trnh PC (Program Counter register), thanh ghi con tr ngn xp SP (Stack pointer register), thanh ghi trng thi F (Status register -Flag register), cc thanh ghi thng dng, thanh ghi lnh IR (Instruction register), thanh ghi a ch AR (Address Register).

Hnh 2.2 : S minh ha cc thanh ghi bn trong ca Microprocessor c t m

2.3.2:Chc nng ca cc thanh ghi a. Thanh ghi Accumulator: Thanh ghi A l mt thanh ghi quan trng ca vi x l c chc nng lu tr d liu khi tnh ton. Hu ht cc php ton s hc v cc php ton logic u xy ra gia ALU v Accumulator. V d khi thc hin mt lnh cng 1 d liu A vi mt d liu B, th mt d liu phi cha trong thanh ghi Accumulator gi s l d liu A, sau s thc hin lnh cng d liu A (cha trong Accumulator) vi d liu B (c th cha trong nh hoc trong mt thanh ghi thng dng), kt qu ca lnh cng l d liu C s c t trong thanh ghi A thay th cho d liu A trc . Ch : Kt qu sau khi thc hin ALU thng gi vo thanh ghi Accumulator lm cho d liu trc cha trong Accumulator s mt. Mt chc nng quan trng khc ca thanh ghi Accumulator l truyn d liu t b nh hoc t cc thanh ghi bn trong ca vi x l ra cc thit b iu khin bn ngoi th d liu phi cha trong thanh ghi Accumulator. Thanh ghi Accumulator cn nhiu chc nng quan trng khc s c thy r qua tp lnh ca mt vi x l c th, s bit ca thanh ghi Accumulator chnh l n v o ca vi x l, vi x l 8 bit th thanh ghi Accumulator c di 8 bit. b. Thanh ghi b m chng trnh PC (Program counter): Thanh ghi PC l mt thanh ghi c vai tr quan trng nht ca vi x l. Chng trnh l mt chui cc lnh ni tip nhau trong b nh ca vi x l, cc lnh ny s yu cu vi x l thc hin chnh xc cc cng vic gii quyt mt vn . Tng lnh phi n gin v chnh xc v cc lnh phi theo ng mt trnh t chng trnh thc hin ng. Chc nng ca thanh ghi PC l qun l lnh ang thc hin v lnh s c thc hin tip theo. Thanh ghi PC trong vi x l c chiu di t d liu ln hn chiu di t d liu ca vi x l. V d i vi cc vi x l 8 bit c th giao tip vi 65536 nh th thanh ghi PC phi c chiu di l 16 bit c th truy xut tng nh bt u t nh th 0 n nh th 65535. Ch : ni dung cha trong thanh ghi PC chnh l ni dung cha trong thanh ghi a ch. Trc khi vi x l thc hin mt chng trnh th thanh ghi PC phi c np mt con s : chnh l a ch ca nh cha lnh u tin ca chng trnh. a ch ca lnh u tin c gi n IC nh thng qua bus a ch 16 bit. Sau b nh s t ni dung ca nh ln bus d liu, ni dung ny chnh l m lnh, qu trnh ny gi l n lnh t b nh. Tip theo vi x l t ng tng ni dung ca thanh ghi PC chun b n lnh k. PC ch c tng khi vi x l bt u thc hin lnh c n trc . Lnh ang thc hin c chiu di bao nhiu byte th thanh ghi PC tng ln ng by nhiu byte.

Mt vi lnh trong chng trnh c th np vo thanh ghi PC mt gi tr mi, khi lnh lm thay i thanh ghi PC sang gi tr mi c thc hin th lnh k c th xy ra mt a ch mi - i vi cc lnh nhy hoc lnh gi chng trnh con. c. Thanh ghi trng thi (Status Register):

Hnh 2-3. Cu trc ca mt thanh ghi trng thi. Thanh ghi trng thi cn c gi l thanh ghi c (Flag register) dng lu tr kt qu ca mt s lnh kim tra. Vic lu tr cc kt qu kim tra cho php ngi lp trnh thc hin vic r nhnh trong chng trnh. Khi r nhnh, chng trnh s bt u ti mt v tr mi. Trong trng hp r nhnh c iu kin th chng trnh r nhnh ch c thc hin khi kt qu kim tra ng iu kin. Thanh ghi trng thi s lu tr cc kt qu kim tra ny. Cc bit thng c trong mt thanh ghi trng thi c trnh by hnh 2-3.

Cc lnh xy ra trong khi ALU thng nh hng n thanh ghi trng thi, v d khi thc hin mt lnh cng 2 d liu 8 bit, nu kt qu ln hn 11111111 th bit carry s mang gi tr l 1. Ngc li nu kt qu ca php cng nh hn 11111111
2

bng 0. V d lnh tng hay gim gi tr ca mt thanh ghi, nu kt qu trong thanh ghi khc 0 th bit Z lun bng 0, ngc li nu kt qu bng 0 th bit Z bng 1. V d v r nhnh khi kim tra bit trong thanh ghi trng thi: hy vit mt chng trnh gim gi tr ca mt thanh ghi c gi tr l 10. 1. Np vo thanh ghi mt s nh phn c gi tr l 10. 2. Gim ni dung ca thanh ghi i 1. 3. Kim tra bit Zero ca thanh ghi trng thi c bng 1 hay khng ? 4. Nu khng nhy n thc hin tip lnh bc 2 5. Nu ng kt thc chng trnh. ngha ca cc bit trong thanh ghi trng thi: [a]. Carry/borrow (c trn/mn): l bit carry khi thc hin mt php cng c gi tr ty thuc vo kt qu ca php cng. Kt qu trn th bit carry =1, ngc li bit carry = 0. L bit borrow khi thc hin mt php tr: nu s b tr ln hn s tr th bit borrow = 0, ngc li bit borrow =1. Bit carry hay bit borrow l 1 bit ch c phn bit khi thc hin lnh c th. [b]. Zero: bit Z bng 1 khi kt qu ca php ton bng 0, ngc li bit Z=0. [c]. Negative (c s m): bit N = 1 khi bit MSB ca thanh ghi c gi tr l 1, ngc li N=0. [d]. Intermediate carry (c trn ph): ging nh bit Carry nhng ch c tc dng i vi php cng hay tr 4 bit thp. [e]. Interrupt Flag (c bo ngt): Bit IF c gi tr l 1 khi ngi lp trnh mun cho php ngt, ngc li th khng cho php ngt. [f]. Overflow (c trn s c du): bit ny bng 1 khi bit trn ca php ton cng vi bit du ca d liu. [g]. Parity (c chn l): bit ny c gi tr l 1 khi kt qu ca php ton l s chn, ngc li l s l th bit P = 0. S lng cc bit c trong thanh ghi trng thi ty thuc vo tng vi x l. Trong mt s vi x l c th xa hoc t cc bit ca thanh ghi trng thi. d. Thanh ghi con tr ngn xp (Stack Pointer Register): Thanh ghi con tr ngn xp l mt thanh ghi quan trng ca vi x l, di t d liu ca thanh ghi SP bng thanh ghi PC, chc nng ca thanh ghi SP gn ging nh thanh ghi PC nhng n dng qun l b nh ngn xp khi mun lu tr tm thi d liu vo ngn xp.

th bit carry

Ging nh thanh ghi PC, thanh ghi SP cng t ng ch n nh k. Trong hu ht cc vi x l, thanh ghi SP gim ( ch n nh tip theo trong ngn xp) sau khi thc hin lnh ct d liu vo ngn xp. Do khi thit lp gi tr cho thanh ghi SP l a ch cui cng ca b nh. Thanh ghi SP phi ch n mt nh do ngi lp trnh thit lp, qu trnh ny gi l khi to con tr ngn xp. Nu khng khi to, con tr ngn xp s ch n mt nh ngu nhin. Khi d liu ct vo ngn xp c th ghi ln d liu quan trng khc lm chng trnh x l sai hoc thanh ghi SP ch n vng nh khng phi l b nh RAM lm chng trnh thc hin khng ng v khng lu tr c d liu cn ct tm vo b nh ngn xp. T chc ca ngn xp l vo sau ra trc (LAST IN FIRST OUT : LIFO). e. Thanh ghi a ch b nh (address Register): Mi khi vi x l truy xut b nh th thanh ghi a ch phi to ra ng a ch m vi x l mun. Ng ra ca thanh ghi a ch c t ln bus a ch 16 bit. Bus a ch dng la chn mt nh hay la chn 1 port Input/Output. Ni dung ca thanh ghi a ch nh v ni dung ca thanh ghi PC l ging nhau khi vi x l truy xut b nh n lnh, khi lnh ang c gii m th thanh ghi PC tng ln chun b n lnh tip theo, trong khi ni dung ca thanh ghi a ch b nh khng tng, trong sut chu k thc hin lnh, ni dung ca thanh ghi a ch ph thuc vo lnh ang c thc hin, nu lnh yu cu vi x l truy xut b nh th thanh ghi a ch b nh c dng ln th 2 trong khi thc hin mt lnh. Trong tt c cc vi x l, thanh ghi a ch b nh c chiu di bng vi thanh ghi PC. f. Thanh ghi lnh (instruction Register): Thanh ghi lnh dng cha m lnh vi x l ang thc hin. Mt chu k lnh bao gm n lnh t b nh v thc hin lnh. u tin l lnh c n t b nh, sau PC ch n lnh k trong b nh. Khi mt lnh c n c ngha l d liu trong nh c copy vo vi x l thng qua bus d liu n thanh ghi lnh. Tip theo lnh s c thc hin, trong khi thc hin lnh b gii m lnh c ni dung ca thanh ghi lnh. B gii m s gii m lnh bo cho vi x l thc hin chnh xc cng vic m lnh yu cu. Chiu di t d liu ca thanh ghi lnh ty thuc vo tng vi x l. Thanh ghi lnh do vi x l s dng ngi lp trnh khng c s dng thanh ghi ny. g. Thanh ghi cha d liu tm thi (Temporary data Register):

Thanh ghi lu tr d liu tm thi dng ALU thc hin cc php ton x l d liu. Do ALU ch x l d liu khng c chc nng lu tr d liu, bt k d liu no a n ng vo ca ALU, lp tc s xut hin ng ra. D liu xut hin ti ng ra ca ALU c quyt nh bi lnh trong chng trnh yu cu ALU thc hin. ALU ly d liu t bus d liu bn trong vi x l, x l d liu, sau t d liu va x l xong tr li thanh ghi Accumulator, do cn phi c thanh ghi lu tr d liu tm thi ALU thc hin. Ngi lp trnh khng c php x dng cc thanh ghi tm thi. S lng cc thanh ghi ny ty thuc vo tng vi x l c th. 2.4. Khi iu khin logic (control logic) v khi gii m lnh (instruction decoder): Chc nng ca khi gii m lnh l nhn lnh t thanh ghi lnh sau gii m gi tn hiu iu khin n cho khi iu khin logic. Cc tn hiu iu khin ca khi iu khin logic l cc tn hiu iu khin b nh, iu khin cc thit b ngoi vi, cc ng tn hiu c-ghi, ...v cc tn hiu iu khin vi x l t cc thit b bn ngoi. Cc ng tn hiu ny s c trnh by c th trong s ca tng vi x l c th. Ng tn hiu vo quan trng nht ca khi iu khin logic l tn hiu clock cn thit cho khi iu khin logic hot ng. Nu khng c tn hiu clock th vi x l khng lm vic. Mch to xung clock l cc mch dao ng, tn hiu c a n ng vo clock ca vi x l. C nhiu vi x l c tch hp mch to dao ng bn trong, khi ch cn thm t thch anh bn ngoi. Chc nng ca khi iu khin logic (control logic) l nhn lnh hay tn hiu iu khin t b gii m lnh, sau s thc hin ng cc yu cu ca lnh. Khi iu khin logic c xem l mt vi x l nh nm trong mt vi x l. 2.4.1. Bus d liu bn trong vi x l: Bus d liu dng kt ni cc thanh ghi bn trong v ALU vi nhau, tt c cc d liu di chuyn trong vi x l u thng qua bus d liu ny. Cc thanh ghi bn trong c th nhn d liu t bus hay c th t d liu ln bus nn bus d liu ny l bus d liu 2 chiu. Bus d liu bn trong c th kt ni ra bus bn ngoi khi vi x l cn truy xut d liu t b nh bn ngoi hay cc thit b IO. Bus d liu bn ngoi cng l bus d liu 2 chiu v vi x l c th nhn d liu t bn ngoi hay gi d liu ra. bit trnh t lm vic ca bus d liu bn trong vi x l hot ng, hy cho vi x l thc hin mt lnh cng 2 s nh phn cha trong thanh ghi 2 thanh ghi: thanh ghi Accumulator (gi tt l A) =1101 1110 v thanh ghi D=1101 1010 Trnh t cng nh sau: Trc khi thc hin lnh cng, ni dung ca 2 thanh ghi phi cha 2 d liu v 2 thanh ghi ny c th ang kt ni vi cc thit b khc. thc hin lnh cng ni dung 2 thanh ghi A v D th thanh ghi lnh phi mang ng m lnh ca php cng ny v gi s m lnh l ADD. c trnh by hnh 2-4. D liu ca thanh ghi A c t ln bus d liu bn trong vi x l, mt trong 2 thanh ghi lu tr d liu tm thi c kt ni vi Bus d liu. Thanh ghi tm
2 2

thi s copy d liu cha trong thanh ghi A. Ch c thanh ghi A v thanh ghi tm thi c kt ni vi bus ti thi im ny. Xem hnh 2-5 D liu ca thanh ghi D c kt ni vi bus d liu v thanh ghi tm thi cn li cng c php kt ni vi bus d liu. Thanh ghi tm thi s copy ni dung ca thanh ghi D. Ch c thanh ghi D v thanh ghi tm thi c kt ni vi bus ti thi im ny. Xem hnh 2-6. ALU s cng trc tip 2 d liu ti 2 ng vo. Ng ra ca ALU c kt ni vi thanh ghi A, kt qu ca php cng c np vo thanh ghi A. Xem hnh 2-7. Sau khi t kt qu vo trong thanh ghi A v cp nht s thay i cc bit trong thanh ghi trng thi th s kt ni gia thanh A v khi ALU chm dt, cc thanh ghi tm thi tr li trng thi sn sng cho lnh tip theo. Xem hnh 2-8 Php cng 2 s nh phn: 1101 1110 + 1101 1010 1 1011 1000 Carry negative

Hnh 2.4: D liu trc khi cng

Hnh 2-5. D liu thanh ghi A c a n thanh ghi Temp1.

Hnh 2-6. D liu thanh ghi D c a n thanh ghi Temp2.

Hnh 2-7. Kt qu lu tr li thanh ghi A.

Hnh 2-8. Cc thanh ghi tm tr li trng thi ban u.

2.5. Tp lnh ca vi x l 2.5.1. Tp lnh ca vi x l Lnh ca vi x l l mt d liu s nh phn, khi vi x l c mt lnh th t d liu nh phn ny s yu cu vi x l lm mt cng vic n gin. Mi mt t d liu tng ng vi mt cng vic m vi x l phi lm. Hu ht cc lnh ca vi x l l cc lnh chuyn d liu v x l d liu. Khi ni n tp lnh ca vi x l tc ni n tt c cc lnh m vi x l c th hiu v thc hin c. Nu tp lnh ca mt vi x l ging vi tp lnh ca mt vi x l khc th cu trc ca 2 vi x l ging nhau. di ca mt lnh bng vi di t d liu ca vi x l, i vi vi x l 8 bit th di ca mt lnh l 8 bit, i vi vi x l 16 bit th di ca mt lnh l 16 bit, ... Trong chu k n lnh, m lnh s c gi n thanh ghi lnh, b gii m lnh, v b iu khin logic ca vi x l. Chc nng ca cc khi s xc nh lnh ny lm g v s gi cc tn hiu iu khin n cc mch in logic khc trong vi x l, cc tn hiu logic ny s thc hin ng chc nng m lnh yu cu. Hnh 2-9 minh ha chu k thc hin lnh:

n lnh t b nh

Gai m lnh

Thc hin lnh

Hnh 2-9: Chu trnh thc hin lnh ca Vi x l Mt lnh c thc hin cn phi hi 2 yu t: Yu t th nht l lnh s yu cu vi x l thc hin cng vic g. V d yu cu vi x l thc hin mt lnh cng: ADD, mt lnh dch chuyn d liu: MOV, ... l nhng lnh m vi x l c thc hin c. Yu t th hai l lnh phi cho vi x l bit cc thng tin a ch tc l v tr ca cc d liu m vi x l phi thc hin. V d khi thc hin mt lnh cng ni dung 2

thanh ghi A v B, hoc ni dung thanh ghi A v d liu cha trong mt nh. Yu t th 2 trong trng hp ny l cc thanh ghi A v B, hoc thanh ghi A v a ch ca nh. Yu t th nht gi l m lnh : op code (operation code) v yu t th 2 gi l a ch. M lnh s bo cho vi x l lm g v a ch s cho vi x l bit v tr ca d liu. S hnh 2-10 minh ha cho cu trc 1 lnh.
Op code Op code

hoc
Address

Address

Address

Hnh 2-10. Cu trc ca mt lnh bao gm m lnh v a ch. T d liu u tin lun l m lnh, cc t d liu tip theo l a ch. i vi cc lnh ch c mt t d liu th a ch c hiu ngm. Do c nhiu cch ch cho vi x l bit a ch ca d liu c gi l cc kiu truy xut b nh. Khi s dng mt vi x l cn phi bit cc kiu truy xut ny. 2.5.2. Cc nhm lnh c bn ca vi x l i vi hu ht cc vi x l tp lnh c chia ra lm 9 nhm lnh c bn: Nhm lnh truyn d liu: Data transfers. Nhm lnh trao i, truyn khi d liu, lnh tm kim: Exchanges, Block transfers, Searches. Nhm lnh s hc v logic: arithmetic and logic. Nhm lnh xoay v dch: Rotates and shifts. Nhm lnh iu khin CPU. Nhm lnh v bit: Bit set, bit reset, and bit test. Nhm lnh nhy: Jumps. Nhm lnh gi, tr v v nhm lnh bt u: Calls, Return, and Restarts. Nhm lnh xut nhp: Input and Output. Cc m gi nh v cc m nh phn ca tt c cc lnh s c cho trong cc s tay ca nh ch to i vi tng vi x l c th. 2.5.3. Cc kiu truy xut a ch ca mt vi x l Nh trnh by cc phn trn, vi x l c th truy xut b nh bng nhiu cch ly d liu. Vi x l c nhiu cch truy xut th chng trnh khi vit s cng ngn gn rt c li cho ngi lp trnh v lm gim thi gian thc hin chng trnh.

Ch : Danh t truy xut b nh c ngha l to ra a ch truy xut d liu, vi x l truy xut d liu c th l ly d liu t nh hoc lu tr d liu vo nh. C th gi l cc kiu a ch ha b nh hay cc kiu to a ch truy xut b nh. bit vi x l c bao nhiu cch truy xut b nh cn phi kho st tng vi x l c th. Cc kiu truy xut c cho trong cc s tay ch to. Cc kiu truy xut a ch c bn ca mt vi x l (c gi tt l kiu nh a ch): Kiu nh a ch tc thi (Immediate Addressing Mode). Kiu nh a ch ngm nh (Implied Addressing Mode). Kiu nh a ch trc tip (Direct Addressing Mode). Kiu nh a ch gin tip dng thanh ghi (Register Indirect Addressing Mode). Kiu nh a ch ch s (Indexed Addressing Mode). Kiu nh a ch tng i (Relative Addressing Mode). a. Kiu nh a ch ngm nh: hiu cc kiu truy xut phi dng tp lnh ca mt vi x l 8 bit. V d lnh cng: ADD reg Lnh ny c hiu l ni dung ca thanh ghi A c cng vi ni dung ca thanh ghi Reg kt qu lu tr vo thanh ghi A. b. Kiu nh a ch tc thi: Mt lnh c chia ra lm 2 phn th nht l m lnh hay cn gi l m cng tc, phn th 2 l a ch. i vi kiu a ch tc thi th phn th 2 l d liu khng phi l a ch. V d lnh np mt d liu tc thi vo thanh ghi A c vit nh sau: MVI A, FE . Trong MVI l m gi nh, FE l d liu dng s Hex. V thanh ghi A ch c 8 bit nn d liu tc thi c di l 8 bit. c. Kiu nh a ch trc tip: V d lnh di chuyn ni dung ca mt nh c a ch 8000 LDA 8000 . LDA l m gi nh, a ch 8000
H H H

c vit trc tip trong cu lnh, vi

vo thanh ghi A:

vi x l 8 bit c 16 ng a ch nn phi dng 4 s Hex ch nh mt nh. i vi nhng lnh dng kiu a ch trc tip th lnh c di l 3 byte: mt byte l m lnh, 2 byte cn li l a ch ca nh (i vi vi x l 8 bit). d. Kiu nh a ch gin tip dng thanh ghi: minh ha kiu a ch gin tip dng thanh ghi ta dng lnh sau:

V d: MOV A,M. Lnh ny s di chuyn ni dung ca nh M c a ch cha trong mt cp thanh ghi. i vi vi x l 8085 th a ch ny thng cha trong cp thanh ghi HL, v a ch 16 bit nn phi dng cp thanh ghi mi cha ht 16 bit a ch. Ch khi dng lnh kiu ny ngi lp trnh phi qun l gi tr trong cp thanh ghi. e. Kiu nh a ch ch s: i vi mt vi vi x l c cc thanh ghi ch s (Index register) c dng cho kiu a ch ch s. Kiu a ch ny c thc hin bng cch cng byte th 2 ca lnh vi ni dung ca thanh ghi ch s ID. V d: lnh cng ni dung thanh ghi A vi ni dung ca nh c a ch cha trong thanh ghi ch s ID vi byte d liu th 2: ADD A, (ID +n) n l mt s c chiu di 8 bit. f. Kiu nh a ch tng i Kiu a ch ny gn ging nh kiu a ch ch s nhng thanh ghi ID c thay th bng thanh ghi PC. a ch ca nh cn truy xut c tnh bng cch cng ni dung hin ti cha trong thanh ghi PC cng vi byte d liu th 2. V d lnh JP 05 : nhy n ti thc hin lnh c a ch cch b m chng trnh PC l 5 byte.
H

CHNG III: KIT PHT TRIN SPARTAN-3E FPGA

 np chng trnh vo chp FPGA ta s dng Kit pht trin SPARTAN -3E. C mt s kit Spartan-3 cho pht trin FPGA nh: Xilinx Spartan-3AN Starter Kit, Spartan-3 PCI Express Starter Kit, Xilinx Spartan-3 Evaluation Kit, Xilinx Spartan-3 Development Kit, Spartan-3 LC Evaluation Kit, Xilinx Spartan-3 Mini-Module, Spartan3 MB Development Kit, v Xilinx Spartan-3E Starter Kit. Trong Xilinx Spartan-3E Starter kit h tr h Spartan-3E FPGA c cc c tnh cnh tranh nh: chi ph thp, to cc thit k logic lp trnh l tng. Spartan-3E l h th 7 trong cc lot Spartan ga r v l h th ba ca Xilinx c sn xut bng cng ngh qu trnh 90nm cao cp, a dng vi ga mt logic r nht trong cng nghip. 3.1. c im ca bng Xilinx Spartan-3E 500k starter kit Bng Xilinx Spartan 3E 500k starter kit (hnh 3.1) l mt thit b pht trin mnh cc thit k phn cng s. N cha ti 500k cng cho php thit k cc h thng phc tp bao gm c b x l mm MicroBlaze RISC vi cc giao tip DDR. Bng c trang b kh nng lp trnh JTAG thng qua cng USB2 trn bng, cc cp song song bn ngoi hoc USB. FPGA h tr cu hnh thng qua b nh flash trn bng mch ca Xilinx, Intel StrataFlash, ST Microelectonics Serial Flash v cc la chn khc. Bng pht trin ny hon ton tng thch vi tt c cc phin bn ca cc cng c Xilinx ISE k c phn mm min ph WebPack. Bng pht trin ny cng tng thch vi Xilinx Embedded Development Kit (EDK) vi trang b li 32-bit MicroBlaze RISC soft processor v cng tng thch vi PicoBlaze ca Xilinx. 3.1.1.Cc c im chnh ca bng pht trin: Thit b Xilinx: Spartan-3E FPGA (XC3S500E-4FG320C), 320-pin FBGA package CoolRunnerTM-II CPLD (XC2C64A-5VQ44C) Platform Flash (XCF04S-VO20C) Clocks: 50 MHz Crystal clock oscillator Memory: 128 Mbit Parallel Flash 16 Mbit SPI Flash 64 MByte DDR SDRAM Connector v Interfaces: Cng ni chut PS/2 hoc bng phm Cng ni hin th VGA 10/100 Ethernet PHY (yu cu Ethernet MAC in FPGA) Hai cng 9-pin RS-232 (DTE- and DCE-style) Giao tip trn bng USB-based FPGA/CPLD cho download/debug 3 Digilent 6-pin connectors m rng 4-output, SPI-based Digital-to-Analog Converter (DAC)

 2-input, SPI-based Analog-to-Digital Converter (ADC) vi programmablegain pre-amplifier ChipScope SoftTouch debugging port Rotary-encoder vi push-button shaft 8 discrete LEDs, 4 slide switches, 4 push-button switches SMA clock input 8-pin DIP socket cho ngun to nhp ng h bn ngoi Texas Instruments TPS75003 Triple-Supply Power Managent IC Display: 16 k t - 2 dng LCD Ngun: Adaptor 100-240V, 50/60 Hz Lp trnh: Lp trnh JTAG qua cng USB2 trn bng, cc cp USB hoc cp song song bn ngoi FPGA h tr mt s la chn cu hnh gm flash trn bng, SPI flash, v flash song song. ISE WebvPACKTM software, ISE FoundationTM software evaluation, v Kit pht trin nhng (EDK). Handbook: Introduction to Programmable Logic Design Quick Start Starter Kit resource CD USB cable.

Hnh 3.1: S khi ca bng pht trin Spartan 3E 500K

Hnh 3.2: Cu trc bn trong ca Spartan 3E 500K FPGA

3.2. B x l mm 32-bit MicroBlaze Cc b vi x l sn c s dng trong cc FPGA ca Xilinx vi cc cng c phn mm Xilinx EDK c th c chia thnh hai loi: cc vi x l li-mm (MicroBlaze) v vi x l li-cng (PowerPC). Cc vi x l li-mm MicroBlaze c s dng trong hu ht cc h Spartan-II, Spartan-3, Spartan-3E, v Virtex FPGA. Cc vi x l li-cng nhng l b x l IBM PowerPC 405, v cng c trong Virtex-II Pro v Virtex-4 FX FPGA. Chng c sn xut sn trong cc chip, v vy y ta ch xt n cc vi x l li-mm. B x l MicroBlaze l b x l 32-bit kin trc RISC c ti u thc ghin trong cc Xilinx FPGA vi cc bus lnh v d liu 32-bit ring bit chy tc y thc hin cc chng trnh v truy nhp d liu t b nh bn trong chip v t b nh bn ngoi chip ng thi. Xng sng ca kin trc MicroBlaze l ng ng 3-giai on mt ng ra vi tp cc thanh ghi chung 32-bit, ALU, n v dch, v hai mc ngt (hnh 3.3). Kin trc c bn ny ca McroBlaze c th sau c cu hnh thm nhng khi chc nng khc cho ph hp vi ng dng nhng nh: b dch (barrel shifter), b chia (divider), b nhn (multiplier), n v du phy ng (FPU), cc cache lnh v d

liu (8KB I-cache, 8KB D-cache), x l ngoi l, logic g ri (debug logic), giao tip lin kt n cng nhanh FSL (Fast Simplex Link),v.v Tnh linh hot ny cho php ngi s dng cn bng hiu nng yu cu ca ng dng i li vi chi ph vng logic ca b x l. V MicroBlaze l b x l li-mm, nn bt k c tnh no khng c s dng s khng c thc hin v s khng s khng ly bt k ti nguyn no bn trong FPGA. V MicroBlaze c m hnh kin trc Havard, trong bus d liu v cc cng I/O (cc cng I/O l mt phn trong b nh) c tch ring vi bus ca lnh, nn c th tham chiu ng thi lnh v d liu. ng ng ca MicroBlaze l ng ng song song, c chia thnh 3 giai on: c lnh (Fetch), Gii m lnh (Decode), v thc hin lnh (Execute). Thng th mi giai on cn 1 chu k nhp nhp ng h thc hin. Nh vy phi mt 3 chu k nhp ng h mt lnh thc hin xong. Mi giai on tch cc trong mt chu k nhp ng h nn 3 lnh c th thc hin ng thi. Nh c b m lnh (Instruction Buffer) nn gim tr ch i gia cc lnh v cc lnh c c t b nh c lin tc theo tin trnh thc hin cc lnh trc ( l c tnh ca ng ng lnh, tng t nh dy truyn sn xut).

Hnh 3.3: S khi ca b x l li-mm MicroBlaze bn trong FPGA

MicroBlaze c 3 giao tip truy nhp b nh: bus b nh cc b LMB (Local Memory Bus); Bus ngoi vi trn chip ca IBM, OPB (IBMs on-chip Peripheral Bus); v XCL (Xilinx CacheLink). LMB m bo mt chu k nhp ng h truy nhp n block RAM hai cng (BRAM) trong FPGA. OPB m bo kt ni vi b nh v ngoi vi c bn trong chip v bn ngoi chip (hnh 3.4). XCL dng cho kt ni vi cc b iu khin b nh (MCH OPB DDR).

Hnh 3.4: Kt ni b x l li-mm MicroBlaze bn trong FPGA

Cc khi ca b nh chnh nm trong khong a ch 0x22000000 - 0x2200FFFF.

Bng 2.5: Bn sp xp a ch ca h thng MicroBlaze

Khi OPB Ethernet c cu hnh cho 10 Mb/s hoc 100 Mb/s ph thuc vo mng ghp ni. Khi iu khin b nh OPB EMC kt ni vi Intel StrataFlash PROM, s dng lu tr Bitstream ca cu hnh phn cng v ng dng khi ng np (Boootloader). Khi OPB UART Lite c cu hnh s dng cc ngt. N c thit lp cng kt ni DTE tun t tc 115200 b/s. N yu cu s dng cp Null modem. MicroBlaze h tr n 8 cng lin kt n cng nhanh FSL, mi cng FSL vi mt master v mt slave. FSL n gin cho kt ni im-im. Cc lnh ca MicroBlaze u rng 32 bit v c xc nh nh l loi A hoc loi B. Cc lnh loi A c 2 thanh ghi ton hng ngun v 1 thanh ghi ton hng ch. Cc

lnh loi B c thanh ghi ton hng ngun v mt ton hng tc thi 16-bit. C cc nhm lnh: s hc, logic, r nhnh, Load/store, v c bit. MicroBlaze l loi x l Load/Store, ngha l n ch c th load/store d liu t/n b nh. N khng th thc hin bt k thao tc no trn d liu trc tip trong b nh, m phi ly d liu vo trong MicroBlaze thc hin. Cc giao tip d liu cng rng 32 bit v s dng Big-Endian, dng o bit biu din d liu, ngha l Bit 0 l MSB v Bit 31 l LSB. MicroBlaze s dng t 32-bit, na t 16-bit, v cho php truy nhp theo byte vo b nh. Ngn xp trong MicroBlaze bt u t vng nh a ch cao v ln dn xung vng nh a ch thp khi cc khon d liu c y vo ngn xp nh lnh Call. Cc khon d liu vng nh a ch thp c pop khi ngn xp trc tin. MicroBlaze cng c cc thanh ghi c bit nh: b m chng trnh (PC) c th c c/ nhng khng th ghi c, thanh ghi trng thi my MSR (Machine Status Register) ch trng thi ca b x l: carry, li chia cho 0, li ca FSL, cho php/cm ngt. Thanh ghi a ch ngoi l EAR (Exception Address Register) lu a ch y ca load/store gy ra mt ngoi l. Thanh ghi trng thi ngoi l ESR (Exception Status Register) ch ra loi ngoi l no xy ra. Thanh ghi trng thi du phy ng FSR (Floating-Point Status Register) ch ra thao tc b li, li chia cho 0, trn, trn di v li ton hng khng c bnh thng ha ca lnh du phy ng. MicroBlaze cng h tr xa, ngt, ngoi l ca ngi dng, break v cc ngoi l ca phn cng. i vi cc ngt, ch mt ngun ngt t bn ngoi (ni vi cng vo ngt). Nu cn phi c nhiu ngt, th phi s dng b iu khin ngt. C mt b iu khin ngt sn c cho s dng vi cc cng c phn mm Xilinx EDK. B x l s phn ng vi cc ngt nu bit cho php ngt IE (interrupt enable) trong MSR c thit lp bng 1. Mt ngt lnh ang thc hin s xy ra, lnh trong giai on gii m c thay th bng mt r nhnh n interrupt vector (a ch 0x10). a ch tr v sau khi thc hin xong ngt (a ch ca lnh trong giai on gii m b ngt) c t ng np vo thanh ghi chung R14. Ngoi ra, b x l cng xa bit IE trong MSR cm cc ngt tip theo. Bit IE c t ng thit lp bng 1 tr li khi thc hin lnh RTID. Chng trnh iu khin MicroBlaze phi c vit ngn ng C/C++. Bi v s dng C/C++ l phng php a thch ca hu ht ngi dng v n l khun dng m cc cng c phn mm pht trin Xilinx EDK mong mun. Cc cng c Xilinx EDK xy dng trnh bin dch C/C++ to m my cn thit cho MicroBlaze.