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Intel® Desktop Board D945GCCR: Technical Product Specification
Intel® Desktop Board D945GCCR: Technical Product Specification
Revision History
Revision -001 Revision History First release of the Specification. Intel Desktop Board D945GCCR Technical Product Date January 2007
This product specification applies to only the standard Intel Desktop Board D945GCCR with BIOS identifier CR94510J.86A. Changes to this specification will be published in the Intel Desktop Board D945GCCR Specification Update before being incorporated into a revision of this document.
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Preface
This Technical Product Specification (TPS) specifies the board layout, components, connectors, power and environmental requirements, and the BIOS for the Intel Desktop Board D945GCCR. It describes the standard product and available manufacturing options.
Intended Audience
The TPS is intended to provide detailed, technical information about the Desktop Board D945GCCR and its components to the vendors, system integrators, and other engineers and technicians who need this level of information. It is specifically not intended for general audiences.
1 2 3 4 5
A description of the hardware used on the Desktop Board D945GCCR A map of the resources of the Desktop Board The features supported by the BIOS Setup program A description of the BIOS error messages, beep codes, and POST codes Regulatory compliance and battery disposal information
Typographical Conventions
This section contains information about the conventions used in this specification. Not all of these symbols and abbreviations appear in all specifications of this type.
INTEGRATORS NOTES
Integrators notes are used to call attention to information that may be useful to system integrators.
CAUTION
Cautions are included to help you avoid damaging hardware or losing data.
iii
WARNING
Warnings indicate conditions which, if not observed, can cause personal injury.
iv
Contents
1 Product Description
1.1 Overview........................................................................................ 10 1.1.1 Feature Summary ................................................................ 10 1.1.2 Board Layout ....................................................................... 12 1.1.3 Block Diagram ..................................................................... 14 1.2 Online Support................................................................................ 15 1.3 Processor ....................................................................................... 15 1.4 System Memory .............................................................................. 16 1.4.1 Memory Configurations ......................................................... 18 1.5 Intel 945GC Chipset....................................................................... 21 1.5.1 Intel 945GC Graphics Subsystem............................................ 21 1.5.2 USB ................................................................................... 23 1.5.3 IDE Support ........................................................................ 24 1.5.4 Real-Time Clock, CMOS SRAM, and Battery .............................. 25 1.6 PCI Express* Connectors .................................................................. 25 1.7 Legacy I/O Controller ....................................................................... 26 1.7.1 Serial Port ........................................................................... 26 1.7.2 Parallel Port......................................................................... 26 1.7.3 Diskette Drive Controller ....................................................... 26 1.7.4 Keyboard and Mouse Interface ............................................... 26 1.8 Audio Subsystem............................................................................. 27 1.8.1 Audio Subsystem Software .................................................... 27 1.8.2 Audio Connectors ................................................................. 27 1.8.3 6-Channel (5.1) Audio Subsystem........................................... 28 1.9 LAN Subsystem ............................................................................... 29 1.9.1 LAN Subsystem Software....................................................... 29 1.9.2 Intel 82562G Physical Layer Interface Device ......................... 29 1.10 Hardware Management Subsystem .................................................... 31 1.10.1 Hardware Monitoring and Fan Control ASIC .............................. 31 1.10.2 Chassis Intrusion and Detection.............................................. 31 1.10.3 Fan Monitoring ..................................................................... 31 1.10.4 Thermal Monitoring .............................................................. 32 1.11 Power Management ......................................................................... 33 1.11.1 ACPI .................................................................................. 33 1.11.2 Hardware Support ................................................................ 35
2 Technical Reference
2.1 Memory Resources .......................................................................... 2.1.1 Addressable Memory............................................................. 2.1.2 Memory Map........................................................................ 2.2 DMA Channels................................................................................. 2.3 Fixed I/O Map ................................................................................. 2.4 PCI Configuration Space Map ............................................................ 41 41 43 43 44 45
2.5 Interrupts ...................................................................................... 46 2.6 PCI Conventional Interrupt Routing Map ............................................. 47 2.7 Connectors and Headers................................................................... 48 2.7.1 Back Panel Connectors .......................................................... 49 2.7.2 Component-side Connectors and Headers ................................ 50 2.8 Jumper Block .................................................................................. 58 2.9 Mechanical Considerations ................................................................ 60 2.9.1 Form Factor......................................................................... 60 2.9.2 I/O Shield ........................................................................... 61 2.10 Electrical Considerations ................................................................... 62 2.10.1 DC Loading.......................................................................... 62 2.10.2 Add-in Board Considerations .................................................. 62 2.10.3 Fan Header Current Capability................................................ 63 2.10.4 Power Supply Considerations ................................................. 63 2.11 Thermal Considerations .................................................................... 64 2.12 Reliability ....................................................................................... 66 2.13 Environmental ................................................................................ 67
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Contents
Figures
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. Board Components .......................................................................... Block Diagram ................................................................................ Memory Channel and DIMM Configuration ........................................... Dual Channel (Interleaved) Mode Configuration with Two DIMMs............ Single Channel (Asymmetric) Mode Configuration with One DIMM .......... Single Channel (Asymmetric) Mode Configuration with Two DIMMs ......... Front/Back Panel Audio Connector Options .......................................... LAN Connector LED Locations ............................................................ Thermal Sensors and Fan Headers ..................................................... Location of the Standby Power Indicator LED ....................................... Detailed System Memory Address Map ............................................... Back Panel Connectors ..................................................................... Component-side Connectors and Headers ........................................... Connection Diagram for Front Panel Header ........................................ Connection Diagram for Front Panel USB Headers ................................ Location of the Jumper Block............................................................. Board Dimensions ........................................................................... I/O Shield Dimensions...................................................................... Localized High Temperature Zones..................................................... 12 14 18 19 19 20 28 30 32 39 42 49 50 55 57 58 60 61 65
Tables
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Feature Summary............................................................................ 10 Board Components Shown in Figure 1 ................................................ 13 Supported Memory Configurations ..................................................... 16 Memory Operating Frequencies ......................................................... 17 LAN Connector LED States ................................................................ 30 Effects of Pressing the Power Switch .................................................. 33 Power States and Targeted System Power........................................... 34 Wake-up Devices and Events ............................................................ 35 System Memory Map ....................................................................... 43 DMA Channels................................................................................. 43 I/O Map ......................................................................................... 44 PCI Configuration Space Map ............................................................ 45 Interrupts ...................................................................................... 46 PCI Interrupt Routing Map ................................................................ 47
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15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44.
Component-side Connectors and Headers Shown in Figure 13................ Front Panel Audio Header ................................................................. Chassis Intrusion Header .................................................................. Serial ATA Connectors ...................................................................... Processor Fan Header ...................................................................... Front and Rear Chassis Fan Headers .................................................. Main Power Connector...................................................................... Processor Core Power Connector........................................................ Auxiliary Front Panel Power/Sleep LED Header..................................... Front Panel Header .......................................................................... States for a One-Color Power LED ...................................................... States for a Two-Color Power LED...................................................... BIOS Setup Configuration Jumper Settings.......................................... DC Loading Characteristics ............................................................... Fan Header Current Capability........................................................... Thermal Considerations for Components ............................................. Environmental Specifications............................................................. BIOS Setup Program Menu Bar.......................................................... BIOS Setup Program Function Keys.................................................... Boot Device Menu Options ................................................................ Supervisor and User Password Functions............................................. Beep Codes .................................................................................... BIOS Error Messages ....................................................................... Port 80h POST Code Ranges.............................................................. Port 80h POST Codes ....................................................................... Typical Port 80h POST Sequence........................................................ Safety Regulations........................................................................... Lead-Free Board Markings ................................................................ EMC Regulations ............................................................................. Product Certification Markings ...........................................................
51 52 52 52 52 52 53 53 54 55 56 56 59 62 63 66 67 70 70 74 76 77 77 78 79 82 83 88 89 90
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Product Description
1.1 Overview........................................................................................ 10 1.2 Online Support................................................................................ 15 1.3 Processor ....................................................................................... 15 1.4 System Memory .............................................................................. 16 1.5 Intel 945GC Chipset....................................................................... 21 1.6 PCI Express* Connectors .................................................................. 25 1.7 Legacy I/O Controller ....................................................................... 26 1.8 Audio Subsystem............................................................................. 27 1.9 LAN Subsystem ............................................................................... 29 1.10 Hardware Management Subsystem .................................................... 31 1.11 Power Management ......................................................................... 33
1.1
1.1.1
Overview
Feature Summary
Table 1 summarizes the major features of the board. Table 1. Feature Summary
Form Factor Processor microATX (9.60 inches by 9.60 inches [243.84 millimeters by 243.84 millimeters]) Support for the following: Intel Core2 Duo processor in an LGA775 socket with a 800 MHz system bus Intel Pentium D processor in an LGA775 socket with an 800 or 533 MHz system bus Intel Pentium 4 processor in an LGA775 socket with an 800 or 533 MHz system bus Intel Celeron D processor in an LGA775 socket with a 533 MHz system bus Memory Two 240-pin DDR2 SDRAM Dual Inline Memory Module (DIMM) sockets Support for DDR2 533 or DDR2 400 MHz DIMMs Support for up to 4 GB of system memory Chipset Intel 945GC Chipset, consisting of: Intel 82945GC Graphics Memory Controller Hub (GMCH) Intel 82801GB I/O Controller Hub (ICH7) Video Audio Legacy I/O Control USB Peripheral Interfaces Intel GMA950 onboard graphics subsystem 6-channel (5.1) audio subsystem with three analog audio outputs using the Realtek* ALC883 audio codec SMSC* 5127 legacy I/O controller for diskette drive, serial, parallel, and PS/2* ports Support for USB 2.0 devices Eight USB ports One serial port One parallel port Four Serial ATA interfaces One Parallel ATA IDE interface with UDMA 33, ATA-66/100 support One diskette drive interface PS/2 keyboard and mouse ports LAN Support BIOS 10/100 Mbits/sec LAN subsystem using the Intel 82562G Platform LAN Connect (PLC) device Intel BIOS (resident in the SPI Flash device) Support for Advanced Configuration and Power Interface (ACPI), Plug and Play, and SMBIOS Expansion Capabilities Two PCI* Conventional bus connectors One PCI Express* x1 bus add-in card connector One PCI Express x16 bus add-in card connector
continued
10
Product Description
Refer to
Section 1.2, page 15
11
1.1.2
Board Layout
12
Product Description
Front panel audio header PCI Conventional bus add-in card connector #2 PCI Conventional bus add-in card connector #1 PCI Express x1 bus add-in card connector PCI Express x16 bus add-in card connector Back panel connectors Processor core power connector Processor fan header Rear chassis fan header LGA775 processor socket Intel 82945GC GMCH DIMM socket DIMM socket Chassis intrusion header Main Power connector Diskette drive connector Parallel ATE IDE connector Intel 82801GB I/O Controller Hub (ICH7) Front chassis fan header Serial ATA connectors [4] Front panel header Speaker Front panel USB headers [2] BIOS Setup configuration jumper block Battery Auxiliary front panel power LED header
13
1.1.3
Block Diagram
14
Product Description
1.2
Online Support
To find information about Intel Desktop Board D945GCCR under Desktop Board Products or Desktop Board Support Available configurations for the Desktop Board D945GCCR Processor data sheets ICH7 addressing Custom splash screens Audio software and utilities LAN software and drivers Supported video modes Visit this World Wide Web site: http://www.intel.com/design/motherbd http://support.intel.com/support/motherboards/desktop http://developer.intel.com/design/motherbd/cr/cr_available.htm http://www.intel.com/design/litcentr http://developer.intel.com/products/chipsets http://intel.com/design/motherbd/gen_indx.htm http://www.intel.com/design/motherbd http://www.intel.com/design/motherbd http://www.intel.com/design/motherbd/cr/cr_documentation.htm
1.3
Processor
Intel Core 2 Duo processor in an LGA775 socket with a 800 MHz system bus Intel Pentium D processor in an LGA775 processor socket with an 800 or 533 MHz system bus Intel Pentium 4 processor in an LGA775 processor socket with an 800 or 533 MHz system bus Intel Celeron D processor in an LGA775 processor socket with a 533 MHz system bus
See the Intel web site listed below for the most up-to-date list of supported processors.
For information about
Supported processors
Refer to:
http://www.intel.com/design/motherbd/cr/cr_proc.htm
CAUTION
Use only the processors listed on web site above. Use of unsupported processors can damage the board, the processor, and the power supply.
INTEGRATORS NOTE
Use only ATX12V-compliant power supplies.
For information about Power supply connectors Refer to Section 2.7.2.1, page 53
15
1.4
System Memory
1.8 V (only) DDR2 SDRAM DIMMs with gold-plated contacts Unbuffered, single-sided or double-sided DIMMs with the following restriction: Double-sided DIMMS with x16 organization are not supported. 2 GB maximum total system memory. Refer to Section 2.1.1 on page 41 for information on the total amount of addressable memory. Minimum total system memory: 128 MB Non-ECC DIMMs Serial Presence Detect DDR2 533 or DDR2 400 MHz SDRAM DIMMs
The board has two DIMM sockets and supports the following memory features:
NOTES
Remove the PCI Express x16 video card before installing or upgrading memory to avoid interference with the memory retention mechanism. To be fully compliant with all applicable DDR SDRAM memory specifications, the board should be populated with DIMMs that support the Serial Presence Detect (SPD) data structure. This allows the BIOS to read the SPD data and program the chipset to accurately configure memory settings for optimum performance. If nonSPD memory is installed, the BIOS will attempt to correctly configure the memory settings, but performance and reliability may be impacted or the DIMMs may not function under the determined frequency.
Table 3 lists the supported DIMM configurations. Table 3. Supported Memory Configurations
DIMM Capacity 128 MB 256 MB 256 MB 512 MB 512 MB 512 MB 1024 MB 1024 MB Configuration SS SS SS DS SS SS DS SS SDRAM Density 256 Mbit 256 Mbit 512 Mbit 256 Mbit 512 Mbit 1 Gbit 512 Mbit 1 Gbit SDRAM Organization Front-side/Back-side 16 M x 16/empty 32 M x 8/empty 32 M x 16/empty 32 M x 8/32 M x 8 64 M x 8/empty 64 M x 16/empty 64 M x 8/64 M x 8 128 M x 8/empty Number of SDRAM Devices 4 8 4 16 8 4 16 8
Note: In the second column, DS refers to double-sided memory modules (containing two rows of SDRAM) and SS refers to single-sided memory modules (containing one row of SDRAM).
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Product Description
NOTE
Regardless of the DIMM type used, the memory frequency will either be equal to or less than the processor system bus frequency. For example, if DDR2 400 memory is used with a 533 MHz system bus frequency processor, the memory will operate at 400 MHz. Table 4 lists the resulting operating memory frequencies based on the combination of DIMMs and processors. Table 4. Memory Operating Frequencies
DIMM Type DDR2 400 DDR2 400 DDR2 533 DDR2 533 Processor system bus frequency 533 MHz 800 MHz 533 MHz 800 MHz Resulting memory frequency 400 MHz 400 MHz 533 MHz 533 MHz
17
1.4.1
Memory Configurations
Dual channel (Interleaved) mode. This mode offers the highest throughput for real world applications. Dual channel mode is enabled when the installed memory capacities of both DIMM channels are equal. Technology and device width can vary from one channel to the other but the installed memory capacity for each channel must be equal. If different speed DIMMs are used between channels, the slowest memory timing will be used. Single channel (Asymmetric) mode. This mode is equivalent to single channel bandwidth operation for real world applications. This mode is used when only a single DIMM is installed or the memory capacities are unequal. Technology and device width can vary from one channel to the other. If different speed DIMMs are used between channels, the slowest memory timing will be used.
18
Product Description
1.4.1.1
Figure 4 shows a dual channel configuration using two DIMMs. In this example, the DIMM sockets are populated with identical DIMMs.
1.4.1.2 NOTE
Dual channel (Interleaved) mode configurations provide the highest memory throughput. Figure 5 shows a single channel configuration using one DIMM. In this example, only the Channel A is populated. Channel B is not populated.
19
Figure 6 shows a single channel configuration using two DIMMs. In this example, the capacity of the DIMM in Channel A does not equal the capacity of the DIMM in Channel B.
20
Product Description
1.5
The GMCH component provides interfaces to the CPU, memory, PCI Express, and the DMI interconnect. The component also provides integrated graphics capabilities supporting 3D, 2D and display capabilities. The ICH7 is a centralized controller for the boards I/O paths.
For information about The Intel 945GC chipset Resources used by the chipset Refer to http://developer.intel.com/ Chapter 2
1.5.1
The Intel 945GC chipset contains two separate, mutually exclusive graphics options. Either the GMA950 graphics controller (contained within the 82945GC GMCH) is used, or a PCI Express x16 add-in card can be used. When a PCI Express x16 add-in card is installed, the GMA950 graphics controller is disabled.
1.5.1.1
The Intel GMA950 graphics controller features the following: 400 MHz core frequency High performance 3-D setup and render engine High quality texture engine DX9* Compliant Hardware Pixel Shader 2.0 Alpha and luminance maps Texture color-keying/chroma-keying Cubic environment reflection mapping Enhanced texture blending functions 3D Graphics Rendering enhancements 1.3 Dual Texture GigaPixel/Sec Fill Rate 16 and 32 bit color Maximum 3D supported resolution of 1600 x 1200 x 32 at 85 Hz Vertex cache Anti-aliased lines OpenGL* version 1.4 support with vertex buffer and EXT_Shadow extensions 2D Graphics enhancements 8, 16,and 32 bit color Optimized 256-bit BLT engine Color space conversion Anti-aliased lines
21
Video Hardware motion compensation for MPEG2 Software DVD at 30 fps full screen Display Integrated 24-bit 400 MHz RAMDAC Up to 2048 x 1536 at 75 Hz refresh (QXGA) DDC2B compliant interface with Advanced Digital Display 2 or 2+ (ADD2/ADD2+) cards, support for TV-out/TV-in and DVI digital display connections Supports flat panels up to 2048 x 1536 at 60Hz or digital CRT/HDTV at 1920 x 1080 at 85 Hz (with ADD2/ADD2+) Two multiplexed DVO port interfaces with 200 MHz pixel clocks using an ADD2/ADD2+ card Dynamic Video Memory Technology (DVMT) support up to 224 MB Intel Zoom Utility
Refer to Section 1.2, page 15
1.5.1.2
DVMT enables enhanced graphics and memory performance through Direct AGP, and highly efficient memory utilization. DVMT ensures the most efficient use of available system memory for maximum 2-D/3-D graphics performance. Up to 224 MB of system memory can be allocated to DVMT on systems that have 512 MB or more of total system memory installed. Up to 128 MB can be allocated to DVMT on systems that have 256 MB but less than 512 MB of total installed system memory. Up to 64 MB can be allocated to DVMT when less than 256 MB of system memory is installed. DVMT returns system memory back to the operating system when the additional system memory is no longer required by the graphics subsystem. DVMT will always use a minimal fixed portion of system physical memory (as set in the BIOS Setup program) for compatibility with legacy applications. An example of this would be when using VGA graphics under DOS. Once loaded, the operating system and graphics drivers allocate additional system memory to the graphics buffer as needed for performing graphics functions.
NOTE
The use of DVMT requires operating system driver support.
22
Product Description
1.5.1.3
The GMCH routes two multiplexed DVO ports that are each capable of driving up to a 200 MHz pixel clock to the PCI Express x16 connector. The DVO ports can be paired for a dual channel configuration to support up to a 400 MHz pixel clock. When an ADD2/ADD2+ card is detected, the Intel GMA950 graphics controller is enabled and the PCI Express x16 connector is configured for DVO mode. DVO mode enables the DVO ports to be accessed by the ADD2/ADD2+ card. An ADD2/ADD2+ card can either be configured to support simultaneous display with the primary VGA display or can be configured to support dual independent display as an extended desktop configuration with different color depths and resolutions. ADD2/ADD2+ cards can be designed to support the following configurations: TV-Out (composite video) Transition Minimized Differential Signaling (TMDS) for DVI 1.0 Low Voltage Differential Signaling (LVDS) Single device operating in dual channel mode VGA output HDTV output
1.5.1.4
Configuration Modes
A list of supported modes for the Intel GMA950 graphics controller is available as a downloadable document.
For information about Supported video modes for the board Refer to Section 1.2, page 15
1.5.2
USB
The board supports up to eight USB 2.0 ports, supports UHCI and EHCI, and uses UHCI- and EHCI-compatible drivers. The ICH7 provides the USB controller for all ports. The port arrangement is as follows: Four ports are implemented with dual stacked back panel connectors Four ports are routed to two separate front panel USB headers
NOTE
Computer systems that have an unshielded cable attached to a USB port may not meet FCC Class B requirements, even if no device is attached to the cable. Use shielded cable that meets the requirements for full-speed devices.
For information about The location of the USB connectors on the back panel The location of the front panel USB headers Refer to Figure 12, page 49 Figure 13, page 50
23
1.5.3
IDE Support
One parallel ATA IDE connector that supports two devices Four serial ATA IDE connectors that support one device per connector
1.5.3.1
The ICH7s Parallel ATA IDE controller has one bus-mastering Parallel ATA IDE interface. The Parallel ATA IDE interface supports the following modes: Programmed I/O (PIO): processor controls data transfer. 8237-style DMA: DMA offloads the processor, supporting transfer rates of up to 16 MB/sec. Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates of up to 33 MB/sec. ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer rates of up to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is device driver compatible. ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH7s ATA-100 logic can achieve read transfer rates up to 100 MB/sec and write transfer rates up to 88 MB/sec.
NOTE
ATA-66 and ATA-100 are faster timings and require a specialized cable to reduce reflections, noise, and inductive coupling. The Parallel ATA IDE interface also supports ATAPI devices (such as CD-ROM drives) and ATA devices using the transfer modes. The BIOS supports Logical Block Addressing (LBA) and Extended Cylinder Head Sector (ECHS) translation modes. The drive reports the transfer rate and translation mode to the BIOS.
For information about The location of the Parallel ATA IDE connector Refer to Figure 13, page 50
1.5.3.2
The ICH7s Serial ATA controller offers four independent Serial ATA ports with a theoretical maximum transfer rate of 3 Gbits/sec per port. One device can be installed on each port for a maximum of four Serial ATA devices. A point-to-point interface is used for host to device connections, unlike Parallel ATA IDE which supports a master/slave configuration and two devices per channel. For compatibility, the underlying Serial ATA functionality is transparent to the operating system. The Serial ATA controller can operate in both legacy and native modes. In legacy mode, standard IDE I/O and IRQ resources are assigned (IRQ 14 and 15). In Native mode, standard PCI Conventional bus resource steering is used. Native mode is the preferred mode for configurations using the Windows* XP and Windows 2000 operating systems.
24
Product Description
NOTE
Many Serial ATA drives use new low-voltage power connectors and require adaptors or power supplies equipped with low-voltage power connectors. For more information, see: http://www.serialata.org/
For information about The location of the Serial ATA IDE connectors Refer to Figure 13, page 50
1.5.4
A coin-cell battery (CR2032) powers the real-time clock and CMOS memory. When the computer is not plugged into a wall socket, the battery has an estimated life of three years. When the computer is plugged in, the standby current from the power supply extends the life of the battery. The clock is accurate to 13 minutes/year at 25 C with 3.3 VSB applied.
NOTE
If the battery and AC power fail, custom defaults, if previously saved, will be loaded into CMOS RAM at power-on.
1.6
The PCI Express interface supports the PCI Conventional bus configuration mechanism so that the underlying PCI Express architecture is compatible with PCI Conventional compliant operating systems. Additional features of the PCI Express interface include the following: Support for the PCI Express enhanced configuration mechanism Automatic discovery, link training, and initialization Support for Active State Power Management (ASPM) SMBus 2.0 support Wake# signal supporting wake events from ACPI S1, S3, S4, or S5 Software compatible with the PCI Power Management Event (PME) mechanism defined in the PCI Power Management Specification Rev. 1.1
25
1.7
The BIOS Setup program provides configuration options for the legacy I/O controller.
1.7.1
Serial Port
The Serial port A connector is located on the back panel. The serial port supports data transfers at speeds up to 115.2 kbits/sec with BIOS support.
For information about The location of the serial port A connector Refer to Figure 12, page 49
1.7.2
Parallel Port
The 25-pin D-Sub parallel port connector is located on the back panel. Use the BIOS Setup program to set the parallel port mode.
For information about The location of the parallel port connector Refer to Figure 12, page 49
1.7.3
The legacy I/O controller supports one diskette drive. Use the BIOS Setup program to configure the diskette drive interface.
For information about The location of the diskette drive connector Refer to Figure 13, page 50
1.7.4
NOTE
PS/2 keyboard and mouse connectors are located on the back panel.
The keyboard is supported in the bottom PS/2 connector and the mouse is supported in the top PS/2 connector. Power to the computer should be turned off before a keyboard or mouse is connected or disconnected.
For information about The location of the keyboard and mouse connectors Refer to Figure 12, page 49
26
Product Description
1.8
Audio Subsystem
Advanced jack sense for the back panel audio jacks that enables the audio codec to recognize the device that is connected to an audio port. The back panel audio jacks are capable of retasking according to users definition, or can be automatically switched depending on the recognized device type. Stereo input and output for all back panel jacks Line out and Mic in functions for front panel audio jacks A signal-to-noise (S/N) ratio of 95 dB
The board supports the Intel High Definition audio subsystem based on the Realtek ALC883 audio codec. The audio subsystem supports the following features:
1.8.1
Audio software and drivers are available from Intels World Wide Web site.
For information about
1.8.2
Audio Connectors
The board contains audio connectors/headers on both the back panel and the component side of the board. The front panel audio header provides mic in and line out signals for the front panel.
For information about The location of the front panel audio header The signal names of the front panel audio header The back panel audio connectors Refer to Figure 13, page 50 Table 16, page 52 Section 2.7.1, page 49
27
1.8.3
The back panel audio connectors are configurable through the audio device drivers. The available configurable audio ports are shown in Figure 7.
28
Product Description
1.9
LAN Subsystem
Intel 82801GB ICH7 Intel 82562G Platform LAN Connect (PLC) device for 10/100 Mbits/sec Ethernet LAN connectivity RJ-45 LAN connector with integrated status LEDs CSMA/CD protocol engine LAN connect interface that supports the 82562G PCI Conventional bus power management Supports ACPI technology Supports LAN wake capabilities
1.9.1
LAN software and drivers are available from Intels World Wide Web site.
For information about Obtaining LAN software and drivers
1.9.2
29
1.9.2.1
Two LEDs are built into the RJ-45 LAN connector (shown in Figure 8).
Figure 8. LAN Connector LED Locations Table 5 describes the LED states when the board is powered up and the 10/100 Mbits/sec LAN subsystem is operating. Table 5. LAN Connector LED States
LED A LED Color Green LED State Off On Blinking B Yellow Off On Condition LAN link is not established. LAN link is established. LAN activity is occurring. 10 Mbits/sec data rate is selected. 100 Mbits/sec data rate is selected.
30
Product Description
1.10.1
The features of the hardware monitoring and fan control ASIC include: Internal ambient temperature sensor Two remote thermal diode sensors for direct monitoring of processor temperature and ambient temperature sensing Power supply monitoring of five voltages (+5 V, +12 V, +3.3 VSB, +1.5 V, and +VCCP) to detect levels above or below acceptable values Thermally monitored closed-loop fan control, for all three fans, that can adjust the fan speed or switch the fans on or off as needed SMBus interface
Refer to Figure 9, page 32
For information about The location of the fan headers and sensors for thermal monitoring
1.10.2
The board supports a chassis security feature that detects if the chassis cover is removed. The security feature uses a mechanical switch on the chassis that attaches to the chassis intrusion header. When the chassis cover is removed, the mechanical switch is in the closed position.
1.10.3
Fan Monitoring
Fan monitoring can be implemented using Intel Desktop Utilities or third-party software. The level of monitoring and control is dependent on the I/O controller used with the board.
For information about The functions of the fan headers Refer to Section 1.11.2.2, page 36
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1.10.4
Thermal Monitoring
Item A B C D E
Description Processor fan Rear chassis fan Thermal diode, located on processor die Remote ambient temperature sensor Front chassis fan
32
Product Description
1.11.1
ACPI
ACPI gives the operating system direct control over the power management and Plug and Play functions of a computer. The use of ACPI with this board requires an operating system that provides full ACPI support. ACPI features include: Plug and Play (including bus and device enumeration) Power management control of individual devices, add-in boards (some add-in boards may require an ACPI-aware driver), video displays, and hard disk drives Methods for achieving less than 15-watt system operation in the power-on/standby sleeping state A Soft-off feature that enables the operating system to power-off the computer Support for multiple wake-up events (see Table 8 on page 35) Support for a front panel power and sleep mode switch
Table 6 lists the system states based on how long the power switch is pressed, depending on how ACPI is configured with an ACPI-aware operating system. Table 6. Effects of Pressing the Power Switch
If the system is in this state Off (ACPI G2/G5 Soft off) On (ACPI G0 working state) On (ACPI G0 working state) Sleep (ACPI G1 sleeping state) Sleep (ACPI G1 sleeping state) and the power switch is pressed for Less than four seconds Less than four seconds More than four seconds Less than four seconds More than four seconds the system enters this state Power-on (ACPI G0 working state) Soft-off/Standby (ACPI G1 sleeping state) Fail safe power-off (ACPI G2/G5 Soft off) Wake-up (ACPI G0 working state) Power-off (ACPI G2/G5 Soft off)
33
1.11.1.1
Under ACPI, the operating system directs all system and device power state transitions. The operating system puts devices in and out of low-power states based on user preferences and knowledge of how devices are being used by applications. Devices that are not being used can be turned off. The operating system uses information from applications and user settings to put the system as a whole into a low-power state. Table 7 lists the power states supported by the board along with the associated system power targets. See the ACPI specification for a complete description of the various system and power states. Table 7. Power States and Targeted System Power
Processor Global States G0 working state G1 sleeping state G1 sleeping state G1 sleeping state G2/S5 Sleeping States S0 working S1 Processor stopped S3 Suspend to RAM. Context saved to RAM. S4 Suspend to disk. Context saved to disk. S5 Soft off. Context not saved. Cold boot is required. No power to the system. States C0 working C1 stop grant No power Device States D0 working state. D1, D2, D3 device specification specific. D3 no power except for wake-up logic. D3 no power except for wake-up logic. D3 no power except for wake-up logic. D3 no power for wake-up logic, except when provided by battery or external source. Targeted System Power (Note 1) Full power > 30 W 5 W < power < 52.5 W
No power
No power
No power
Total system power is dependent on the system configuration, including add-in boards and peripherals powered by the system chassis power supply. Dependent on the standby power consumption of wake-up devices used in the system.
1.11.1.2
Two-Watt Standby
In 2001, the U.S. government issued an executive order requiring a reduction in power for appliances and personal computers. This board meets that requirement by operating at 1.5 W (or less) in S5 (Standby) mode. Two-Watt operation applies only to the S5 state when the computer is turned off, but still connected to AC power. Two-Watt operation does not apply to the S3 (Suspend to RAM) or S4 (Suspend to disk) states. Newer energy-efficient power supplies using less than 0.5 W (in Standby mode) may also be needed to achieve this goal.
34
Product Description
1.11.1.3
Table 8 lists the devices or specific events that can wake the computer from specific states. Table 8. Wake-up Devices and Events
These devices/events can wake up the computer LAN Modem (back panel Serial Port A) PME# signal Power switch PS/2 devices RTC alarm USB WAKE# signal Note: from this state S1, S3, S4, S5 (Note) S1, S3 S1, S3, S4, S5 (Note) S1, S3, S4, S5 S1, S3 S1, S3, S4, S5 S1, S3 S1, S3, S4, S5
For LAN and PME# signal, S5 is disabled by default in the BIOS Setup program. Setting this option to Power On will enable a wake-up event from LAN in the S5 state.
NOTE
The use of these wake-up events from an ACPI state requires an operating system that provides full ACPI support. In addition, software, drivers, and peripherals must fully support ACPI wake events.
1.11.2
Hardware Support
CAUTION
Ensure that the power supply provides adequate +5 V standby current if LAN wake capabilities and Instantly Available PC technology features are used. Failure to do so can damage the power supply. The total amount of standby current required depends on the wake devices supported and manufacturing options. The board provides several power management hardware features, including: Power connector Fan headers LAN wake capabilities Instantly Available PC technology Resume on Ring Wake from USB Wake from PS/2 keyboard PME# signal wake-up support WAKE# signal wake-up support
LAN wake capabilities and Instantly Available PC technology require power from the +5 V standby line.
35
Resume on Ring enables telephony devices to access the computer when it is in a power-managed state. The method used depends on the type of telephony device (external or internal).
NOTE
The use of Resume on Ring and Wake from USB technologies from an ACPI state requires an operating system that provides full ACPI support.
1.11.2.1
Power Connector
ATX12V-compliant power supplies can turn off the system power through system control. When an ACPI-enabled system receives the correct command, the power supply removes all non-standby voltages. When resuming from an AC power failure, the computer returns to the power state it was in before power was interrupted (on or off). The computers response can be set using the Last Power State feature in the BIOS Setup programs Boot menu.
For information about The location of the main power connector The signal names of the main power connector Refer to Figure 13, page 50 Table 21, page 53
1.11.2.2
Fan Headers
The function/operation of the fan headers is as follows: The fans are on when the board is in the S0 or S1 state. The fans are off when the board is off or in the S3, S4, or S5 state. Each fan header is wired to a fan tachometer input of the hardware monitoring and fan control ASIC. All fan headers support closed-loop fan control that can adjust the fan speed or switch the fan on or off as needed. All fan headers have a +12 V DC connection.
Refer to Figure 13, page 50 Figure 9, page 32 Table 19, page 52 Table 20, page 52
For information about The location of the fan headers The location of the fan headers and sensors for thermal monitoring The signal names of the processor fan header The signal names of the chassis fan headers
36
Product Description
1.11.2.3
CAUTION
For LAN wake capabilities, the +5 V standby line for the power supply must be capable of providing adequate +5 V standby current. Failure to provide adequate standby current when implementing LAN wake capabilities can damage the power supply. LAN wake capabilities enable remote wake-up of the computer through a network. The LAN network adapter monitors network traffic at the Media Independent Interface. Upon detecting a Magic Packet* frame, the LAN subsystem asserts a wake-up signal that powers up the computer. Depending on the LAN implementation, the board supports LAN wake capabilities with ACPI in the following ways: The PCI Express WAKE# signal The PCI Conventional bus PME# signal for PCI 2.3 compliant LAN designs The onboard LAN subsystem
1.11.2.4
CAUTION
For Instantly Available PC technology, the +5 V standby line for the power supply must be capable of providing adequate +5 V standby current. Failure to provide adequate standby current when implementing Instantly Available PC technology can damage the power supply. Instantly Available PC technology enables the board to enter the ACPI S3 (Suspend-toRAM) sleep-state. While in the S3 sleep-state, the computer will appear to be off (the power supply is off, and the front panel LED is amber if dual colored, or off if single colored.) When signaled by a wake-up device or event, the system quickly returns to its last known wake state. Table 8 on page 35 lists the devices and events that can wake the computer from the S3 state. The board supports the PCI Bus Power Management Interface Specification. Add-in boards that also support this specification can participate in power management and can be used to wake the computer. The use of Instantly Available PC technology requires operating system support and PCI 2.3 compliant add-in cards, PCI Express add-in cards, and drivers.
1.11.2.5
Resume on Ring
The operation of Resume on Ring can be summarized as follows: Resumes operation from ACPI S1 or S3 states Detects incoming call similarly for external and internal modems Requires modem interrupt be unmasked for correct operation
37
1.11.2.6 NOTE
Wake from USB requires the use of a USB peripheral that supports Wake from USB.
1.11.2.7
1.11.2.8
When the PME# signal on the PCI Conventional bus is asserted, the computer wakes from an ACPI S1, S3, S4, or S5 state (with Wake on PME enabled in BIOS).
1.11.2.9
When the WAKE# signal on the PCI Express bus is asserted, the computer wakes from an ACPI S1, S3, S4, or S5 state.
38
Product Description
CAUTION
If AC power has been switched off and the standby power indicator is still lit, disconnect the power cord before installing or removing any devices connected to the board. Failure to do so could damage the board and any attached devices.
39
40
Technical Reference
2.1
2.1.1
Memory Resources
Addressable Memory
The board utilizes 2 GB of addressable system memory. Typically the address space that is allocated for PCI Conventional bus add-in cards, PCI Express configuration space, BIOS (SPI Flash), and chipset overhead resides above the top of DRAM (total system memory). On a system that has 2 GB of system memory installed, it is not possible to use all of the installed memory due to system address space being allocated for other system critical functions. These functions include the following: BIOS/ SPI Flash (4 MB) Local APIC (19 MB) Digital Media Interface (40 MB) Front side bus interrupts (17 MB) PCI Express configuration space (256 MB) GMCH base address registers, internal graphics ranges, PCI Express ports (up to 512 MB) Memory-mapped I/O that is dynamically allocated for PCI Conventional and PCI Express add-in cards
41
The amount of installed memory that can be used will vary based on add-in cards and BIOS settings. Figure 11 shows a schematic of the system memory map. All installed system memory can be used when there is no overlap of system addresses.
42
Technical Reference
2.1.2
Memory Map
Table 9 lists the system memory map. Table 9. System Memory Map
Address Range (decimal) 1024 K - 2097152 K 960 K - 1024 K 896 K - 960 K 800 K - 896 K Address Range (hex) 100000 - FFFFFFFF F0000 - FFFFF E0000 - EFFFF C8000 - DFFFF Size 2048 MB 64 KB 64 KB 96 KB Description Extended memory Runtime BIOS Reserved Potential available high DOS memory (open to the PCI Conventional bus). Dependent on video adapter used. Video memory and BIOS Extended BIOS data (movable by memory manager software) Extended conventional memory Conventional memory
2.2
DMA Channels
DMA Channel Number 0 1 2 3 4 5 6 7 Data Width 8 or 16 bits 8 or 16 bits 8 or 16 bits 8 or 16 bits 8 or 16 bits 16 bits 16 bits 16 bits System Resource Open Parallel port Diskette drive Parallel port (for ECP or EPP) DMA controller Open Open Open
43
2.3
Notes: 1. 2. 3. Default, but can be changed to another address range Dword access only Byte access only
NOTE
Some additional I/O addresses are not available due to ICH7 address aliasing. The ICH7 data sheet provides more information on address aliasing.
For information about Obtaining the ICH7 data sheet Refer to Section 1.2, page 15
44
Technical Reference
2.4
Bus
01 Notes: 1. 2.
Present only when a PCI Express x16 graphics card is installed. Bus number is dynamic and can change based on add-in cards used.
45
2.5
Interrupts
The interrupts can be routed through either the Programmable Interrupt Controller (PIC) or the Advanced Programmable Interrupt Controller (APIC) portion of the ICH7 component. The PIC is supported in Windows 98 SE and Windows ME and uses the first 16 interrupts. The APIC is supported in Windows 2000 and Windows XP and supports a total of 24 interrupts. Table 13. Interrupts
IRQ NMI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Note 2) 17 (Note 2) 18 (Note 2) 19 (Note 2) 20 (Note 2) 21 (Note 2) 22 (Note 2) 23 (Note 2) Notes: 1. Default, but can be changed to another IRQ. 2. Available in APIC mode only. System Resource I/O channel check Reserved, interval timer Reserved, keyboard buffer full Reserved, cascade interrupt from slave PIC User available COM1 (Note 1) User available Diskette drive LPT1 (Note 1) Real-time clock User available User available User available Onboard mouse port (if present, else user available) Reserved, math coprocessor Primary Parallel ATA/Serial ATA Legacy Mode (if present, else user available) Secondary Parallel ATA/Serial ATA Legacy Mode (if present, else user available) User available (through PIRQA) User available (through PIRQB) User available (through PIRQC) User available (through PIRQD) User available (through PIRQE) User available (through PIRQF) User available (through PIRQG) User available (through PIRQH)
46
Technical Reference
2.6
This section describes interrupt sharing and how the interrupt signals are connected between the PCI Conventional bus connectors and onboard PCI Conventional devices. The PCI Conventional specification describes how interrupts can be shared between devices attached to the PCI Conventional bus. In most cases, the small amount of latency added by interrupt sharing does not affect the operation or throughput of the devices. In some special cases where maximum performance is needed from a device, a PCI Conventional device should not share an interrupt with other PCI Conventional devices. Use the following information to avoid sharing an interrupt with a PCI Conventional add-in card. PCI Conventional devices are categorized as follows to specify their interrupt grouping: INTA: By default, all add-in cards that require only one interrupt are in this category. For almost all cards that require more than one interrupt, the first interrupt on the card is also classified as INTA. INTB: Generally, the second interrupt on add-in cards that require two or more interrupts is classified as INTB. (This is not an absolute requirement.) INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC and a fourth interrupt is classified as INTD.
The ICH7 has eight Programmable Interrupt Request (PIRQ) input signals. All PCI Conventional interrupt sources either onboard or from a PCI Conventional add-in card connect to one of these PIRQ signals. Some PCI Conventional interrupt sources are electrically tied together on the board and therefore share the same interrupt. Table 14 shows an example of how the PIRQ signals are routed. Table 14. PCI Interrupt Routing Map
ICH7 PIRQ Signal Name PCI Interrupt Source PCI bus connector 1 PCI bus connector 2 ICH7 LAN INTA PIRQA PIRQB PIRQC PIRQD PIRQE INTD INTA PIRQF INTA INTB PIRQG INTB INTC PIRQH INTC INTD
NOTE
In PIC mode, the ICH7 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt. However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ lines to be connected to the same IRQ signal. Refer to Table 13 for the allocation of PIRQ lines to IRQ signals in APIC mode. PCI interrupt assignments to the USB ports, Serial ATA ports, and PCI Express ports are dynamic.
47
2.7
CAUTION
Only the following connectors have overcurrent protection: back panel USB, front panel USB, and PS/2. The other internal connectors/headers are not overcurrent protected and should connect only to devices inside the computers chassis, such as fans and internal peripherals. Do not use these connectors/headers to power devices external to the computers chassis. A fault in the load presented by the external devices could cause damage to the computer, the power cable, and the external devices themselves. This section describes the boards connectors and headers. The connectors and headers can be divided into these groups: Back panel connectors (see page 49) Component-side connectors and headers (see page 50)
48
Technical Reference
2.7.1
Item
A B C D E F G H I J
Description
PS/2 mouse port PS/2 keyboard port Parallel port Serial port VGA port LAN USB ports [4] Audio line in Mic in Audio line out
NOTE
The back panel audio line out connector is designed to power headphones or amplified speakers only. Poor audio quality occurs if passive (non-amplified) speakers are connected to this output.
49
2.7.2
50
Technical Reference
Table 15 lists the component-side connectors and headers identified in Figure 13. Table 15. Component-side Connectors and Headers Shown in Figure 13
Item/callout from Figure 13 A B C D E F G H I J K L M N O P Q R S T U Description
Front panel audio header PCI Conventional bus add-in card connector 2 PCI Conventional bus add-in card connector 1 PCI Express x1 bus add-in card connector PCI Express x16 bus add-in card connector Processor core power connector Processor fan header Rear chassis fan header Chassis intrusion header Main power connector Diskette drive connector Parallel ATA IDE connector Front chassis fan header Serial ATA connector 1 Serial ATA connector 3 Serial ATA connector 2 Front panel header Serial ATA connector 0 Front panel USB header Front panel USB header Auxiliary front panel power LED header
51
INTEGRATORS NOTE
The front panel audio header is colored yellow. Table 17. Chassis Intrusion Header
Pin 1 2 Signal Name Intruder Ground
52
Technical Reference
2.7.2.1
The board has power supply connectors: Main power a 2 x 12 connector. This connector is compatible with 2 x 10 connectors previously used on Intel Desktop boards. The board supports the use of ATX12V power supplies with either 2 x 10 or 2 x 12 main power cables. When using a power supply with a 2 x 10 main power cable, attach that cable on the rightmost pins of the main power connector, leaving pins 11, 12, 23, and 24 unconnected. Processor core power a 2 x 2 connector. This connector provides power directly to the processor voltage regulator and must always be used. Failure to do so will prevent the board from booting.
INTEGRATORS NOTE
When using high wattage PCI Express x16 graphics cards, use a power supply with a 2 x 12 main power cable. The 2 x 12 main power cable can provide up to 144 W of power from the +12 V rail. Table 21. Main Power Connector
Pin 1 2 3 4 5 6 7 8 9 10 11 12 Signal Name +3.3 V +3.3 V Ground +5 V Ground +5 V Ground PWRGD (Power Good) +5 V (Standby) +12 V +12 V (Note) 2 x 12 connector detect (Note) Pin 13 14 15 16 17 18 19 20 21 22 23 24 Signal Name +3.3 V -12 V Ground PS-ON# (power supply remote on/off) Ground Ground Ground No connect +5 V +5 V +5 V (Note) Ground (Note)
Note: When using a 2 x 10 power supply cable, this pin will be unconnected.
53
2.7.2.2
The board has the following add-in card connectors: One PCI Express x16 connector supporting simultaneous transfer speeds up to 4 GBytes/sec of peak bandwidth per direction and up to 8 GBytes/sec concurrent bandwidth. One PCI Express x1 connector. The x1 interface supports simultaneous transfer speeds up to 250 Mbytes/sec of peak bandwidth per direction and up to 500 MBytes/sec concurrent bandwidth. PCI Conventional (rev 2.3 compliant) bus: two PCI Conventional bus add-in card connectors. The SMBus is routed to all PCI Conventional bus connectors. PCI Conventional bus add-in cards with SMBus support can access sensor data and other information residing on the board. All of the PCI Conventional bus connectors are bus master capable. SMBus signals are routed to all PCI Conventional bus connectors. This enables PCI Conventional bus add-in boards with SMBus support to access sensor data on the boards. The specific SMBus signals are as follows: The SMBus clock line is connected to pin A40. The SMBus data line is connected to pin A41.
Note the following considerations for the PCI Conventional bus connectors:
NOTE
The PCI Express x16 connector is configured to support only a PCI Express x1 link when the Intel GMA950 graphics controller is enabled.
2.7.2.3
Pins 1 and 3 of this header duplicate the signals on pins 2 and 4 of the front panel header. Table 23. Auxiliary Front Panel Power/Sleep LED Header
Pin 1 2 3 Signal Name HDR_BLNK_GRN Not connected HDR_BLNK_YEL Out Front panel yellow LED In/Out Out Description Front panel green LED
54
Technical Reference
2.7.2.4
This section describes the functions of the front panel header. Table 24 lists the signal names of the front panel header. Figure 14 is a connection diagram for the front panel header. Table 24. Front Panel Header
In/ Pin Signal Out Description Pin Signal Hard Drive Activity LED [Yellow] 1 3 HD_PWR HDA# Out Out Hard disk LED pull-up to +5 V Hard disk active LED 2 4 HDR_BLNK_ GRN HDR_BLNK_ YEL In/ Out Power LED [Green] Out Out Front panel green LED Front panel yellow LED Description
Reset Switch [Purple] 5 7 Ground FP_RESET# In Power 9 +5 V Power 10 N/C Ground Reset switch 6 8 FPBUT_IN Ground
On/Off Switch [Red] In Power switch Ground Not Connected Not connected
55
2.7.2.4.1
Pins 1 and 3 [Yellow] can be connected to an LED to provide a visual indicator that data is being read from or written to a hard drive. Proper LED function requires one of the following: A Serial ATA hard drive connected to an onboard Serial ATA connector An IDE hard drive connected to an onboard IDE connector Reset Switch Header [Purple]
2.7.2.4.2
Pins 5 and 7 [Purple] can be connected to a momentary single pole, single throw (SPST) type switch that is normally open. When the switch is closed, the board resets and runs the POST. 2.7.2.4.3 Power/Sleep LED Header [Green]
Pins 2 and 4 [Green] can be connected to a one- or two-color LED. Table 25 shows the possible states for a one-color LED. Table 26 shows the possible states for a twocolor LED. Table 25. States for a One-Color Power LED
LED State Off Steady Green Description Power off/sleeping Running
NOTE
The colors listed in Table 25 and Table 26 are suggested colors only. Actual LED colors are product- or customer-specific. 2.7.2.4.4 Power Switch Header [Red]
Pins 6 and 8 [Red] can be connected to a front panel momentary-contact power switch. The switch must pull the SW_ON# pin to ground for at least 50 ms to signal the power supply to switch on or off. (The time requirement is due to internal debounce circuitry on the board.) At least two seconds must pass before the power supply will recognize another on/off signal.
56
Technical Reference
2.7.2.5
INTEGRATORS NOTES
The +5 V DC power on the USB headers is fused. Pins 1, 3, 5, and 7 comprise one USB port. Pins 2, 4, 6, and 8 comprise one USB port. Use only a front panel USB connector that conforms to the USB 2.0 specification for high-speed USB devices.
57
2.8
Jumper Block
CAUTION
Do not move the jumper with the power on. Always turn off the power and unplug the power cord from the computer before changing a jumper setting. Otherwise, the board could be damaged. Figure 16 shows the location of the jumper block. The jumper block determines the BIOS Setup programs mode. Table 27 describes the jumper settings for the three modes: normal, configure, and recovery. When the jumper is set to configure mode and the computer is powered-up, the BIOS compares the processor version and the microcode version in the BIOS and reports if the two match.
58
Technical Reference
3 2 1
Configure 2-3
After the POST runs, Setup runs automatically. The maintenance menu is displayed.
3 2 1
Recovery None
3 2 1
The BIOS attempts to recover the BIOS configuration. A recovery diskette is required.
59
2.9
2.9.1
Mechanical Considerations
Form Factor
The board is designed to fit into an ATX- or microATX-form-factor chassis. Figure 17 illustrates the mechanical form factor of the board. Dimensions are given in inches [millimeters]. The outer dimensions are 9.60 inches by 9.60 inches [243.84 millimeters by 243.84 millimeters]. Location of the I/O connectors and mounting holes are in compliance with the ATX specification.
60
Technical Reference
2.9.2
I/O Shield
The back panel I/O shield for the board must meet specific dimension and material requirements. Systems based on this board need the back panel I/O shield to pass certification testing. Figure 18 shows the I/O shield dimensions. Dimensions are given in millimeters [inches]. The figures also indicate the position of each cutout. Additional design considerations for I/O shields relative to chassis requirements are described in the ATX specification.
NOTE
The I/O shield drawing is for reference only. I/O shields compliant with the ATX chassis specification are available from Intel.
61
2.10.2
The boards are designed to provide 2 A (average) of +5 V current for each add-in board. The total +5 V current draw for both boards is as follows: a fully loaded D945GCCR board (all three expansion slots and the PCI Express x16 slot filled) must not exceed 8 A.
62
Technical Reference
2.10.3
CAUTION
The processor fan must be connected to the processor fan header, not to a chassis fan header. Connecting the processor fan to a chassis fan header may result in onboard component damage that will halt fan operation. Table 29 lists the current capability of the fan headers. Table 29. Fan Header Current Capability
Fan Header Processor fan Front chassis fan Rear chassis fan Maximum Available Current 2.0 A 1.5 A 1.5 A
2.10.4
CAUTION
The +5 V standby line for the power supply must be capable of providing adequate +5 V standby current. Failure to do so can damage the power supply. The total amount of standby current required depends on the wake devices supported and manufacturing options. System integrators should refer to the power usage values listed in Table 28 when selecting a power supply for use with the board. Additional power required will depend on configurations chosen by the integrator. The power supply must comply with the following recommendations found in the ATX form factor specification: The potential relation between 3.3 VDC and +5 VDC power rails The current capability of the +5 VSB line All timing parameters All voltage tolerances
63
CAUTION
Failure to ensure appropriate airflow may result in reduced performance of both the processor and/or voltage regulator or, in some instances, damage to the board. For a list of chassis that have been tested with Intel desktop boards please refer to the following website: http://developer.intel.com/design/motherbd/cooling.htm All responsibility for determining the adequacy of any thermal or system design remains solely with the reader. Intel makes no warranties or representations that merely following the instructions presented in this document will result in a system with adequate thermal performance.
CAUTION
Ensure that the ambient temperature does not exceed the boards maximum operating temperature. Failure to do so could cause components to exceed their maximum case temperature and malfunction. For information about the maximum operating temperature, see the environmental specifications in Section 2.13.
CAUTION
Ensure that proper airflow is maintained in the processor voltage regulator circuit. Failure to do so may result in damage to the voltage regulator circuit. The processor voltage regulator area (item A in Figure 19) can reach a temperature of up to 85 oC in an open chassis.
64
Technical Reference
Item A B C D
Description Processor voltage regulator area Processor Intel 82945GC GMCH Intel 82801GB ICH7
65
Table 30 provides maximum case temperatures for the components that are sensitive to thermal changes. The operating temperature, current load, or operating frequency could affect case temperatures. Maximum case temperatures are important when considering proper airflow to cool the board. Table 30. Thermal Considerations for Components
Component Processor Intel 82945GC GMCH Intel 82801GB ICH7 Maximum Case Temperature For processor case temperature, see processor datasheets and processor specification updates 99 oC (under bias) 110 oC (under bias, without heatsink) 99 oC (under bias, with heatsink)
Refer to
Section 1.2, page 15
2.12 Reliability
The Mean Time Between Failures (MTBF) prediction is calculated using component and subassembly random failure rates. The calculation is based on the Bellcore Reliability Prediction Procedure, TR-NWT-000332, Issue 4, September 1991. The MTBF prediction is used to estimate repair rates and spare parts requirements. The MTBF data is calculated from predicted data at 55 C. The MTBF for the D945GCCR board is 152,352 hours.
66
Technical Reference
2.13 Environmental
Table 31 lists the environmental specifications for the board. Table 31. Environmental Specifications
Parameter Temperature Non-Operating Operating Shock Unpackaged 50 g trapezoidal waveform Velocity change of 170 inches/second Packaged Half sine 2 millisecond Product Weight (pounds) <20 21-40 41-80 81-100 Vibration Unpackaged 5 Hz to 20 Hz: 0.01 g Hz sloping up to 0.02 g Hz 20 Hz to 500 Hz: 0.02 g Hz (flat) Packaged 5 Hz to 40 Hz: 0.015 g Hz (flat) 40 Hz to 500 Hz: 0.015 g Hz sloping down to 0.00015 g Hz Free Fall (inches) 36 30 24 18 Velocity Change (inches/sec) 167 152 136 118 -40 C to +70 C 0 C to +55 C Specification
67
68
3.1
Introduction
The boards use an Intel BIOS that is stored in the Serial Peripheral Interface Flash Memory (SPI Flash) and can be updated using a disk-based program. The SPI Flash contains the BIOS Setup program, POST, the PCI auto-configuration utility, and Plug and Play support. The BIOS displays a message during POST identifying the type of BIOS and a revision code. The initial production BIOSs are identified as CR94510J.86A. When the BIOS Setup configuration jumper is set to configure mode and the computer is powered-up, the BIOS compares the CPU version and the microcode version in the BIOS and reports if the two match. The BIOS Setup program can be used to view and change the BIOS settings for the computer. The BIOS Setup program is accessed by pressing the <F2> key after the Power-On Self-Test (POST) memory test begins and before the operating system boot begins. The menu bar is shown below. Maintenance Main Advanced Security Power Boot Exit
NOTE
The maintenance menu is displayed only when the Desktop Board is in configure mode. Section 2.8 on page 58 shows how to put the Desktop Board in configure mode.
69
Table 32 lists the BIOS Setup program menu features. Table 32. BIOS Setup Program Menu Bar
Maintenance Clears passwords and displays processor information Main Displays processor and memory configuration Advanced Configures advanced features available through the chipset Security Sets passwords and security features Power Configures power management features and power supply controls Boot Selects boot options Exit Saves or discards changes to Setup program options
Table 33 lists the function keys available for menu screens. Table 33. BIOS Setup Program Function Keys
BIOS Setup Program Function Key <> or <> <> or <> <Tab> <Enter> <F9> <F10> <Esc> Description Selects a different menu screen (Moves the cursor left or right) Selects an item (Moves the cursor up or down) Selects a field (Not implemented) Executes command or selects the submenu Load the default configuration values for the current menu Save the current values and exits the BIOS Setup program Exits the menu
3.2
The Serial Peripheral Interface Flash Memory (SPI Flash) includes a 4 Mbit (512 KB) flash memory device.
3.3
3.3.1
Resource Configuration
PCI Autoconfiguration
The BIOS can automatically configure PCI devices. PCI devices may be onboard or add-in cards. Autoconfiguration lets a user insert or remove PCI cards without having to configure the system. When a user turns on the system after adding a PCI card, the BIOS automatically configures interrupts, the I/O space, and other system resources. Any interrupts set to Available in Setup are considered to be available for use by the add-in card.
70
3.3.2
If you select Auto in the BIOS Setup program, the BIOS automatically sets up the PCI IDE connector with independent I/O channel support. The IDE interface supports hard drives up to ATA-66/100 and recognizes any ATAPI compliant devices, including CD-ROM drives, tape drives, and Ultra DMA drives. The interface also supports second-generation SATA drives. The BIOS determines the capabilities of each drive and configures them to optimize capacity and performance. To take advantage of the high capacities typically available today, hard drives are automatically configured for Logical Block Addressing (LBA) and to PIO Mode 3 or 4, depending on the capability of the drive. You can override the auto-configuration options by specifying manual configuration in the BIOS Setup program. To use ATA-66/100 features the following items are required: An ATA-66/100 peripheral device An ATA-66/100 compatible cable ATA-66/100 operating system device drivers
NOTE
Do not connect an ATA device as a slave on the same IDE cable as an ATAPI master device. For example, do not connect an ATA hard drive as a slave to an ATAPI CD-ROM drive.
3.4
SMBIOS is a Desktop Management Interface (DMI) compliant method for managing computers in a managed network. The main component of SMBIOS is the Management Information Format (MIF) database, which contains information about the computing system and its components. Using SMBIOS, a system administrator can obtain the system types, capabilities, operational status, and installation dates for system components. The MIF database defines the data and provides the method for accessing this information. The BIOS enables applications such as third-party management software to use SMBIOS. The BIOS stores and reports the following SMBIOS information: BIOS data, such as the BIOS revision level Fixed-system data, such as peripherals, serial numbers, and asset tags Resource data, such as memory size, cache size, and processor speed Dynamic data, such as event detection and error logging
Non-Plug and Play operating systems, such as Windows NT*, require an additional interface for obtaining the SMBIOS information. The BIOS supports an SMBIOS table interface for such operating systems. Using this support, an SMBIOS service-level application running on a non-Plug and Play operating system can obtain the SMBIOS information.
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3.5
BIOS Updates
Intel Express BIOS Update utility, which enables automated updating while in the Windows environment. Using this utility, the BIOS can be updated from a file on a hard disk, a 1.44 MB diskette, or a CD-ROM, or from the file location on the Web. Intel Flash Memory Update Utility, which requires creation of a boot diskette and manual rebooting of the system. Using this utility, the BIOS can be updated from a file on a 1.44 MB diskette (from a legacy diskette drive or an LS-120 diskette drive) or a CD-ROM.
The BIOS can be updated using either of the following utilities, which are available on the Intel World Wide Web site:
Both utilities verify that the updated BIOS matches the target system to prevent accidentally installing an incompatible BIOS.
NOTE
Review the instructions distributed with the upgrade utility before attempting a BIOS update.
For information about The Intel World Wide Web site Refer to Section 1.2, page 15
3.5.1
Language Support
The BIOS Setup program and help messages are supported in US English. Additional languages are available in the Integrators Toolkit utility. Check the Intel website for details.
3.5.2
During POST, an Intel splash screen is displayed by default. This splash screen can be augmented with a custom splash screen. The Integrators Toolkit that is available from Intel can be used to create a custom splash screen.
NOTE
If you add a custom splash screen, it will share space with the Intel branded logo.
For information about The Intel World Wide Web site Refer to Section 1.2, page 15
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3.6
Legacy USB support enables USB devices to be used even when the operating systems USB drivers are not yet available. Legacy USB support is used to access the BIOS Setup program, and to install an operating system that supports USB. Legacy USB support operates as follows: 1. When you apply power to the computer, legacy support is disabled. 2. POST begins. 3. Legacy USB support is enabled by the BIOS allowing you to use a USB keyboard to enter and configure the BIOS Setup program and the maintenance menu. 4. POST completes. 5. The operating system loads. While the operating system is loading, USB keyboards and mice are recognized and may be used to configure the operating system. 6. After the operating system loads the USB drivers, all legacy and non-legacy USB devices are recognized by the operating system, and Legacy USB support from the BIOS is no longer used. To install an operating system that supports USB, follow the operating systems installation instructions.
3.7
Boot Options
In the BIOS Setup program, the user can choose to boot from a diskette drive, hard drives, CD-ROM, or the network. The default setting is for the diskette drive to be the first boot device, the hard drive second, and the ATAPI CD-ROM third. The fourth device is disabled.
3.7.1
CD-ROM Boot
Booting from CD-ROM is supported in compliance to the El Torito bootable CD-ROM format specification. Under the Boot menu in the BIOS Setup program, ATAPI CDROM is listed as a boot device. Boot devices are defined in priority order. Accordingly, if there is not a bootable CD in the CD-ROM drive, the system will attempt to boot from the next defined drive.
3.7.2
Network Boot
The network can be selected as a boot device. This selection allows booting from the onboard LAN or a network add-in card with a remote boot ROM installed. Pressing the <F12> key during POST automatically forces booting from the LAN. To use this key during POST, the User Access Level in the BIOS Setup program's Security menu must be set to Full.
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3.7.3
For use in embedded applications, the BIOS has been designed so that after passing the POST, the operating system loader is invoked even if the following devices are not present: Video adapter Keyboard Mouse
3.7.4
Pressing the <F10> key during POST causes a boot device menu to be displayed. This menu displays the list of available boot devices (as set in the BIOS setup programs Boot Device Priority Submenu). Table 34 lists the boot device menu options. Table 34. Boot Device Menu Options
Boot Device Menu Function Keys <> or <> <Enter> <Esc> Description Selects a default boot device Exits the menu, saves changes, and boots from the selected device Exits the menu without saving changes
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3.8
3.8.1
3.8.2
Use of the following BIOS Setup program settings reduces the POST execution time. In the Boot Menu: Set the hard disk drive as the first boot device. As a result, the POST does not first seek a diskette drive, which saves about one second from the POST execution time. Disable Quiet Boot, which eliminates display of the logo splash screen. This could save several seconds of painting complex graphic images and changing video modes.
In the Peripheral Configuration submenu, disable the LAN device if it will not be used. This can reduce up to four seconds of option ROM boot time.
NOTE
It is possible to optimize the boot process to the point where the system boots so quickly that the Intel logo screen (or a custom logo splash screen) will not be seen. Monitors and hard disk drives with minimum initialization times can also contribute to a boot time that might be so fast that necessary logo screens and POST messages cannot be seen. This boot time may be so fast that some drives might be not be initialized at all. If this condition should occur, it is possible to introduce a programmable delay ranging from three to 30 seconds (using the Hard Disk Pre-Delay feature of the Advanced Menu in the Drive Configuration Submenu of the BIOS Setup program).
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3.9
The BIOS includes security features that restrict access to the BIOS Setup program and who can boot the computer. A supervisor password and a user password can be set for the BIOS Setup program and for booting the computer, with the following restrictions: The supervisor password gives unrestricted access to view and change all the Setup options in the BIOS Setup program. This is the supervisor mode. The user password gives restricted access to view and change Setup options in the BIOS Setup program. This is the user mode. If only the supervisor password is set, pressing the <Enter> key at the password prompt of the BIOS Setup program allows the user restricted access to Setup. If both the supervisor and user passwords are set, users can enter either the supervisor password or the user password to access Setup. Users have access to Setup respective to which password is entered. Setting the user password restricts who can boot the computer. The password prompt will be displayed before the computer is booted. If only the supervisor password is set, the computer boots without asking for a password. If both passwords are set, the user can enter either password to boot the computer. For enhanced security, use different passwords for the supervisor and user passwords. Valid password characters are A-Z, a-z, and 0-9. Passwords may be up to 16 characters in length.
Table 35 shows the effects of setting the supervisor password and user password. This table is for reference only and is not displayed on the screen. Table 35. Supervisor and User Password Functions
Password Set Neither Supervisor only User only Supervisor and user set Note: Supervisor Mode Can change all options (Note) Can change all options N/A Can change all options User Mode Can change all options (Note) Setup Options None Password to Enter Setup None Supervisor Password During Boot None None
Can change a Supervisor Password limited number of options Can change all options Enter Password Clear User Password
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4.1
Speaker
The board-mounted speaker provides audible error code (beep code) information during POST.
For information about The location of the onboard speaker Refer to Figure 1, page 12
4.2
Whenever a recoverable error occurs during POST, the BIOS displays an error message describing the problem (see Table 36). Table 36. Beep Codes
Type Memory error Thermal warning Pattern Three long beeps Four alternating beeps: High tone, low tone, high tone, low tone Frequency 1280 Hz High tone: 2000 Hz Low tone: 1600 Hz
4.3
Table 37 lists the error messages and provides a brief description of each. Table 37. BIOS Error Messages
Error Message CMOS Battery Low CMOS Checksum Bad Memory Size Decreased No Boot Device Available Explanation The battery may be losing power. Replace the battery soon. The CMOS checksum is incorrect. CMOS memory may have been corrupted. Run Setup to reset values. Memory size has decreased since the last boot. If no memory was removed then memory may be bad. System did not find a device to boot.
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4.4
During the POST, the BIOS generates diagnostic progress codes (POST-codes) to I/O port 80h. If the POST fails, execution stops and the last POST code generated is left at port 80h. This code is useful for determining the point where an error occurred. Displaying the POST-codes requires a PCI bus add-in card, often called a POST card. The POST card can decode the port and display the contents on a medium such as a seven-segment display.
NOTE
The POST card must be installed in PCI bus connector 1. The following tables provide information about the POST codes generated by the BIOS: Table 38 lists the Port 80h POST code ranges Table 39 lists the Port 80h POST codes themselves Table 40 lists the Port 80h POST sequence
NOTE
In the tables listed above, all POST codes and range values are listed in hexadecimal. Table 38. Port 80h POST Code Ranges
Range 00 0F 10 1F 20 2F 30 3F 40 4F 50 5F 60 6F 70 7F 80 8F 90 9F A0 AF B0 BF C0 CF D0 DF E0 FF Category/Subsystem Debug codes: Can be used by any PEIM/driver for debug. Host Processors: 1F is an unrecoverable CPU error. Memory/Chipset: 2F is no memory detected or no useful memory detected. Recovery: 3F indicated recovery failure. Reserved for future use. I/O Busses: PCI, USB, ISA, ATA, etc. 5F is an unrecoverable error. Start with PCI. Reserved for future use (for new busses). Output Devices: All output consoles. 7F is an unrecoverable error. Reserved for future use (new output console codes). Input devices: Keyboard/Mouse. 9F is an unrecoverable error. Reserved for future use (new input console codes). Boot Devices: Includes fixed media and removable media. BF is an unrecoverable error. Reserved for future use. Boot device selection. F0 FF: FF processor exception. E0 EE: Miscellaneous codes. See Table 39. EF boot/S3: resume failure.
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continued
79
continued
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5.1
Regulatory Compliance
Safety regulations European Union Declaration of Conformity statement Product Ecology statements Electromagnetic Compatibility (EMC) regulations Product certification markings
This section contains the following regulatory compliance information for Desktop Board D945GCCR:
5.1.1
Safety Regulations
Desktop Board D945GCCR complies with the safety regulations stated in Table 41 when correctly installed in a compatible host system. Table 41. Safety Regulations
Regulation
UL 60950-1:2003/ CSA C22.2 No. 60950-1-03 EN 60950-1:2002 IEC 60950-1:2001, First Edition
Title
Information Technology Equipment Safety - Part 1: General Requirements (USA and Canada) Information Technology Equipment Safety - Part 1: General Requirements (European Union) Information Technology Equipment Safety - Part 1: General Requirements (International)
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5.1.2
We, Intel Corporation, declare under our sole responsibility that the product Intel Desktop Board D945GCCR is in conformity with all applicable essential requirements necessary for CE marking, following the provisions of the European Council Directive 89/336/EEC (EMC Directive) and Council Directive 73/23/EEC (Safety/Low Voltage Directive). The product is properly CE marked demonstrating this conformity and is for distribution within all member states of the EU with no restrictions.
This product follows the provisions of the European Directives 89/336/EEC and 73/23/EEC. etina Tento vrobek odpovd poadavkm evropskch smrnic 89/336/EEC a 73/23/EEC. Dansk Dette produkt er i overensstemmelse med det europiske direktiv 89/336/EEC & 73/23/EEC. Dutch Dit product is in navolging van de bepalingen van Europees Directief 89/336/EEC & 73/23/EEC. Eesti Antud toode vastab Euroopa direktiivides 89/336/EEC ja 73/23/EEC kehtestatud nuetele. Suomi Tm tuote noudattaa EU-direktiivin 89/336/EEC & 73/23/EEC mryksi. Franais Ce produit est conforme aux exigences de la Directive Europenne 89/336/EEC & 73/23/EEC. Deutsch Dieses Produkt entspricht den Bestimmungen der Europischen Richtlinie 89/336/EEC & 73/23/EEC. 89/336/ 73/23/. Magyar E termk megfelel a 89/336/EEC s 73/23/EEC Eurpai Irnyelv elrsainak. Icelandic essi vara stenst regluger Evrpska Efnahags Bandalagsins nmer 89/336/ EEC & 73/23/EEC. Italiano Questo prodotto conforme alla Direttiva Europea 89/336/EEC & 73/23/EEC. Latvieu is produkts atbilst Eiropas Direktvu 89/336/EEC un 73/23/EEC noteikumiem. Lietuvi is produktas atitinka Europos direktyv 89/336/EEC ir 73/23/EEC nuostatas. Malti Dan il-prodott hu konformi mal-provvedimenti tad-Direttivi Ewropej 89/336/EEC u 73/23/EEC.
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Norsk Dette produktet er i henhold til bestemmelsene i det europeiske direktivet 89/336/ EEC & 73/23/EEC. Polski Niniejszy produkt jest zgodny z postanowieniami Dyrektyw Unii Europejskiej 89/336/EWG i 73/23/EWG. Portuguese Este produto cumpre com as normas da Diretiva Europia 89/336/EEC & 73/23/EEC. Espaol Este producto cumple con las normas del Directivo Europeo 89/336/EEC & 73/23/EEC. Slovensky Tento produkt je v slade s ustanoveniami eurpskych direktv 89/336/EEC a 73/23/EEC. Slovenina Izdelek je skladen z dolobami evropskih direktiv 89/336/EGS in 73/23/EGS. Svenska Denna produkt har tillverkats i enlighet med EG-direktiv 89/336/EEC & 73/23/EEC. Trke Bu rn, Avrupa Birliinin 89/336/EEC ve 73/23/EEC ynergelerine uyar.
5.1.3
The following information is provided to address worldwide product ecology concerns and regulations.
5.1.3.1
Disposal Considerations
This product contains the following materials that may be regulated upon disposal: lead solder on the printed wiring board assembly.
5.1.3.2
Recycling Considerations
As part of its commitment to environmental responsibility, Intel has implemented the Intel Product Recycling Program to allow retail consumers of Intels branded products to return used products to select locations for proper recycling. Please consult the http://www.intel.com/intel/other/ehs/product_ecology/Recycling_Program.htm for the details of this program, including the scope of covered products, available locations, shipping instructions, terms and conditions, etc. Intel Product Recycling Program http://www.intel.com/intel/other/ehs/product_ecology/Recycling_Program.htm
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Deutsch Als Teil von Intels Engagement fr den Umweltschutz hat das Unternehmen das Intel Produkt-Recyclingprogramm implementiert, das Einzelhandelskunden von Intel Markenprodukten ermglicht, gebrauchte Produkte an ausgewhlte Standorte fr ordnungsgemes Recycling zurckzugeben. Details zu diesem Programm, einschlielich der darin eingeschlossenen Produkte, verfgbaren Standorte, Versandanweisungen, Bedingungen usw., finden Sie auf der
http://www.intel.com/intel/other/ehs/product_ecology/Recycling_Program.htm
Espaol Como parte de su compromiso de responsabilidad medioambiental, Intel ha implantado el programa de reciclaje de productos Intel, que permite que los consumidores al detalle de los productos Intel devuelvan los productos usados en los lugares seleccionados para su correspondiente reciclado. Consulte la http://www.intel.com/intel/other/ehs/product_ecology/Recycling_Program.htm para ver los detalles del programa, que incluye los productos que abarca, los lugares disponibles, instrucciones de envo, trminos y condiciones, etc. Franais Dans le cadre de son engagement pour la protection de l'environnement, Intel a mis en uvre le programme Intel Product Recycling Program (Programme de recyclage des produits Intel) pour permettre aux consommateurs de produits Intel de recycler les produits uss en les retournant des adresses spcifies.
http://www.intel.com/intel/other/ehs/product_ecology/Recycling_Program.htm pour en savoir
plus sur ce programme, savoir les produits concerns, les adresses disponibles, les instructions d'expdition, les conditions gnrales, etc.
http://www.intel.com/intel /other/ehs/product_ecology/Recycling_Program.htm Malay Sebagai sebahagian daripada komitmennya terhadap tanggungjawab persekitaran, Intel telah melaksanakan Program Kitar Semula Produk untuk membenarkan pengguna-pengguna runcit produk jenama Intel memulangkan produk terguna ke lokasi-lokasi terpilih untuk dikitarkan semula dengan betul. Sila rujuk http://www.intel.com/intel/other/ehs/product_ecology/Recycling_Program.htm untuk mendapatkan butir-butir program ini, termasuklah skop produk yang dirangkumi, lokasi-lokasi tersedia, arahan penghantaran, terma & syarat, dsb.
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Portuguese Como parte deste compromisso com o respeito ao ambiente, a Intel implementou o Programa de Reciclagem de Produtos para que os consumidores finais possam enviar produtos Intel usados para locais selecionados, onde esses produtos so reciclados de maneira adequada. Consulte o site http://www.intel.com/intel/other/ehs/product_ecology/Recycling_Program.htm (em Ingls) para obter os detalhes sobre este programa, inclusive o escopo dos produtos cobertos, os locais disponveis, as instrues de envio, os termos e condies, etc. Russian , Intel Intel (Product Recycling Program) Intel . , -
http://www.intel.com/intel/other/ehs/product_ecology/Recycling_Program.htm
, , , , .. Trke Intel, evre sorumluluuna bamllnn bir paras olarak, perakende tketicilerin Intel markal kullanlm rnlerini belirlenmi merkezlere iade edip uygun ekilde geri dntrmesini amalayan Intel rnleri Geri Dnm Programn uygulamaya koymutur. Bu programn rn kapsam, rn iade merkezleri, nakliye talimatlar, kaytlar ve artlar v.s dahil btn ayrntlarn grenmek iin ltfen
http://www.intel.com/intel/other/ehs/product_ecology/Recycling_Program.htm
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5.1.3.3
This desktop board is lead free although certain discrete components used on the board contain a small amount of lead which is necessary for component performance and/or reliability. This desktop board is referred to as Lead-free second level interconnect. The board substrate and the solder connections from the board to the components (second-level connections) are all lead free. Table 42 shows the various forms of the Lead-Free 2nd Level Interconnect mark as it appears on the board and accompanying collateral. Table 42. Lead-Free Board Markings
Description
Lead-Free 2 Level Interconnect: This symbol is used to identify electrical and electronic assemblies and components in which the lead (Pb) concentration level in the desktop board substrate and the solder connections from the board to the components (second-level interconnect) is not greater than 0.1% by weight (1000 ppm).
nd
Mark
or
or
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5.1.4
EMC Regulations
Desktop Board D945GCCR complies with the EMC regulations stated in Table 43 when correctly installed in a compatible host system. Table 43. EMC Regulations
Regulation
FCC Class B ICES-003 (Class B) EN55022: 1998 (Class B) EN55024: 1998 AS/NZS CISPR 22 (Class B) CISPR 22, 3rd Edition, (Class B) CISPR 24: 1997 VCCI (Class B)
Title
Title 47 of the Code of Federal Regulations, Parts 2 and 15, Subpart B, Radio Frequency Devices. (USA) Interference-Causing Equipment Standard, Digital Apparatus. (Canada) Limits and methods of measurement of Radio Interference Characteristics of Information Technology Equipment. (European Union) Information Technology Equipment Immunity Characteristics Limits and methods of measurement. (European Union) Australian Communications Authority, Standard for Electromagnetic Compatibility. (Australia and New Zealand) Limits and methods of measurement of Radio Disturbance Characteristics of Information Technology Equipment. (International) Information Technology Equipment Immunity Characteristics Limits and Methods of Measurement. (International) Voluntary Control for Interference by Information Technology Equipment. (Japan)
Japanese Kanji statement translation: this is a Class B product based on the standard of the Voluntary Control Council for Interference from Information Technology Equipment (VCCI). If this is used near a radio or television receiver in a domestic environment, it may cause radio interference. Install and use the equipment according to the instruction manual.
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Korean Class B statement translation: this is household equipment that is certified to comply with EMC requirements. You may use this equipment in residential environments and other non-residential environments.
5.1.5
Desktop Board D945GCCR has the product certification markings shown in Table 44: Table 44. Product Certification Markings
Description
UL joint US/Canada Recognized Component mark. Includes adjacent UL file number for Intel desktop boards: E210882. FCC Declaration of Conformity logo mark for Class B equipment. Includes Intel name and D945GCCR model designation.
Mark
CE mark. Declaring compliance to European Union (EU) EMC directive (89/336/EEC) and Low Voltage directive (73/23/EEC).
Australian Communications Authority (ACA) C-tick mark. Includes adjacent Intel supplier code number, N-232.
S. Korea MIC (Ministry of Information and Communication) mark. Includes adjacent MIC certification number: CPU-D945GCCR
For information about MIC certification, go to http://support.intel.com/support/motherboards/desktop/ Taiwan BSMI (Bureau of Standards, Metrology and Inspections) mark. Includes adjacent Intel company number, D33025. Printed wiring board manufacturers recognition mark. Consists of a unique UL recognized manufacturers logo, along with a flammability rating (solder side). V-0
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5.2
Risk of explosion if the battery is replaced with an incorrect type. Batteries should be recycled where possible. Disposal of used batteries must be in accordance with local environmental regulations.
CAUTION
PRECAUTION
Risque d'explosion si la pile usage est remplace par une pile de type incorrect. Les piles usages doivent tre recycles dans la mesure du possible. La mise au rebut des piles usages doit respecter les rglementations locales en vigueur en matire de protection de l'environnement.
FORHOLDSREGEL
Eksplosionsfare, hvis batteriet erstattes med et batteri af en forkert type. Batterier br om muligt genbruges. Bortskaffelse af brugte batterier br foreg i overensstemmelse med gldende miljlovgivning.
OBS!
Det kan oppst eksplosjonsfare hvis batteriet skiftes ut med feil type. Brukte batterier br kastes i henhold til gjeldende miljlovgivning.
VIKTIGT!
Risk fr explosion om batteriet erstts med felaktig batterityp. Batterier ska kasseras enligt de lokala miljvrdsbestmmelserna.
VARO
Rjhdysvaara, jos pariston tyyppi on vr. Paristot on kierrtettv, jos se on mahdollista. Kytetyt paristot on hvitettv paikallisten ympristmrysten mukaisesti.
VORSICHT
Bei falschem Einsetzen einer neuen Batterie besteht Explosionsgefahr. Die Batterie darf nur durch denselben oder einen entsprechenden, vom Hersteller empfohlenen Batterietyp ersetzt werden. Entsorgen Sie verbrauchte Batterien den Anweisungen des Herstellers entsprechend.
AVVERTIMENTO
Esiste il pericolo di un esplosione se la pila non viene sostituita in modo corretto. Utilizzare solo pile uguali o di tipo equivalente a quelle consigliate dal produttore. Per disfarsi delle pile usate, seguire le istruzioni del produttore.
PRECAUCIN
Existe peligro de explosin si la pila no se cambia de forma adecuada. Utilice solamente pilas iguales o del mismo tipo que las recomendadas por el fabricante del equipo. Para deshacerse de las pilas usadas, siga igualmente las instrucciones del fabricante.
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WAARSCHUWING
Er bestaat ontploffingsgevaar als de batterij wordt vervangen door een onjuist type batterij. Batterijen moeten zoveel mogelijk worden gerecycled. Houd u bij het weggooien van gebruikte batterijen aan de plaatselijke milieuwetgeving.
ATENO
Haver risco de exploso se a bateria for substituda por um tipo de bateria incorreto. As baterias devem ser recicladas nos locais apropriados. A eliminao de baterias usadas deve ser feita de acordo com as regulamentaes ambientais da regio.
, . , , . .
ACIAROZNA
UPOZORNN
V ppad vmny baterie za nesprvn druh me dojt k vbuchu. Je-li to mon, baterie by mly bt recyklovny. Baterie je teba zlikvidovat v souladu s mstnmi pedpisy o ivotnm prosted.
. . .
VIGYAZAT
Ha a telepet nem a megfelel tpus telepre cserli, az felrobbanhat. A telepeket lehetsg szerint jra kell hasznostani. A hasznlt telepeket a helyi krnyezetvdelmi elrsoknak megfelelen kell kiselejtezni.
AWAS
Risiko letupan wujud jika bateri digantikan dengan jenis yang tidak betul. Bateri sepatutnya dikitar semula jika boleh. Pelupusan bateri terpakai mestilah mematuhi peraturan alam sekitar tempatan.
OSTRZEENIE
Istnieje niebezpieczestwo wybuchu w przypadku zastosowania niewaciwego typu baterii. Zuyte baterie naley w miar moliwoci utylizowa zgodnie z odpowiednimi przepisami ochrony rodowiska.
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PRECAUIE
Risc de explozie, dac bateria este nlocuit cu un tip de baterie necorespunztor. Bateriile trebuie reciclate, dac este posibil. Depozitarea bateriilor uzate trebuie s respecte reglementrile locale privind protecia mediului.
. . , .
Ak batriu vymente za nesprvny typ, hroz nebezpeenstvo jej vbuchu. Batrie by sa mali poda monosti vdy recyklova. Likvidcia pouitch batri sa mus vykonva v slade s miestnymi predpismi na ochranu ivotnho prostredia.
UPOZORNENIE
Zamenjava baterije z baterijo druganega tipa lahko povzroi eksplozijo. e je mogoe, baterije reciklirajte. Rabljene baterije zavrzite v skladu z lokalnimi okoljevarstvenimi predpisi.
POZOR
Yanl trde pil takldnda patlama riski vardr. Piller mmkn olduunda geri dntrlmelidir. Kullanlm piller, yerel evre yasalarna uygun olarak atlmaldr.
UYARI
, . , . , .
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