TABLE OF CONTENTS

CHAPTER TITLE NAME NUMBER

i Ii Iii iv 1 2 3 3.1 3.2 3.3 3.3.2 4 4.1 Title of the Project Certificate Acknowledgement Abstract Introduction Simulation Core Object Models CPU Models The O3CPU Pipeline and time buffers Memory System I/O Devices Ethernet Overview of Graphical Processing Unit (GPU)

PAGE NUMBER

i ii iii iv 1-2 3-6 7 8-9 10-11 12-13 14 15 16-19

5 6 7 8

GPU architecture Pitfalls of Simulating Networking Workloads Validating M5 Conclusion References

20-23 24-28 29-30 31 32 33

Appendix

TABLE OF FIGURE

FIGURE NUMBER
1 2 3 4 5

FIGURE NAME
Backward Communication A sample system hierarchy GPU GPU Performance Architectural Voodoo 3 GPU Overview

PAGE NUMBER
10 13 17 19 of 20

Voodoo 3 GPU 2D Block Diagram

22

Voodoo 3 GPU FBI/TMU 23 Block Diagram

8 9

Sender and Receiver Diagram Flow Chart

26 27