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4. CMOS Transistor Theory

J. A. Abraham

60 Department

of Electrical and Computer Engineering The University of Texas at Austin EE 382M.7 VLSI I Fall 2011
September 7, 2011

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Lecture 4. CMOS Transistor Theory

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Electrical Properties
Necessary to understand basic electrical properties of the MOS mm to design transistor 40 useful circuits 60 80 100 Deal with non-ideal devices Ensure that the circuits are robust Create working layouts Predict delays and power consumption As circuit dimensions scale down, electrical eects become more 60 important, even for digital circuits
1.65 GHz square wave from an 80 HDMI Interface (Source: Dunnihoo, EE Times Asia, 8/25/2005)
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The nMOS Transistor

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Terminal Voltages Modes of operation depend on Vg , Vd , Vs

60 Vgs = Vg Vs Vgd = Vg Vd Vd s = Vd Vs = Vgs Vgd

Source and drain are symmetric diusion terminals

By convention, source is terminal at lower voltage, so Vds 0 80 nMOS body is grounded for simple designs; assume source is 0

Three regions of operation: Cuto, Linear, Saturated

Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 2 / 31

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Modes in nMOS Structure

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nMOS Transistor Operation

Positive voltage on Gate produces electric eld across substrate attracts to the Gate 60 and repels holes mm electrons 40 80 100 120 With sucient voltage, region under Gate changes from p- to n-Type conducting path between the Source and Drain Inversion layer is eld-induced junction, unlike a PN junction which is metallurgical 40 Horizontal component of electric eld associated with Vds > 0 is responsible for sweeping electrons from channel to drain Threshold Voltage 60 The gate voltage at which conduction takes place is the Threshold Voltage, Vt Current ow occurs when the drain to source voltage Vds > 0, and 80 consists almost entirely of majority-carriers (electrons), that ow through the channel A depletion region insulates the channel from the substrate
ECE Department, University of Texas at Austin Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 4 / 31

Conducting nMOS Transistor

Conduction when Vgs > Vt and Vds > 0
No signicant current through the substrate because of reverse mm biased PN 40junction with 60 the channel80 100 120 As the voltage from drain to source is increased, the resistive drop along the channel begins to change the shape of the channel characteristic At source end of the channel, the full gate voltage is eective 40 in inverting the channel At drain end of the channel, only the dierence between the gate and the drain voltage is eective

If Vds > Vgs Vt , then Vgd < Vt , and the channel is pinched down (the inversion layer no longer reaches the drain) 60
In this case, conduction is brought about by the drift mechanism of electrons under the inuence of positive drain voltage; as the negative electrons leave the channel, they are accelerated towards the drain 80 Voltage across the pinchdown channel tends to remain xed at (Vgs Vt ), and the channel current remains constant with increasing Vds
ECE Department, University of Texas at Austin Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 5 / 31

nMOS Device Behavior

Vgs > Vt , Vds = 0
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Nonsaturated Mode Vds < Vgs Vt

Saturated Mode (Vds > Vgs Vt )

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The pMOS Transistor

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Moderately doped n- type substrate (or well) in which two heavily doped p+ regions, the Source and Drain, are diused

Application of a negative gate voltage (w.r.t. source) draws holes 60 into the region below the gate; channel changes from n to p-type (source-drain conduction path) Conduction due to holes; negative Vd sweeps holes from source (through channel) to drain
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Current in the Channel

In the Linear region, Ids depends on how much charge there is in mm 40 fast the charge 60 80 100 120 the channel and how is moving Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion (Gate Oxide Channel) 40 Qchannel = CV C = Cg =
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ox W L/tox

= Cox W L (Cox =

ox /tox )

V = Vgc Vt = (Vgs Vds /2) Vt

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Carrier Velocity
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Charge is carried by electrons Carrier velocity proportional to lateral E- eld between 40 source and drain = E
is called mobility

E = Vds /L
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Time for carrier to cross channel: t = L/

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I-V Characteristics
nMOS Linear I-V Current from 60 charge in channel and the mm can be obtained 40 80 100time t each carrier takes to cross Qchannel Ids = t W 40 = Cox (Vgs Vt Vds /2) Vds L = (Vgs Vt Vds /2) Vds nMOS Saturation I-V 60 If Vgd < Vt , channel pinches o near drain
when Vds > Vdsat = Vgs Vt 120

Now drain voltage no longer increases with current

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Ids = (Vgs Vt Vdsat /2) Vdsat = (Vgs Vt )2 2

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ECE Department, University of Texas at Austin

nMOS I-V Summary

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Shockley First Order transistor models

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Ids

0 Vgs < Vt Cutof f (Vgs Vt Vds /2) Vds Vds < Vdsat Linear = 2 ( V V ) V > V Saturation gs t ds dsat 2
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pMOS I-V
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All dopings and voltages are inverted for pMOS (compared with nMOS)
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Mobility p is determined by holes

Typically 2x-3x lower than that of electrons n

Thus pMOS must be wider to provide the same current

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n p

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Capacitance
Capacitance in CMOS circuits Two conductors separated by an insulator have capacitance mm 40 60 80 100 Gate to channel capacitor is very important
Creates channel charge necessary for operation 120

Source and drain have capacitance to body

40 Across reverse-biased diodes Called diusion capacitance because it is associated with source/drain diusion

Interconnection wires also have (distributed) capacitance

60 Gate Capacitance Approximate channel as connected to source

Cgs = ox W L/tox = Cox W L = 80 Cpermicron W Typical Cpermicron 2fF/m

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ECE Department, University of Texas at Austin

Device Capacitances
The mm dynamic response (switching speed) of a CMOS circuit is 40 60 80 100 120 very dependent on parasitic capacitances associated with the circuit Use a simple approximation for quick estimates 40 of capacitances; use tools for extraction of more accurate values from actual layouts
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Consider the capacitances seen during the dierent regions of operation 80

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Device Capacitances, Contd

O Region
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Vgs Vt ; when the MOS device is o, only Cgb (due to the series combination of gate oxide and depletion layer capacitance) is non-zero. Cgb = Cox = A/tox , where A is the gate area, and 40 = 0 SiO2
is the permittivity of free space (8.854 104 F/m), and SiO2 is the dielectric constant of SiO2 (about 3.9)
0

60 Linear Region Depletion region exists, forming dielectric of depletion capacitance, Cdep in series with Cox

As the device turns on, Cgb reduces to 0

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The gate capacitance is now a function of the gate voltage

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Device Capacitances, Contd

Saturated Region Region under40 the gate is 60 heavily inverted, mm 80 and drain 100region of 120 channel pinched o, with Cgd reducing to zero Gate capacitance is now less than Cox
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Source: Mlynik and Leblebici EPFL web-based course

Approximation of Gate Capacitance 80 For simplicity, we can assume the gate capacitance to be constant, Cg = A/tox
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Diusion (Source/Drain) Capacitance

Capacitance at the drain (Cdb ) or source (Csb ) of a device, or when mm is used as 40 60 diusion a wire Two components:
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An Area component A Peripheral (sidewall) 40 component

The peripheral component comes from the depth of the diusion

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Assume diusion capacitance is approximately Cg for contacted diusion 80 It is 1/2Cg for uncontacted diusion
Lecture 4. CMOS Transistor Theory

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Uncontacted
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ECE Department, University of Texas at Austin

J. A. Abraham, September 7, 2011

Pass Transistors
Have assumed that source is grounded
mm 40 What happens if source > 0? 60 Example, pass transistor passing VDD Vg = VDD 40 If Vs > VDD Vt , Vgs < Vt Hence, transistor would turn itself o 80 100 120

nMOS 60pass transistors pull no higher than VDD Vt Called a degraded 1 Degraded value reached slowly in a transition (low Ids )
80pass transistors pull no lower than Vtp pMOS

Degraded 0
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Pass Transistor Circuits

mm 40 voltages on 60the dierent 80 nodes? 100 What would be the 120

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Pass Transistor Circuits

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What would be the voltages on the dierent nodes?

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Pass Transistor Circuits

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What would be the voltages on the dierent nodes?

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Example 1
Assumption: initial voltage on each node is 2.5 volts
mm transistor 40parameters60 80 Relevant are, Vdd = 5 V , Vtn = 1100 V and |Vtp | = 0.7V 120

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Example 1, Contd
Vdd = 5V , Vtn = 40 1V and |Vtp |60 = 0.7V mm
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Example 2
Assume: initial voltage of 0.5V on all the internal nodes Vdd = 1.0V , Vtn = Vtp | = 0.2V 80 mm 400.2V and |60
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Lecture 4. CMOS Transistor Theory

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Example 2, Contd
Assume: initial voltage of 0.5V on all the internal nodes Vdd = 1.0V , Vtn = Vtp | = 0.2V 80 mm 400.2V and |60
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Eective Resistance
Resistance of a bar of uniform material R= A = t W mm 40 60 80 where = resistivity of the material A = cross-section of the resistor t, W = thickness, width of the material
L L

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The channel resistance of a MOS transistor in the linear L 40 , region, Rc = k W

where k =
1 Cox (Vgs Vt )

Resistance values depend on the technology 60 Obtain the information from the technology les Sheet resistance (/ )
Lowest for metal, increases for poly, active, highest for Well

Contact (via) resistance becomes more important as 80 processes scale down Channel (turned-on transistor) on the order of 1000 /
ECE Department, University of Texas at Austin Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 26 / 31

Example of Process Parameters and Simulation

Example: TSMC 0.18 process
mm 40 60 80 100 120 http://www.mosis.com/cgi-bin/cgiwrap/umosis/swp/params/tsmc-018/

Look at one process Example of SPICE simulation

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Resistance on a Turned-On Transistor

Circuit delay depends on resistance and capacitance delay mm on RC 40 60 80 100 120 depends Need to deal with the resistance of conducting transistors and interconnects Shockley models have limited value for obtaining resistance
40 Not accurate enough for modern transistors Too complicated for much hand analysis Replace Ids (Vds , Vgs ) with eective resistance R ds Ids = VR R averaged across switching of digital gate

Simplication: treat transistor as resistor

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Too inaccurate to predict current at any given time, but good enough to predict RC delay
80 More accurate values of delay obtained from detailed design using the tools
ECE Department, University of Texas at Austin Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 28 / 31

RC Delay Model
Use mm equivalent circuits for MOS 40 60 transistors 80 Ideal switch + capacitance and ON resistance
Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C 40 Capacitance proportional to width 100 120

Resistance inversely proportional to width

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Inverter Delay Estimate

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Estimate the delay of a fanout-of-1 inverter

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Inverter Delay Estimate

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Estimate the delay of a fanout-of-1 inverter

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d = 6RC
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