Codigo VHDL

EJERCICIO BCD
library ieee; use ieee.std_logic_1164.all; Entity bcd is Port (X1,X2,X3,X4: in bit; a,b,c,d,e,f,g: out bit); End bcd; architecture RTL of bcd is begin a <=X1 OR X3 OR (NOT(X2) AND (NOT(X4))) OR (X2 AND X4); b <=NOT(X2) OR (X3 AND X4) OR (NOT(X3) AND NOT(X4)); c <=X2 OR NOT(X3) OR X4; d <=X1 OR (NOT(X2) AND X3) OR (NOT(X2) AND NOT(X4)) OR (X3 AND NOT(X4)) OR (X2 AND NOT(X3) AND X4); e <=(X3 AND NOT(X4)) OR (NOT(X2) AND NOT(X4)); f <=X1 OR (NOT(X3) AND NOT(X4)) OR (X2 AND NOT(X3)) OR (X2 AND NOT(X4)); g <=X2 OR (NOT(X2) AND X3) OR (X2 AND NOT(X3)) OR (X2 AND NOT(X4)); end RTL;

SIMULACION

Codigo VHDL
EJERCICIO DISPLAY NOMBRE JOSEPH
library ieee; use ieee.std_logic_1164.all; Entity nombre1display is Port (X1,X2,X3: in bit; a,b,c,d,e,f,g: out bit); End nombre1display; architecture RTL of nombre1display is begin a <= X2 OR (X1 AND NOT(X3)) OR (NOT(X1) AND X3); b <= X1 OR NOT(X2); c <= (NOT(X1) AND NOT(X3)) OR (NOT(X2) AND X3) OR (X2 AND NOT(X3)); d <= X2 OR NOT(X1); e <= X1 OR X3; f <= X1 OR X2; g <= X2 OR X1 OR X3; end RTL;

SIMULACION

Codigo VHDL
EJERCICIO DISPLAY NOMBRE XAVIER
library ieee; use ieee.std_logic_1164.all; Entity nombre2display is Port (X1,X2,X3: in bit; a,b,c,d,e,f,g: out bit); End nombre2display; architecture RTL of nombre2display is begin a <= X1 OR (NOT(X2) AND X3); b <= (NOT(X1) AND NOT(X3)) OR (NOT(X1) AND NOT(X2)); c <= (NOT(X1) AND NOT(X3)) OR (NOT(X1) AND NOT(X2)); d <= (X1 AND NOT(X3)) OR (X2 AND NOT(X3)); e <= '1'; f <= '1'; g <= (NOT(X1)AND NOT(X2)) OR (NOT(X2) AND NOT(X3)); end RTL;

SIMULACION