International Conference on Computing and Control Engineering (ICCCE 2012), 12 & 13 April, 2012

VLSI IMPLEMENTATION OF LOW POWER MULTIPLIER

N.Nithyalakshmi Electronics& Communication Engineering, B.S.Abdur Rahman University,Chennai-48, Tamil Nadu , India. email: nithyanarayanan88@gmail.com

ABSTRACT Multiplier is one of the key logic blocks in most digital and high performance systems. Among them booth multiplier is widely used. Here, radix 2 booth multiplier based on conventional carry select adder and also based on modified carry select adder has been developed. The carry select adder is used in partial product addition of booth multiplier. The designs are tested and compared using NClaunch in cadence. Results show that modified carry select adder based on binary to excess 1 converter is efficient than conventional adder. Keywords: Booth multiplier, Carry Select Adder, Ripple Carry Adder, Binary to Excess 1 converter 1.INTRODUCTION Multipliers offer either of the following- high speed, low power consumption, less area or even combination of them. This makes them suitable for various high speed, low power, and compact VLSI implementations. Area and speed are the two main constraints of any multiplier and optimizing them is a major design issue. Here, the booth multiplier is optimized by using Carry Select Adder. Carry Select Adder is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. It alleviates the problem of carry propagation delay by independently generating multiple carries and then selects a carry to generate the sum [1]. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. Carry-select method has deemed to be a good compromise between cost and performance in carry propagation adder design. The square root CSLA requires less power, area and has balanced delay [2], [3]. However, conventional carry-select adder is still area consuming due to the dual Ripple Carry Adder (RCA) structure. In order to reduce the area and power consumption the dual array of RCA is replaced by a single array of RCA and an array of Binary to Excess 1 Converter (BEC) [4][6]. Multiplication is normally done in two steps- Partial product generation and addition. In booth multiplication, partial product generation is done based on radix 2 encoding which is as given by Table1. Bits of multiplicand (Y) are grouped from left to right and corresponding operation on multiplier (X) is done to generate partial product. The addition of partial

ISBN 978-1-4675-2248-9 2012 Published by Coimbatore Institute of Information Technology

International Conference on Computing and Control Engineering (ICCCE 2012), 12 & 13 April, 2012

products is carried out by using CSLA. The flow of radix 2 booth multiplication is show in Fig.1 Table 1: Radix 2 encoding

Y1 0 0 1 1 Fig.1. Flow of booth multiplication 2.CONVENTIONAL CARRY SELECT ADDER

Y0 0 1 0 1

Operation X*0 X*1 X<<1 X+(X<<1)

In conventional Carry select adder, blocks of bits are added in two ways: one assuming a carry-in of 0 and the other with a carry-in of 1.This results in two pre-computed sum and carry-out signal pairs. The correct output is selected based on the original carry-in. Generally multiplexers are used to propagate carries. Fig.2 shows the internal logic schematic of a carry select adder constructed using the conventional ripple carry adder (RCA). The RCA uses multiple full adders to perform addition operation. Each full adder inputs a carry-in, which is the carry-out of the preceding adder. The CSA divides the words to be added into blocks and forms two sums for each block in parallel, one with assumed carry in (Cin) of 0 and the other with Cin of 1. As shown in Fig. 2, the carry-out from one stage of RCA is used as the select signal for the multiplexer. This selects the corresponding sum bit from the next block of data. This speeds-up the computation process of the adder. Thus, the carry select adder achieves higher speed of operation at the cost of increased number of devices used in the circuit. This in turn increases the area and power consumed by the circuits of this type of structure. The logic equations of the adder are as follows:

si
ci

si 0 c si1c
ci 0 ci1c

Si refers to the sum out at each stage and Ci refers to the carry out. C is the carry in, depending on which the correct sum out and carry out are selected by multiplexer. The proposed adder circuit is obtained by replacing the second RCA block of Fig.2 with the basic unit. The basic unit consists of Binary to Excess 1 Converter as shown in Fig.3. The 4-bits B0 to B3 are applied to the basic unit as input. The incremented outputs X0 to X3 are generated through the logic function as shown in Fig.3.

ISBN 978-1-4675-2248-9 2012 Published by Coimbatore Institute of Information Technology

International Conference on Computing and Control Engineering (ICCCE 2012), 12 & 13 April, 2012

Fig.2. Conventional CSLA 3.PROPOSED CARRY SELECT ADDER Fig.3 shows the logic diagram of BEC. The Boolean expressions depicting the 4-bit basic block are listed below:

X0= ~B0; X1=B1^B0; X2=B2^(B1*B0); X3=B3^(B0&B1&B2);

Fig.3. Binary to excess 1 As stated above the main idea of this work is to use BEC instead of the RCA with Cin = 1 in order to reduce the area and power consumption of the regular CSLA. To replace the n-bit RCA, an n+1-bit BEC is required. This produces the two possible partial results in parallel and the multiplexer is used to select either the BEC output or the direct inputs according to the control signal Cin. Fig.4 illustrates how the basic function of the CSLA is obtained by using the 4-bit BEC together with the multiplexer. The least significant bits are

Fig.4. Modified CSLA

ISBN 978-1-4675-2248-9 2012 Published by Coimbatore Institute of Information Technology

International Conference on Computing and Control Engineering (ICCCE 2012), 12 & 13 April, 2012

added using conventional RCA, while other blocks are added in parallel along with the given incrementer. Once all the interim sums and carries are calculated, the final sums are computed using multiplexers having minimal delay. The multiplexer block receives the two sets of input and selects the final sum based on the select input from the previous stage. One input of the 8:4 multiplexer gets as its input B3, B2, B1, and B0 and another input of the multiplexer is the BEC output. The importance of the BEC logic stems from the large silicon area reduction when the CSLA with large number of bits are designed. Use of BEC with multiplexer thus achieves fast incrementing action with reduced device count. Thus, the proposed CSA excels the conventional CSA circuit in terms of area and power. 4.IMPLEMENTATION RESULTS The radix 2 booth multiplier using carry select adder and modified carry select adder has been designed in Verilog HDL and synthesized in Cadence using NClaunch. The results of the simulation and synthesis are given in Fig.5 and Table 2 respectively.Results show that the booth multiplier using modified CSLA occupies less area and consumes less power compared to regular CSLA. The power consumed is a sum of leakage and dynamic power. This proves that carry select adder using binary to excess 1 converter is efficient for VLSI implementation.

Fig.5. Simulation output for 8x8 booth multiplier using CSLA Table 2: Synthesis output for 8x8 booth multiplier using regular CSLA and modified CSLA Adder Power (nw) Area ( m2 ) Regular CSLA Modified CSLA REFERENCES [1] O. J. Bedrij, Carry-select adder, IRE Trans. Electron. Comput., pp. 340344, 1962. [2] J. M. Rabaey, Digtal Integrated CircuitsA Design Perspective. Upper Saddle River, NJ: Prentice-Hall, 2001. 830195.287 670596.722 6127 5276

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International Conference on Computing and Control Engineering (ICCCE 2012), 12 & 13 April, 2012

[3] Y. He, C. H. Chang, and J. Gu, An area efficient 64-bit square root carry-select adder for lowpower applications, in Proc. IEEE Int. Symp. Circuits Syst., 2005, vol. 4, pp. 4082 4085. [4] B. Ramkumar, H.M. Kittur, and P. M. Kannan, ASIC implementation of modified faster carry save adder, Eur. J. Sci. Res., vol. 42, no. 1, pp. 5358, 2010. [5] T. Y. Ceiang and M. J. Hsiao, Carry-select adder using single ripple carry adder, Electron. Lett., vol. 34, no. 22, pp. 21012103, Oct. 1998. [6] Y. Kim and L.-S. Kim, 64-bit carry-select adder with reduced area, Electron. Lett., vol. 37, no. 10, pp. 614615, May 2001. [7] Cadence, Encounter user guide, Version 6.2.4, March 2008.

ISBN 978-1-4675-2248-9 2012 Published by Coimbatore Institute of Information Technology