Gii thiu Verilog, Quartus

Bi Vn Hiu Khoa Cng ngh thng tin Trng H Bch Khoa TPHCM

Ni dung
Gii thiu cch vit chng trnh bng ngn ng Verilog Hng dn s dng phn mm Quartus

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Mt s c im c bn ca Verilog
L ngn ng ta C Phn bit ch hoa v ch thng C th h tr m t mch bng nhiu cch
Cu trc (structural): kt ni cc thnh phn c thnh mch mi Hnh vi (behavioral): ch m t chc nng ca mch, cng c t ng s sinh ra mch

Bi Vn Hiu FCSE - DCE

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Gii thiu ngn ng Verilog

Cu trc mt chng trnh
Khai bo module:
module module_name (PORT LIST) ;

Khai bo cc port
input PORT NAME ; output PORT NAME ;

Khai bo cc dy ni:
wire WIRE NAME ;

Kt ni cc wire v cc module vit sn endmodule

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M t mch theo kiu cu trc

Lnh assign S dng mt module c
module_name instance_name (PORT LIST)

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V d
Vit chng trnh mch cng bn phn

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Hng dn Quartus
To Project vi Quartus Thm file vo project Tng hp project M phng Gn chn Np chng trnh

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Bi tp
Ch s dng wire v cc module c sn trong file logic_gate.v xy dng, m phng, np chy th cc mch
Gii m BCD ra led by on Mch cng, tr hai s nh phn 4 bit IC74163 IC74194

Lm tt c cc IC h 74 (chia nhm) Lm cc bi lab trong CD kit DE2 Bui sau mi nhm 5 pht demo kt qu lm c
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