library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.

ALL; entity laboratorio is Port ( X : in STD_LOGIC_VECTOR (15 downto 0); Y : in STD_LOGIC_VECTOR (15 downto 0); C : in STD_LOGIC_VECTOR (15 downto 0); H : in STD_LOGIC_VECTOR (15 downto 0); x : out STD_LOGIC_VECTOR (10 downto 0); y : out STD_LOGIC_VECTOR (10 downto 0); c : out STD_LOGIC_VECTOR (11 downto 0) h : out STD_LOGIC_VECTOR (10 downto 0) l : out STD_LOGIC_VECTOR (10 downto 0));

clk : in STD_LOGIC; enax : in STD_LOGIC; enay : in STD_LOGIC; enac : in STD_LOGIC; enah : in STD_LOGIC; enal : in STD_LOGIC; rst : in STD_LOGIC); end laboratorio;

architecture Behavioral of laboratorio is

signal sigx : in std_logic_vector (15 downto 0) := (others => '0'); signal sigy : in std_logic_vector (15 downto 0) := (others => '0'); signal sigc : in std_logic_vector (15 downto 0) := (others => '0'); signal sigh : in std_logic_vector (15 downto 0) := (others => '0'); signal sigmul : in std_logic_vector (15 downto 0) := (others => '0'); signal sigl : in std_logic_vector (15 downto 0) := (others => '0'); begin X: process (clk, reset)

begin if rst = '1' then sig x<= (others => '0'); elsif clk event and clk = '1' then if enax = '1' then sig x<= X; else null; end if; end if; end process; x <= sigx(15)& sigx(14)& sigx(13)& sigx(12)& sigx(11)& sigx(10)& sigx(9)& sigx(8)& sigx(7)& sigx(6)& sigx(5);

Y: process (clk, reset) begin if rst = '1' then sigy <= (others => '0'); elsif clk event and clk = '1' then if enay = '1' then sigy <= Y; else null; end if; end if; end process; y <= sigy(15)& sigy(14)& sigy(13)& sigy(12)& sigy(11)& sigy(10)& sigy(9)& sigy(8)& sigy(7)& sigy(6)& sigy(5);

C: process (clk, reset) begin if rst = '1' then sigc <= (others => '0'); elsif clk event and clk = '1' then if enac = '1' then sigc <= C; else null; end if;

end if; end process; c <= sigc(15)& sigc(14)& sigc(13)& sigc(12)& sigc(11)& sigc(10)& sigc(9)& sigc(8)& sigc(7)& sigc(6)& sigc(5)& sigc(4);

H: process (clk, reset) begin if rst = '1' then sigh <= (others => '0'); elsif clk event and clk = '1' then if enah = '1' then sigh <= H; else null; end if; end if; end process; h <= sigh(15)& sigh(14)& sigh(13)& sigh(12)& sigh(11)& sigh(10)& sigh(9)& sigh(8)& sigh(7)& sigh(6)& sigh(5);

L: process (clk, reset) begin if rst = '1' then sigl <= (others => '0'); elsif clk event and clk = '1' then if enal = '1' then sigmul <= h; sigl <= sigmul x x3; else null; end if; end if; end process; l <= sigl(15)& sigl(14)& sigl(13)& sigl(12)& sigl(11)& sigl(10)& sigl(9)& sigl(8)& sigl(7)& sigl(6)& sigl(5); end Behavioral;

DATAPATH
entity datap is port ( clk, reset : in bit; multiplicand, multiplier : in integer; product : out integer ); end entity datap; architecture mixed of datap is signal partial_product, full_product : integer; signal arith_control, result_en, mult_bit, mult_load : bit; begin arith_unit : entity work.shift_adder(behavior) port map ( addend => multiplicand, augend => full_product, sum => partial_product, add_control => arith_control ); result : entity work.reg(behavior) port map ( d => partial_product, q => full_product, en => result_en, reset => reset );