BI TP K THUT S 2

SINH VIN THC HIN : Thng Thng Hng

LP : HT08ALT
MSSV :

12084211
BI LM

Bi tp 1 : S dung T-FF thit k mch c grap sau ::

Gii :
Nhn vo grap ta nhn thy rng :
Mch c 1 ng vo C
Hai ng ra A v B
Mch c 4 trng thi trong nn ta chn s ng ra n
Vy ta chn 2 T-FF.
Ta chon Pr tch cc mc cao
Chn Cl tch cc mc cao
Chn xung Ck tc ng cnh ln
T grap ta c bng trng thi sau :

=2

TT hin ti

0
0
1
1

0
1
0
1

Trng thi k tip

C=0
C=1
0
1
0
0

1
0
0
0

1
0
0
0

Ng vo T-FF
C=0
C=1
1
0
1
0

0
1
1
1

1
1
0
1

1
0
1
1

S mch thit k :

+ C

Ng ra

1
1
1
1

A
0
1
0
0

B
0
0
0
1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY BAI_1 IS PORT // khai bo module, input, output.
(clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
C : IN STD_LOGIC;
a,b : OUT STD_LOGIC);
END BAI_1;
ARCHITECTURE Behavioral OF BAI_1 IS // khai bo bin trng thi ca module.
TYPE state_type IS (s0,s1,s2,s3);
4 bin: s0, s1, s2, s3
SIGNAL state : state_type;
BEGIN
// bt u ARCHITECTURE
Next_state_logic : PROCESS (clock,reset) // process thc hin ( nhy sang trng thi k)
BEGIN // bt u ca hm process
//khi c bt k s thay i no ca tn hiu clock hoc reset.
IF(reset='1')THEN
// nu reset = 1, (tc ng n process) th trng thi k l s0.
state <= s0;
ELSIF(clock'EVENT AND clock = '1')THEN // hoc clock = 1 th
CASE state IS
xt n trng thi hin ti l ? c bn trng hp
WHEN s0=>
// TH1 : trng thi l s0
IF C='1' THEN
nu C = 1, th trng thi k l s3
state <=s3;
ELSE
C = 0, trng thi k l s1
state <=s1;
END IF;
WHEN s1=>
// TH2 : trng thi l s1
IF C='1' THEN
nu C = 1, trng thi k l s0
State <= s0;
ELSE
C = 0, trng thi k l s2
State <=s2;
END IF;
WHEN s2=>
// TH3 : trng thi l s2
IF C='1' THEN
nu C = 1, th trng thi k l s1
state <=s1;
ELSE
C = 0, trng thi k l s0
state <=s0;
END IF;
WHEN s3=>
// TH4 : trng thi l s3
state <=s0;
trng thi k l s0 (C ty nh)
END CASE; // kt thc hm CASE
END IF;
// kt thc hm IF (hm ln u chng trnh)

END PROCESS; // kt thc PROCESS

Out_logic: PROCESS (state)
// on chng trnh ng ra: PROCESS thc hin khi c
BEGIN
//s thay i bin trng thi (bin nhy l state)
CASE state IS
// c 4 trng hp
WHEN s0=>
// TH1: trng thi s0, ng ra ab=00.
a<='0';
b<='0';
WHEN s1=>
// TH2: trng thi s1, ng ra ab=10.
a<='1';
b<='0';
WHEN s2=>
// TH3: trng thi s2, ng ra ab=00.
a<='0';
b<='0';
WHEN s3=>
// TH4: trng thi s3, ng ra ab=01.
a<='0';
b<='1';
END CASE; // kt thc CASE.
END PROCESS; // kt thc PROCESS
END Behavioral; // kt thc ARCHITECTURE

Bi tp 2 :S dung T-FF thit k mch c grap sau :

Gii :
Da vo grap trn ta suy ra :
Mch c 2 ng vo
2 ng ra

 4 trng thi trong

Da vo grap ta c bng trng thi sau :
Trng thi k tip
Ng vo T-FF
Present
status AB=00 AB=01 AB=10 AB=11 AB=00 AB=01 AB=10 AB=11
0
0
1
1

0
1
0
1

0
0
0
0

1
0
1
0

0
1
0
0

1
0
1
0

0
0
1
1

0
0
0
1

0
1
1
1

0
1
0
1

0
0
1
0

1
1
1
1

Bng trng thi ng ra

TT hin ti
0
0
1
1
S mch thit k :

0
1
0
1
Y=X=

output
X
Y
1
1
0
0
1
1
1
1

0
1
1
1

1
1
1
1

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY BAI_2 IS PORT(
// khai bo module, input, output
Clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
A,B : IN STD_LOGIC;
X,Y: OUT STD_LOGIC);
END BAI_2;
ARCHITECTURE Behavioral OF BAI_2 IS // khai bo bin trng thi ca module
TYPE state_type IS (s0,s1,s2,s3);
4 bin s0, s1, s2, s3
SIGNAL state : state_type;
BEGIN
Next_state_logic : PROCESS (clock,reset) // tng t bi 1. hm PROCESS c 2 bin
BEGIN
nhy l clock v reset.
IF (reset='1') THEN
// nu reset = 1, trng thi k l s0
state <= s0;
ELSIF (clock'EVENT AND clock ='1')THEN // nu clock = 1 th
CASE state IS
xt trng thi hin ti ?
WHEN s0=>
// TH1: trng thi l s0
IF A='0' THEN
nu A = 0, th trng thi k l s1.
state <=s1;
ELSE
A = 1, th trng thi k l s0
state <=s0;
END IF;
WHEN s1=>
// tng t nh bi 1
IF A='0' AND B='0' THEN
State <= s0;
ELSIF A='0' AND B='1' THEN

State <= s2;

ELSIF A='1' AND B='0' THEN
State <= s1;
ELSE
State <=s3;
END IF;
WHEN s2=>
IF A='0' THEN
state <=s1;
ELSE
state <=s2;
END IF;
WHEN s3=>
IF A='0' THEN
state <=s0;
ELSE
state <=s3;
END IF;
END CASE;
END IF;
END PROCESS;
Out_logic: PROCESS (state)
BEGIN
CASE state IS
WHEN s0=>
X<='1';
Y<='1';
WHEN s1=>
X<='0';
Y<='0';
WHEN s2=>
X<='1';
Y<='1';
WHEN s3=>
X<='1';
Y<='1';
END CASE;
END PROCESS;
END Behavioral;

Bi tp 4 : Thit k FSM m t hot ng ca n giao thng mt tr:

Yu cu:
Thi gian sng ca cc n nh sau:
n xanh: 12s

n vng: 3s n : 15s

Dng T Flip Flop chn Cl, Pr tch cc mc cao

Chn Reset ni vi nt nhn, khi nhn nt Reset th chu trnh bt u li t u vi n xanh

sng

Chn Stop ni vi cng tc, khi gt cng tc Stop th n sng

Bi lm

ta chn chu k T=3 giy

vy

f=

phn tch mch :

o nhn vo s khi ta thy mch c 3 ng ra : X,,V
o ta chn mt ng vo Reset : R
o ng stop ta s thit lp ti phn cng
tng thi gian ca mch l 30 giy m ta chn chu k T=3s s trng thi trong ca mch l 10
trng thi s T-FF cn chn l n
3.3 vy ta chn 4 T-FF.
hnh trng thi

R=X

0000
XV=100

R=0
R=1
0001
XV=100

1001
XV=001
R=1

R=1

R=0

R=0

1000
XV=001

0010
XV=100

R=1
R=1

R=0

R=0

R=1
R=1

R=1

0111
XV=001

0011
XV=100

R=0

R=0

0110
XV=001

0100
XV=010

R=0

0101
XV=001

R=0

 t hnh trng thi ta c bng trng thi sau :

Trng thi hin ti
R
0
0
0 0
0
0
0 0
0
0
0 1
0
0
0 1
0
0
1 0
0
0
1 0
0
0
1 1
0
0
1 1
0
1
0 0
0
1
0 0
1
0
0 0
1
0
0 0
1
0
0 1
1
0
0 1
1
0
1 0
1
0
1 0
1
0
1 1
1
0
1 1
1
1
0 0
1
1
0 0

Trng thi k
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0

0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0

0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0

Ng vo hi tip
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
1

0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0

0
1
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
1
0
0

Rt gn bng trng thi

T3

1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1

Ng ra
X V
1 0
1 0
1 0
1 0
0 1
0 0
0 0
0 0
0 0
0 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0

0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0

T2

T1

T0

Xanh :

X=R+
Vng :

V=

S thit k :

Bi tp 5 : Thit k FSM m t hot ng ca b m ln/xung ca s BCD 1 digit, hin th trn Led

7 on loi anode chung

Yu cu:
-

Dng T Flip Flop (Cl tch cc cao, Pr tch cc thp)

khi nhn nt Reset th led hin th s 0

khi S= 0 th b m m xung, khi S= 1 th b m m ln.

Thi gian sng ca cc s l 1 s

Bi gii
Phn tch mch
o Mch c 1 ng vo iu khin S
o Thi gian sng 1s f=1hz
o Mch m t 0 9 nn c 10 trng thi trong
o T-FF c Cl tch cc cao, Pr tch cc thp
hnh trng thi :

Bng trng thi

Trng thi hin ti

Trng thi k tip

Ng vo T-FF

S
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
Rt gn bng trng thi :

0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0

0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0

0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
0
0

0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0

0
1
0
1
0
1
0
1
0
0
0
0
1
0
1
0
1
0
1
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

S
thp
phn
0
1
2
3
4
5
6
7
8
9
0
9
8
7
6
5
4
3
2
1

T3 :

T2 :

T1:

T0:

=1

S mch thit k :