BI 1: TNG QUAN V PHN MM XILINX ISE 1.

MC CH Bi thc hnh nhm cung cp cho sinh vin cc kin thc v ngn ng m t phn cng VHDL, k E trong thit k dng vi mch lp trnh c. 2. TM TT L THUYT 2.1. Ngn ng m phng phn cng (HDL) 2.1.1. Cc phng php thit k truyn thng a. Phng php thit k dng hm Boolean Tt c cc mch da trn cc phn t logic c bn gm cng logic v cc mch flip-flop u c nhiu phng php c s dng ti thiu ho hm Boolean nhm tng tnh hiu qu s dn n. V mt l thuyt bt k h thng s no cng c th biu din di dng cc hm Boolean. hm logic r rng l khng thc t. Trong khi cc yu cu thit k h thng hin nay i hi

Hnh 1.1. Minh ho cho phng php thit k bng hm Boolean. b. Phng php thit k da trn s (l s m rng ca phng php thit k bng hm Boole Trong phng php ny, ngi thit k c th s dng thm cc mch chc nng thng dng khc . Nh vy, phng php ny cho php thit k thit k h thng mt cch c cu trc. Phng p phn mm thit k cung cp cho ngi thit k mt giao din thit k ho thun tin. Trong g ch yu trong ngnh cng nghip ch to phn cng s.

Hnh 1.2. Minh ho cho phng php thit k da trn s . c. Nhc im ca cc phng php thit k truyn thng Mc d c u im l d hiu v d s dng, phng php thit k dng hm Boolean v phng p hng php ny l chng ch m t h thng di dng mng cc phn t ni vi nhau. Nhn vo Boolean hay dng s ) ta khng th lp tc ch ra c cc ch tiu v chc nng chung nht php truyn thng, ngi thit k cn phi i qua hai bc thc hin hon ton th cng: sang biu din h thng bng hm Boolean, sau chuyn t hm Boolean sang s mch ca h h thng ngi phn tch cn phn tch s mch ca h thng chuyn n thnh cc hm Boole g. V cc bc ni trn hon ton phi thc hin th cng khng c bt k s tr gip no ca g c h tr trong vic v s mch ca h thng (dng cng c CAE Computer Aided Tool) v hp mch vt l (dng cng c Synthesis). Mt nhc im khc ca phng php thit k truyn thng l s gii hn trong phc tp c g thit k cc h thng ln nht biu din bi vi trm hm. Phng php da trn s ch 2.1.2. Ngn ng m phng phn cng (HDL) Ngn ng m phng phn cng gii quyt c nhc im ln nht ca cc phng php thit k ch tiu v chc nng ca h thng) sang tp hp cc hm logic bng tay th bc chuyn i g m phng phn cng. Hu ht cc cng c thit k dng ngn ng m phng phn cng u cho -machine) cho cc h thng tun t cng nh cho php s dng bng chn l cho h thng tng h thi v bng chn l sang m ngn ng m phng phn cng c thc hin t ng. Ngn ng m gic lp trnh c (PLD-Programmable Logic Device) t loi n gin n cc loi phc tp nh Programmable Gate Array). 2.2. Ngn ng m phng phn cng VHDL VHDL l vit tt ca cm t Very High Speed Intergrated Circuit Hardware Description Languag e-ngn ng m phng phn cng cho cc mch tch hp tc rt cao. VHDL l ngn ng m phng h VHSIC (Very High Speed Intergrated Circuit) ca b quc phng M. Mc tiu ca vic pht tr l c c mt ngn ng m phng phn cng tiu chun v thng nht cho php pht trin th n php d dng a cc h thng vo ng dng trong thc t. Ngn ngi VHDL c ba cng ty ents bt u nghin cu pht trin vo 7/1983. Phin bn u tin c cng b vo 8/1985. Sa mt tiu chun. Nm 1987, a ra tiu chun v VHDL tiu chun IEEE-1076-1987. VHDL c pht trin gii quyt cc kh khn trong vic pht trin, thay i v lp ti li g s c rt nhiu ti liu m t. c th vn hnh bo tr sa cha mt h thng ta cn tm vic xem xt cc ti liu m t tr nn d dng hn v b ti liu c th c thc thi cc phn t ca h thng hot ng trong mt m hnh thng nht. Trc khi VHDL ra i, c nhiu ngn ng m phng phn cng c s dng nhng khng c mt t cng c pht trin phc v cc b m phng chy chng. V cc ngn ng m phng phn gn vi cc thit b ca nh cung cp v thuc s hu ca nh cung cp. Trong khi , VHDL c pht trin nh mt ngn ng c lp khng gn vi bt k mt phng p . Ngi thit k c th t do la chn cng ngh, phng php thit k trong khi vn s dng VHDL c mt s u im hn hn cc ngn ng m phng phn cng khc l:

- Tnh cng cng - Kh nng h tr nhiu cng ngh v phng php thit k - c lp vi cng ngh - Kh nng m t m rng - Kh nng trao i kt qu - Kh nng h tr thit k mc ln v kh nng s dng li cc thit k 2.3. Cc cu trc c bn ca ngn ng VHDL Cc thnh phn chnh xy dng trong ngn ng VHDL c chia ra thnh nm nhm c b - Entity - Architecture - Package - Configuration. - Library.

Hnh 1.3. Cu trc code VHDL. Entity: Trong mt h thng s, thng thng c thit k theo mt s xp chng cc modul, m h thit k (c gi l Entity) trong VHDL. Mi mt Entity bao gm hai phn : - Khai bo thc th (Entity). - Thn kin trc (Architecture Bodies) Mt khai bo Entity c dng m t giao tip bn ngoi ca mt phn t (component), n ba cng u ra ca phn t . Phn thn ca kin trc c dng m t s thc hin bn trong Packages: Cc ng gi ch ra thng tin dng chung, m cc thng tin ny c s dng bi mt Configuration: nh cu hnh, n cho php gn kt cc th hin ca phn t cn dng no c hin ny vo trong cp Entity v Architecture. N cho php ngi thit k c th th nghim thay i cc s thc thi khc nhau trong mt o gm mt vi n v th vin, m mt trong cc th vin ny c dch sn v 2.3.1. Library Cc th vin thng s dng: - ieee.std_logic_1164 (from the ieee library), - standard (from the std library), and - work (work library). + + + std_logic_1164 Gi ca th vin IEEE h tr multi-level logic. std Gi th vin ti nguyn (kiu d liu, text IO) cho mi trng thit k VHDL. work Gi th vin cha cc thit k ca ngi dng mi to ra. Th vin IEEE: - std_logic_1164 + std_logic (8 mc logic),std_ulogic (9 mc logic) - std_logic_arith + Thc hin cc php ton s hc v so snh. - std_logic_signed +Thc hin cc php ton vi kiu DL std_logic_vector, d liu coi l c du - std_logic_unsigned + Thc hin cc php ton vi kiu DL std_logic_vector, d liu coi l khng du. 2.3.2. Entity ENTITY l danh sch c t ca cc cng vo ra (input/output pins) ca mch.

PORT l giao din ca mch vi cc mch bn ngoi khc, PORT thng l cc chn pin. - signal_mode: chiu truyn d liu + IN, OUT, INOUT (2chiu), BUFFER (khi tn hiu ra c dng cho cc tn hiu khc bn trong) Ch signal_mode cho bit chiu d liu c truyn nhn: IN D liu ch i vo ENTITY OUT D liu ch i ra khi ENTITY (v khng c s d INOUT D liu l hai chiu (i vo v ra) BUFFER D liu i ra khi ENTITY v cng c a quay tr li vo trong

- signal_type: + bit, std_logic, integer - Port_name: + t tn theo quy tc t tn chun, trnh cc t kha. V d: 2.3.3. Achitecture Phn ARCHITECTURE m t mch hot ng nh th no.

Mt ARCHITECTURE lun gn vi mt ENTITY v m t hot ng ca ENTITY . Mt ARCHITECTURE ch gn vi mt ENTITY nhng mt ENTIY c th c nhiu ARCHITECTURE khc nha - ARCHITECTURE c hai phn: + Phn khai bo (optional): Khai bo tn hiu v bin. + Phn m code: M t cch kt ni, hot ng ca mch. V d v mch NAND:

2.4. Mi trng phn mm tch hp ISE 2.4.1 Phng php phn chia h thng TOP-DOWN DESIGN y l phng php dng trong thit k, c cc cng c ca Xilinx h tr. i vi nhng h ng m phi phn chia ra nhiu thnh phn v theo tng cp khc nhau gi l qu trnh top-down Top-down design l phng php phn chia nhiu ln ca h thng thnh nhng thnh phn con ch con ny c th qun l c. Mt thnh phn c th qun l c nu n c sn trong th vi c th c m t bng chng trnh tng hp c vit bi ngi thit k hoc mt phn cng Sau khi tin hnh phn cp h thng thit k th ngi thit k thc hin nh x vo phn c g ngh cui cng, th vin v cng ngh sn c. i vi nhng h thng c th lp trnh c, lle lp trnh thit b gi l Design Fille. Mt phn mm c trang b nhng cng c tt v t hn v h thng c nhng thnh phn n gin hn, d dng cho vic thit k. 2.4.2 M t khi qut v ISE ISE (Integrate Software Environment)- mi trng phn mm tch hp- l mt b phn mm thit ii hn ng dng rt rng t nhng thit k ban u vi CPLD n nhng th nghim thit k v GA. ISE cho php to ra cc sn phm thit k thng qua vic nhp cc thit k vo thit b c ISE cho php c th la chn mt hoc nhiu phng n thit k khc nhau bao gm: + Thit k bng ngn ng m t phn cng HDL (VHDL,Verilog HDL, ABEL) + Thit k di dng s cng Logic (Schematic) + EDIF (Electronic Data Interchange Format) + NGC/NGO (kt hp vi Core Gerenator) + hnh trng thi (State Machines) + IP codes Vi mi phng n thit k, c mt fille ngun, ISE cho php nhanh chng xc minh chc nng c nng m phng tch hp bn trong, bao gm MODELSIM v HDL Bench. Vi phng n thit k bng ) thit k c tng hp bng cng ngh tng hp ca Xilinx (XST), n c th l mt phn mm t phin bn ISE 6.1 tch hp cc cng c tng hp). Cng c thc hin thit k tip tc q trong CPLD v kt thc ca qu trnh mt dng bit c hnh thnh cu hnh nn thit k ca ator cung cp mt ci nhn ton din ton b qu trnh thit k. Cc giai on thit k s dng ISE: Cc giai on thit k s dng ISE trn cng ngh FPGA hoc CPLD tng i ging nhau v bao b cng c cn thit to ra nhng thit k t n gin n phc tp v m bo thit k VHDL, Verilog) hay s (Schematic) hoc trong vi trng hp n l mt s pha trn gia s to mt thit k trong ISE (i vi c CPLD v FPGA), ngi thit k phi tri qua cc b 1. To mt d n mi (New Project) hoc m mt d n c. 2. To v thm file vo trong d n. 3. To cc file Constraints (UCF) - cc quy tc v s rng buc trong thit k. 4. a vo cc rng buc (quy tc) nh s nh thi, quy tc gn chn, v nh cc vng. 5. La chn cc thuc tnh tng hp v thc hin thit k. 6. M phng thit k: vic m phng c th thc hin trc khi tng hp (m phng theo hnh v phng theo vic nh thi) 7. Thc hin thit k: Thit k s c tng hp (nu n cha thc hin vic ny) v thc thi ap), sp t v kt ni (Plane & Route). 8. Xem li nhng bo co ca vic dch, nh x, sp t v kt ni.

9. Thay i nhng thuc tnh, rng buc... v tip tc thc hin thit k. Lp li cho n kh 10. Xem s sp t thit k trong FloorPlanner, c th dng tay t v nhm li trt t logi Floorplanner 11. Xem s sp t v kt ni thit k trong FPGA Editor (i vi trng hp thit k FPGA), ng cc mc thit k bng FPGA Editor 12. To mt file chng trnh (.bit) cu hnh cho thit b. 13. To mt PROM, ACE, hoc file JTAG g ri hoc ti xung thit b. 14. S dng cng c IMPACT np chng trnh cho thit b vi mt cp lp trnh. Tuy mt thit k trn ISE phi tri qua rt nhiu bc nhng tt c c chnh cc cng c hng qu phc tp c th khng cn phi thc hin vic sp t v kt ni bng tay trn Floor trc tip n nh s rng buc trong thit k - tt c c ISE t ng gii quyt mt c III. NI DUNG TH NGHIM thy c mt cch trc quan vic s dng phn mm ISE trong thit k cc bo mch in t gin, trong v d ny chng ta s thit k mt b m 4 bit, 2 chiu. thit k mt bo mch bt k trc ht ngi thit k phi bit mc ch ca vic thit k, it k. T hnh thnh thut ton thit k. Vi vic thit k b m 4 bit, 2 chiu, trc ht phi hiu qu trnh m ca b m l qu rng thi trong ca b m c m ho bng m nh phn. Mt b m 2 chiu l b m c th m ln t mt s cho trc hoc m li t s . Cc - CKL: Xung ng b; - DIRECTION u vo cho php m ln (tch cc mc cao, sn dng xung Clock) hoc m xu ck); - Q<3> - Q<0>: nhng u ra ca b m. Qu trnh m ca b m c th c m t nh sau: b m ch lm vic khi c xung ng h ( vic m ln hay. 3.1. Quy trnh thit k FPGA s dng phn mm Xilinx ISE Khi ng chng trnh XILINX ISE, to mt Project mi chng ta tin hnh cc bc nh sau New Project Xut hin hp thoi New Project Wizard. 1. Vo menu File 2. G tn ca project vo Project Name, chng hn SimpleCounter 3. Trong mc Project Location chng ta chn v tr lu project; 4. Trong mc Top-Level Source chng ta chn HDL. 5. Click Next chuyn n hp thoi la chn thit b 6. Khi hp thoi xut hin, chng ta la chn nh sau: Product Category: All Family: Spartan3 Device: XC3S200 Package: FT256 Speed Grade: -4 Top-Level Module Type: HDL Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator (VHDL/Verilog) Chn mc Enable Enhanced Design Summary. Sau khi chn cc thng s, chng ta c kt qu nh sau:

Hnh 1.4: Hp thoi Device Properties. 7. Click Next tip tc n hp thoi Create New Source nhm to m ngun cho thit k. Xu Hnh 1.5: Hp thoi Create New Source. 8. Click the New Source trong hp thoi New Project Wizard 9. Chn VHDL Module 10. Trong trng File name g Counter 11. Chn checkbox Add to project 12. Click Next. Kt qu nh sau: Hnh 1.6: Hp thoi Select Source Type. Xut hin hp thoi Define Module, chng ta cu hnh cc thng s nh sau: Hnh 1.7: Hp thoi Define Module. 13. Click Next Finish kt thc qu trnh to m ngun mi;

14. Click Next,

Next,

Finish khi xut hin ca s Project mi nh sau:

Hnh 1.8: Chng trnh chnh vi Project mi. La chn file Counter.vhd trong tab Source chng ta c mi trng son tho ngn ng VHDL vi nh sau:

Hnh 1.9: Chng trnh chnh vi file VHDL c to sn. Cn c vo chc nng ca b m cn xy dng chng ta tin hnh lp trnh dng ngn ng VHDL. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitive in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter is Port ( CLOCK : in STD_LOGIC; DIRECTION : in STD_LOGIC; COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); end counter; architecture Behavioral of counter is signal count_int : std_logic_vector(3 downto 0) := "0000"; begin process (CLOCK) begin if CLOCK='1' and CLOCK'event then if DIRECTION='1' then count_int <= count_int + 1; else count_int <= count_int - 1; end if; end if; end process; COUNT_OUT <= count_int; end Behavioral; 15. Lu li file VHDL va son tho, vo File Save Sau ta tin hnh kim tra thit k va c to ra. 16. Trong tab Source chn Synthesis/Implementation Hnh 1.10: Tab Source 17. Trong tab Process chn Synthesize-XST (click vo du +) it k:

nhy p vo Check Syntax ki

Hnh 1.11: Tab Process. Nu chng trnh khng bo li (ti tab Error) th kt thc qu trnh son tho, nu xy ra l u trnh son tho thit k n khi khng cn li c php. Khi ti v tr Check Syntax xu Khi c th xem s nguyn l RTL ca thit k.

Hnh 1.12: RTL Schematic. xem cc mc thit k thp hn chng ta bm vo s nguyn l c to ra t qu trnh t 3.2. M phng thit k Chng ta tin hnh m phng thit k qua cc bc sau: 1. Chn file Counter.hdl trong ca s Sources. 2. to file m phng, vo Project New Source. 3. Trong ca s New Source Wizard, chn Test Bench WaveForm v t tn counter_tbw 4. Click Next Next Finish. 5. Hp thoi Initialize Timing xut hin cho php thit lp cc thng s dnh cho qu trnh m B m phi hot ng mt cch chnh xc vi mt tn s xung CLOCK u vo = 25 MHz.

u vo DIRECTION s c gi tr 10 ns trc khi c cnh ln ca CLOCK. u ra (COUNT_OUT) phi c gi tr 10 ns sau khi c cnh ln ca CLOCK. Cc thng s s c thit lp nh sau: Clock Time High: 20 ns. Clock Time Low: 20 ns. Input Setup Time: 10 ns. Output Valid Delay: 10 ns. Offset: 0 ns. Global Signals: GSR (FPGA) Ch : khi GSR(FPGA) c cho php gi tr Offset s c t ng gn gi tr. Initial Length of Test Bench: 1500 ns. Hnh 1.13: Hp thoi Initialize Timing. Click Finish. - Xut hin ca s Test Bench WaveForm: Hnh 1.14: Hp thoi Test Bench WaveForm. - i vi xung DIRECTION: + Click vo thi im 300ns t xung DIRECTION ln mc cao + Click vo thi im 900ns t xung DIRECTION xung mc thp. - Lu li dng sng File Save. 6. Trong ca s Sources chn Behavioral Simulation: Hnh 1.15: Behavioral Simulation. Chn file counter_tbw trong ca s Sources 7. Trong tab Process, click vo du + ti mc Xilinx ISE Simulator process v double-click Generate Expected Simulation Results process. 8. Hp thoi Expected Results xut hin. Chn Yes thy kt qu ca qu trnh m phng.

Hnh 1.16. Kt qu m phng. 3. Bi tp thc hnh 3.1. Gii thch dng sng thu c sau khi qu trnh m phng. 3.2. To project mi, thit k v m phng thit k b m Johnson 4 bit, 2 chiu, c lnh i Vi vic thit k b m Johnson 4 bit, 2 chiu, c lnh iu khin dng, trc ht phi hiu g thi ny n trng thi khc v mi trng thi trong ca b m c m ho bng m Johnson - Nu dng 2 bin nh phn th s m ho c ti a l 2n trng thi. - Hai t m gn nhau ch khc nhau mt bin. A B C D 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1

1 0 1 1 1 0 0 1 1 0 0 0 1 Hnh trn l bng m Johnson cho 4 bin nh phn: (quy c A l bt c trng s nh n Mt b m 2 chiu l b m c th m ln t mt s cho trc hoc m li t s . Cc u vo, ra: - CKL: Xung ng b - LEFT: u vo cho php dch tri (m ln)- tch cc mc thp. - RIGHT: u vo cho php dch phi (m li)- tch cc mc thp - STOP: u vo cho php dng s m- tch cc mc thp. - Q<3>- Q<0>: nhng u ra ca b m. Qu trnh m ca b m c th c m t nh sau: b m ch lm vic khi c xung ng h ( cc mc thp) s bt u thc hin vic m ln hay xung (dch tri hay phi). Khi c xun g vic m v ch tip tc khi c xung LEFT hay RIGHT tc ng . ________________

BI 2: LP TRNH VHDL VI CC PHT BIU TUN T 1. MC CH Bi thc hnh nhm cung cp cho sinh vin cc kin thc v ngn ng m t phn cng VHDL, k E trong thit k dng vi mch lp trnh c. 2. TM TT L THUYT 2.1. Cc pht biu tun t Pht biu tun t ch ra s thc hin tng bc ca mt qu trnh. Chng thc h i, ... cu lnh cui cng. Cc pht biu nm trong mt pht biu qu trnh (Pht biu Process pht biu sau y l cc pht biu tun t c nh ngha trong VHDL: 2.2. Pht biu gn bin Dng thay th gi tr hin thi ca bin vi mt gi tr mi, gi tr mi ny c ch ra ng mt pht biu qu trnh hay cn c gi l pht biu Process. Mt bin c gn mt gi biu ny c hnh thc nh sau: target_variable : = expression; Lu cc bin c khai bo trong mt Process khng th chuyn gi tr ra ngoi Process, i ong Process hoc trong chng trnh con. 2.3. Pht biu gn tn hiu Pht biu gn tn hiu s thay th gi tr hin ti ca tn hiu vi mt gi tr mi bi vic Tn hiu v kt qu ca biu thc cn c cng mt kiu d liu. C php ca chng nh sau: target_signal <= [ Transport] expression [after time_expression] Pht biu gn tn hiu c th xut hin bn trong hoc bn ngoi mt qu trnh. Nu n xy ra pht biu gn tn hiu ng thi. Khi pht biu gn tn hiu xut hin bn trong qu trnh, n c xem nh l mt pht biu g o th t ca nhng pht biu tun t khc xut hin bn trong qu trnh. 2.4. Cc pht biu IF Mt pht biu if c dng chn la nhng pht biu tun t cho vic thc thi da trn gi l mt biu thc bt k m gi tr ca chng phi l kiu lun l. Dng thng thng ca pht biu if l: if boolean-expression then sequential-statements {elsif boolean-expression then sequential -statement }

{else sequential-statement} enf if; 25. Pht biu CASE Dng ca pht biu case l: case expression is when choices => sequential -statement -- branch 1 when choices => sequential -statement -- branch 2 -- -- C th c nhiu nhnh {when others => sequential-statement} -- last branch end case; Pht biu case la chn mt trong nhng nhnh cho vic thc thi da trn gi tr ca biu th uc kiu ri rc hoc kiu mng mt chiu. Cc chn la (Choices) c th c din t nh mt " | " hoc s dng mnh khc. Tt c cc gi tr c th c ca biu thc phi c th hi dng bao qut tt c cc gi tr, v nu c, phi l nhnh cui cng trong pht biu c vi kiu ca biu thc. 2.6. Pht biu NULL L mt pht biu tun t khng gy ra bt k hnh ng no; H thng s b qua pht biu NULL Mt th d cho vic s dng pht biu ny l trong pht biu if hoc trong pht biu case. V d : Variable A, B : INTEGER range 0 to 31 ; Case A is when 0 to 12 => B:= A; when others => Null; End Case; 2.7. Pht biu Loop Mt pht biu lp c s dng lp li mt lot cc cu lnh tun t. C php ca pht bi [loop-label:] iteration-scheme loop sequential-statements end loop [loop-lebel]; C 3 kiu s lp. u tin l s lp c dng: for identifier in range V d 1: V d v For ...Loop FACTORAL:=1; for NUMBER in 2 to N loop FACTORAL :=FACTORAL*NUMBER; enf loop; Trong th d ny, thn ca vng lp thc thi N-1 ln, vi nh danh lp l NUMBER v tng ln ER c khai bo n trong vng lp ty thuc vo kiu integer, n c gi tr t 2 n N. V h vng lp l iu cn thit, nh danh vng lp cng khng th c gn cho bt k gi tr n tn c to bn ngoi vng lp for, l hai loi bin c gii quyt ring r v bin s anh vng lp. Vng ca vng lp FOR cng c th l vng ca mt kiu lit k. V d 2: type HEXA is (0,1,2,3,A,B,C ); . . . . for NUM in HEXA(2) downto HEXA(0) loop -- Num s ly nhng gi tr trong kiu HEXA t 2 cho n 0. end loop; V d 3: V d v While .... loop process variable Count : interger := 0; begin wait until Clk = 1; while level = 1 loop Count := Count +1; wait until Clk = 0; end loop; end process; 2.8. Pht biu Next Pht biu next cng l pht biu lin tc cng ch c th s dng bn trong vng lp. C php next [loop-label][when condition]; Kt qu ca pht biu next s b qua nhng pht biu cn li trong ln lp hin ti ca vng tin trong vng lp k tip. Nu tn ti mt ln v nu nhn vng lp khng r rng th s x xit, n l nguyn nhn ca vng lp b gii hn.

V d 1: for j in 10 downto 5 loop if SUM < TOTAL_SUM then SUM:=SUM +2; elsif SUM:= TOTAL_SUM then next; else null; end if; K:=K+1; end loop; Khi pht biu next c thc thi, qu trnh thc hin s nhy n phn cui ca vng lp (ph gi tr ca nh danh vng lp j, v thc hin li t u. 2.9. Pht biu EXIT Pht biu exit l mt pht biu tun t n ch c th s dng bn trong vng lp. N c th l ong cng hoc ra khi vng n v tr ca nhn xc nh no khi n gp nhn ny trong vn exit [loop-label][when condition] Nu nhn vng lp khng c ch ra th qu trnh thc hin s lp n vng lp trong cng. xy ra nu iu kin l ng. Ngc li, vic thc hin s tip tc vi pht biu k tip. V d : SUM :=1; J:=0 ; L3:loop J:=J+21; SUM:=SUM*10 if (SUM >100) then exit L3; -- Thc hin exit khi L3 nu Sum> 100 enf if; end loop L3; 2.10. Pht biu WAIT Nh chng ta thy, mt qu trnh m phng c th tr hon (Hay treo s thc hin ca mt p con) cho n khi gp mt iu kin ph hp. C 3 hnh thc c bn ca pht biu wait. wait on sensitivity-list; wait until boolean -expression; wait for time-expression; V d 1: wait on A,B ; wait until A = B; wait for 10 ns; wait on CLOCK for 20 ns ; wait until SUM >100 for 50 ms; S hin din ca sensitivity list trong mt qu trnh trng vi trng hp mt trong ba trn t. Mt pht biu qu trnh c wait on cui ca Process tng ng vi mt pht biu qu t . Xem hnh di y: Hai process ny l tng ng nhau. process begin somestatements1; somestatements2; somestatements3; wait on SomeSign; end process; SomeSign process begin somestatements1; somestatements2; somestatements3;

end process; V d 2 : process -- Khng sensitivity list variable TEMP1, TEMP2:BIT; begin TEMP1:=A and B; TEMP2:=C and D; TEMP1:=TEMP1 or TEMP2; Z<=not TEMP1; wait on A, B, C, D; -- Thay th cho sensitivity-list u Process . end process. 2.11. Cc li gi chng trnh con Khi m t thit k theo kiu hot ng hnh vi, cc chng trnh con thng hay c s dn i loi chng trnh con hay c s dng l Hm v Th tc. - Th tc (Procedure) tr v nhiu gi tr. - Hm (Function) tr v mt gi tr n. Cc li gi th tc s gi th tc m n cn c thc hin trong mt qu trnh. Pht biu t con, v n ch c s dng trong mt hm hoc mt th tc. i vi hm th n c qui nh v h c th s dng tu trong thn th tc. C php ca pht biu tr v nh sau: return [expression]; y expression s a ra cc gi tr tr v ca hm, pht biu return trong mt hm cn ph g i vi pht biu tr v trong th tc th khng cn phi c mt ca biu thc. Mt hm c ng ch c mt pht biu tr v c s dng bi mt li gi hm. 3. NI DUNG THC HNH 3.1. Thc hin b cng ton phn Full Adder Hnh 3.1. B cng ton phn Full Adder. - Lp mt project mi trong Xilinx ISE vi tn gi l Full_Adder - Thc hin m t b cng ton phn Full Adder vi 3 dng: + M t di dng cu trc (STRUCTURE): library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FullAdder is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; SUM : out STD_LOGIC; CARRY : out STD_LOGIC); end FullAdder; architecture Structure of FullAdder is Component XOR2 Port (I0,I1 : in STD_LOGIC; O: out STD_LOGIC); End Component; Component AND2 Port (I0,I1 : in STD_LOGIC; O: out STD_LOGIC); End Component; Component OR3 Port (I0,I1,I2 : in STD_LOGIC; O: out STD_LOGIC); End Component; Signal S1,T1,T2,T3 : STD_LOGIC; begin U1: XOR2 Port map (A,B,S1); U2: XOR2 Port map (Cin,S1,SUM); U3: AND2 Port map (A,B,T1); U4: AND2 Port map (A,Cin,T2);

U5: AND2 Port map (Cin,B,T3); U6: OR3 Port map (T1,T2,T3,CARRY); end Structure; + M t di dng dng d liu (DATA FLOW): library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FullAdder is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; SUM : out STD_LOGIC; CARRY : out STD_LOGIC); end FullAdder; architecture Data_Flow of FullAdder is begin SUM <= A XOR B XOR Cin; CARRY <= (A AND B) OR (B AND Cin) OR (A AND Cin); end Data_Flow; + M t di dng hnh vi (BEHAVIORA): library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FullAdder is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; SUM : out STD_LOGIC; CARRY : out STD_LOGIC); end FullAdder; architecture Behavioral of FullAdder is begin Process (A,B,Cin) Begin SUM <= A XOR B XOR Cin; CARRY <= (A AND B) OR (B AND Cin) OR (A AND Cin); End Process; end Behavioral; Bi tp: Xy dng b cng ton phn Full Adder da trn cc b bn tng Half Adder; 3.2. Mch gii m a ch, phn knh, ghp knh Xy dng mch gii m a ch 2:4 vi bng chn l nh sau: CONTROL LINES OUTPUT LINES

A B Y0 Y1 Y2 Y3 0

0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Decoder_2to4 is Port ( Din : in STD_LOGIC_VECTOR (1 downto 0); Dout : out STD_LOGIC_VECTOR (3 downto 0)); end Decoder_2to4; architecture Behavioral of Decoder_2to4 is begin Process (Din) Begin CASE (Din) is When "00" => Dout <= "0001"; When "01" => Dout <= "0010"; When "10" => Dout <= "0100"; When Others => Dout <= "1000"; End Case; End Process; end Behavioral; Bi tp: - Thit k b gii m 3:8; - Thit k b gii m BCD sang m 7 thanh (dng LED 7 thanh chung Cathode hoc chung Anode). ________________

BI 3: THIT K CC MCH T HP THNG DNG 1. MC CH Bi thc hnh nhm cung cp cho sinh vin cc kin thc v s dng ngn ng m t phn cng V ic t hp. 2. TM TT L THUYT Mch logic t hp (Combinational logic circuit) l mch m gi tr t hp tn hiu ra ti mt gi tr t hp tn hiu vo ti thi im . Hiu mt cch khc mch t hp khng c trng t hin logic chc nng nh AND, OR, NOT i vi mch t hp tham s thi gian tr Tdelay l khong thi gian ln nht k t thi im tt c cc kt qu u ra tr nn n nh. Trn thc t vi vi mch tch hp vic thi gian

bng cch lit k tt c cc ng bin i tn hiu c th t tt c cc u vo ti tt c h tnh c tr ca cc ng truyn ny v tm ra ng truyn c tr ln nht, gi t

Hnh 3.1. tr ca mch t hp. Minh ha cho tr trong mch t hp nh hnh 3.1. V l thuyt xc nh tr ca mc In3, In4 n 2 u ra Out1, Out2. i vi mi cp u ra u vo tn ti nhiu ng truyn k ln. Chnh v th i vi nhng mch t hp ln th vic xc nh tr u phi thc hin V d xc nh tr ca hai ng truyn 1 v 2 trn hnh v: ng 1 ln lt i qua c a cng NOT, AND, OR_4, AND_4, OR_4. tr ca cc ng truyn ny tnh bng tr ca cc ite). T1 = TNOT + TAND_4 + TNOR + TAND_3 + T AND_3 + TWire1 (1.1) T2 = TNOT + TAND + TOR_4 + TAND_4 + T OR_4 + TWire2 (1.2) Do tr ca cng nhiu u vo ln hn tr ca cng t u vo nn mc d s cng i qua truyn c tr ln nht c gi l Critical paths. Cc ng truyn ny cn c bit quan 3. NI DUNG THC HNH 3.1. Thc hin b cng ton phn Full Adder da trn b cng bn tng: Hnh 3.1. B cng ton phn Full Adder da trn b cng bn tng Half Adder. 3.2. Thc hin gii m a ch