Microprocessors and Instruction Sets 80286 Microprocessor ............. Real-Address Mode .......... Protected Virtual Address Mode 80287 Math Coprocessor Programming Interface Hardware Interface ...... 80386 Microprocessor Baia Real Address Mode ......... Protected Virtual Address Mode Virtual 8086 Mode ........ 80386 Paging Mechanism 80387 Math Coprocessor .......... ce res | 80387 To 80486 Math Coprocessor Compatibility aH Beer OVAATAYONN= Programming Interface 10 Hardware Interface 1 | 80486 Microprocessor ...... 13 | Cache Control ...... 13 | Cache Paging Control 14 | Page Protection Feature . . yee aaa | New Alignment Check ........ : f 7 BG: MMR MURR NIE aes fee eee 80286 Microprocessor Instruction Set . . 7 Data Transfer sees 7 Arithmetic : 21 ONG sere 2 String Manipulation 27 Control Transfer peat 29 Processor Control ........ 33 Protection Control 35 80287 Math Coprocessor Instruction’ Set 38 DataTransfer ......... 38 Comparison 40 Constants a Arithmetic . 42 Transcendental . . 43 Processor Control .. . 44 Introduction to the 80386 Instruction 's 45 Code and Data Segment Descriptors it é oe. 46 Iie ees tee ee elder eesre teeter eee eer seeeee A Instruction Format ............ PALE ebereesH ed ueeaieaieeesetC 48 Encoding Ie seeesee des ee eeee CH ee cH cE Eeee sees et ee erg eet ete 50 paddress: Modeliscesee cimicier crc aerate 50 © Copyright IBM Corp. 1990 'Operand Length (w) Field ............... 00.00.0005 53 Segment Register (sreg) Field 54 General Register (reg) Field ................... 54 Operation Direction (d) Field .... 55 Sign-Extend (s) Field .......... desea 55 Conditional Test (tttn) Field .............2... 55 Control, Debug, or Test Register (eee) Field Eee ree 56 80386 Microprocessor Instruction Set . . ... 57 Data Transfer ....... cee 57 Segment Control 60 Flag Control 61 Arithmetic 62 Logic tee 67 String Manipulation . . : aii Cee 71 Repeated String Manipulation eee eee 72 Bit Manipulation ..... ee ‘ 74 Control Transfer 75 Conditional Jumps 76 Conditional Byte Set 81 Interrupt Instructions 83 Processor Control 84 Processor Extension 85 Prefix Bytes epee See sec sese eee da cee BD Protection Control ........... Serer eee eter 86 Introduction to the 80387 InstructionSet ............ ... 89 80387 Usage of the Scale-Index-Base ee sane eee Instruction and Data Pointers ae 89 New Instructions ...... 92 80387 Math Coprocessor Instruction ‘ Set . 93 Data Transfer 2 93 Comparison 94 Constants 95 Arithmetic eee : Pee erate 96 Transcendental .... eerie seer 98 Processor Control; 30a eee 98 80486 Microprocessor InstructionSet ........... 7 100 il Microprocessors and Instruction Sets - October 1990Figures 1. 80287 Data Types 2. 80386 Addressing Eee ‘ Eels OM ECM eect Eee 4. Data Type Classifications and Instructions 5. 80387 DataTypes ........... 6. ay 7, 8. 9. Control RegisterO ...... 80386 Compatible Operation 80486 Protection Operation . . . 2-Bit Register Field 10. 3-Bit Register Field at te 11. 80287 Encoding Fieid Summary. ine BEE 12. 80386 Code and Data Segment Descriptor Format 13. Instruction Format ........-........... 7 14. 80386 Instruction Set Encoding Field Summary 15. Effective Address (16-Bit and 32-Bit Address Modes) 16. Scale Factor (s-i-b Byte Present) ........ 17. Index Registers (s-i-b Byte Present) 18. Base Registers (s-i-b Byte Present) 19. Effective Address (32-Bit Address Mode — Rem tsetse eeeeeeee gee eee 20. Operand Length Field Encoding 21. Segment Register Field Encoding 22. General Register Field Encoding 23. Operand Direction Field Encoding 24. Sign-Extend Field Encoding ..... eee 25. Conditional Test Field Encoding ........ eee 26. Control, Debug, and Test Register Field Encoding ~ eerie 27. 80387 Encoding Field Summary . 28. Instruction and Pointer Image (16-Bit Real Address Mode) 29. Instruction and Pointer Image (16-Bit Protected Mode) ... 30. Instruction and Pointer Image (32-Bit Real Address Mode) 31. Instruction and Pointer Image (32-Bit Protected Mode) © Copyright IBM Corp. 1990