EXPERIMENT NO.

2
Transmission Gate

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all;

entity transmision_gate is Port ( p_gate,n_gate,source : in std_logic; drain : out std_logic); end transmision_gate;

architecture Behavioral of transmision_gate is

begin

process(p_gate,n_gate,source) begin if( p_gate='0' and n_gate='1')then drain<= source;

elsif( p_gate='1' and n_gate='0')then drain<= 'Z'; else drain<= 'X'; end if;

end process;

end Behavioral;