[Total No.

of Questions: 12]

[Total No. of Printed Pages: 2]

UNIVERSITY OF PUNE [4364]-113 B. E. (Electrical) Examination - 2013 VLSI Design (2003 Course) [Time: 3 Hours] Instruction: 1) 2) 3) 4) 5) [Max. Marks: 100]

Answer any 3 questions from each Section Answers to the two sections should be written in separate answer-books. Neat diagrams must be drawn wherever necessary. Figures to the right indicate full marks. Use of logarithmic tables, slide rule, Mollier charts, electronic pocket calculator and steam tables is allowed. 6) Assume suitable data, if necessary.

Q.1 Q.2

A A

SECTION -I Explain the EDA tool Design flow in Detail alongwith flow-chart of each stage. OR Draw and explain Mealy and Moore Modelling used for design of digital circuits using any one example with state diagram, state table, analysis & Designed circuit. Which are the various HDLs available example the salient features of HDL Design basic gates using suitable Multiplexer. OR Differentiate between HDL? High level language. Design 16:1 MUX using only 4:1 MUX also explain its truth table. Differentiate between sequential & combinational circuit with example. Draw circuit & timing diagram of 3bit synchronous up counter & explain the same. OR Draw and explain 4 bit universal shift register. Draw state diagram of 10101 Detector use Mealy Modelling.
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18 18

Q. 3

A B

8 8 8 8 8 8 8 8

Q. 4 Q. 5

A B A B A B

Q. 6

Q. 7 Q. 8 Q. 9

A A A B

SECTION II Explain various Modelling types used in VHDL coding. OR Which are the various Data types and Data objects in VHDL? Explain. What is sub-program overloading? Explain with example. What is configuration? Explain with one VHDL example. OR What is component? How it is used in programming? give example & explain What is the Difference between simulation and Synthesis? Explain Write VHDL Code for 2 x 4 decoder Write VHDL code for 8 x 8 RAM OR Write VHDL code for 4 bit ALU Write VHDL code for 16:1 MUX

18 18 8 8 8 8 8 8 8 8

Q. 10 A B Q. 11 A B Q. 12 A B

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