ChiaTien DanLo DepartmentofComputerScienceandSoftware Engineering SouthernPolytechnicStateUniversity

AdvantageofUsingVHDL
y Industrialstandard(IEEE1076) y Portabilityofdesignsandknowledge y Hierarchyindesigndescription y Technology(implementation)independence y CodeReusability y ParameterizedDesign y (Thelistdoesnotendhere!)

BasicConcepts
y VHDLisstronglytyped y VHDLallowsuserdefinedtypes y VHDLiscaseinsensitiveandfreeformat y Commentsarespecifiedbytwoconsecutivedashes()

Example
entityMyAnd2is port(a,b:inbit; c:outbit ); endMyAnd2; specifyentitynamebyconvention specifyin/out/inout ports no;here endedby; endentityspecification behaviorspec starthere dataflow endhere

architecturedataflowofMyAnd2is Begin c<=aandb; enddataflow;

Entity
y BITisapredefinedtype;itisanenumerationtype

containingthecharacterliterals0and1.Std_logic on theotherhandmaycontainzforexample. y TheINandOUTspecifythemodeoftheportsignals. AsignalwithmodeINcannotbeassignedavaluefrom withinthecomponent.AnOUTsignalcannotbeused ontherighthandsideofasignalassignment.Inout willprovidebothdirectionI/Os.

Architecture
Thearchitecturebodycanbeusedforthefollowing modelingstyles:
y Asasetofconcurrentassignments(torepresent

dataflow), y Asasetofinterconnectedcomponents(torepresent structure) y Asasetofsequentialassignmentstatements(to representbehavior), y Anycombinationoftheabovethree.

DataflowDesc inVHDL
y Inadigitalsystem,variousformsofhardware

structureareusedfortheselectionandplacementof dataintobusesorregisters. y ConcurrentsignalassignmentstatementsinVHDLcan beusedtodirectthedataflowinhardware. y TheConcurrentsignalassignmentstatementsare:

y simplesignalassignment y selectedsignalassignment y conditionalsignalassignment

SimpleSignalAssignment
y E.g.,c<=aandb; y c :targetsignal y a,b:sourcesignals y <=:signalassignmentoperator y Thesixlogicaloperatorsare: y ANDORNANDNORXORNOT

SelectedSignalAssignment
y Theselectedsignalassignmentstatementismuchlike

acasestatement.However,aselectedsignal assignmentstatementisaconcurrentsignalwhilea casestatementisasequentialstatement. y Note,theprocesscancontainsequentialstatements only.

SelectedSignalAssignment(Syn)
Thesyntaxis: WITHexpressionSELECT target<=waveformWHENchoice, waveformWHENchoice, ... ...;

2to1Multiplexer
entityMux21is port(a,b,sel :inbit; y:outbit ); endMux21; architecturedataflowofMux21is begin withsel select ys outputisbasedonsel y<=awhen1, bwhen0; enddataflow;

BitVector
y Severalbitscanbeaggregatedtofromabitvector y E.g.,myBitVector:inbit_vector(7downto 0); y Eachofthebitscanbeaccessedbybit_vector[i]to

easydesignthatneedtodealwithonebyteinputfor example y Thereisacorrespondingstd_logic_vector defined.

ConditionalSignalAssignment
y Conditionalsignalassignmentstatementslistaseries

ofexpressionsthatareassignedtoatargetsignalafter thepositiveevaluationofonemoreBoolean expressions. y Anexamplewillbeshowninthenextslide.

41Multiplexer
entityMux41is port(data:inbit_vector(3down0); sel:inintegerrange0to3; f:outbit ); endMux41; architecturedataflowofMux41is begin f<= data(0)whensel =0else data(1)whensel =1else data(2)whensel =2else data(3); enddataflow;

Process
y AprocessinVHDLisusedtomodelbothsequentialand y y y y

combinationallogics. Ithasadeclarativepart(betweenthekeywordPROCESSand BEGIN),andastatementpart(betweenthekeywordBEGINand ENDPROCESS). Theprocessstatementisinvokedwheneverthereisaneventon anysignalinthesensitivitylist. Aprocesscontainssequentialstatementsonly. Processescommunicationeachotherwithsignals.

process(A,B,enable) variable...:bit; begin ... endprocess;

IfThanElseinProcess
y Equivalenttoconditionalstatementbutitis

sequentialstatement y Processitselfisaconcurrentstatementandcontains onlysequentialstatements. y Exampleisnext.

ConditionalSignalSelectionin Process CombinationalLogic

entityMux41is port(data:inbit_vector(3downto 0); sel:inintegerrange0to3; f:outbit ); endMux41;

architecturedataflowofMux41is begin process(data,sel,f) begin

if(sel =0)then f<=data(0); elsif (sel =1)then f<=data(1); elsif (sel =2)then f<=data(2); else f<=data(3);

endif; endprocess; enddataflow;

SequentialLogic
process(clk,clr) begin ifclr =1then reset q<=0; elsif clkevent andclk =1then q<=d; endif;makesureplaceendifhere endprocess;