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  • DAFSH

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    Yaniv Avrahami
    6 views2 pages
    The document describes various logic gates and components, including their truth tables. It covers basic gates like AND, OR, NAND, NOR, XOR and XNOR. It also covers multiplexers, demultiplexers, full adders, half adders, encoders and decoders.

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    Original Title

    DAFSH (2)

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    © Attribution Non-Commercial (BY-NC)

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    The document describes various logic gates and components, including their truth tables. It covers basic gates like AND, OR, NAND, NOR, XOR and XNOR. It also covers multiplexers, demultiplexers, full adders, half adders, encoders and decoders.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    6 views2 pages

    DAFSH

    Uploaded by

    Yaniv Avrahami
    The document describes various logic gates and components, including their truth tables. It covers basic gates like AND, OR, NAND, NOR, XOR and XNOR. It also covers multiplexers, demultiplexers, full adders, half adders, encoders and decoders.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 2

    X

    0 0 1 1

    0 1 0 1

    1 1 1 0

    X NAND Y F=XY

    X AND Y F=XY

    0 0 1 1

    0 1 0 1

    0 0 0 1

    0 0 1 1

    0 1 0 1

    1 0 0 0

    X NOR Y F=X+Y

    X OR Y F=X+Y

    0 0 1 1

    0 1 0 1

    0 1 1 1

    0 0 1 1

    0 1 0 1

    0 1 1 0

    X XOR Y

    F NOT F=XY

    X F=X

    MULTIPLEXER X XOR Y F=XY MUX 22 1


    21 20

    0 0I 0 1I1 1I 2 I3

    0 1 0 1

    1 0 0 1

    S1 0 0 1 1

    S0

    0 1 0 1

    S1 S0 mi
    I0 I1 I2 I3

    F = m i I i
    i =0

    n 1

    DEMULTIPLEXER
    D0 DEMUX D 1 1 4 D2 D3
    S1 S0

    S1 0 0 1 1

    S0

    D0

    0 1 0 1

    I 0 0 0

    D1 0 I 0 0

    D2 0 0 I 0

    D3

    0 0 0 I

    DECODER DECODER

    ENCODER

    S1 S0

    ENCODER

    A 3 O1 O 0 A 0 A4 A5 A6
    A7 E N C O D E

    FULL ADDER X
    C out

    HALF ADDER Y .F. A C in C X Y .H. A S=XY S=XYCin HALF SUB. X B S .H . D=XY B=XY Y XYBD0000011 110011100 C=XY XYCS00000101 10011110

    X 0 0 0 0 1 1 1 1 X 0 0 0 0 1 1 1 1

    Y 0 0 1 1 0 0 1 1

    C in 0 1 0 0 0 1 0 1

    C out S

    0 0 0 1 0 1 1 1

    0 1 1 0 1 0 0 1

    C out = X Y + C in ( X + Y ) Y Bin Bout D 0 0 0 0 0 1 1 1 1 0 FULL 1 SUBTRACTOR 1 1 0 1 0 0 0 0 1 S X .F.Y 0 1 0 0 1 0 0 0 B Bout =XY+B (X+Y) out D=Xin YBB in in 1 1 1 1

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