You are on page 1of 1

module example (clk1,out1);

input clk1;
output out1;
nmos # (17) nmos(out1,vss,clk1); //0.36u 0.12u
pmos # (17) pmos(out1,vdd,clk1); //0.72u 0.12u
endmodule

You might also like