EEE596 ASIC DESIGN LAB

LAB REPORT
By

<Name>
(<Register Number>)

M.Tech. VLSI Design

Winter 2012 -13

SCHOOL OF ELECTRONICS ENGINEERING VIT UNIVERSITY VELLORE 632014, TAMILNADU, INDIA

May 2013

EEE596 ASIC DESIGN LAB

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Vellore 632014, Tamilnadu, India.

SCHOOL OF ELECTRONICS ENGINEERING

BONAFIDE CERTIFICATE

This is certified to be the bonafide record of work done by ________________ Reg.No. _____________ of First Year M.Tech VLSI Design for EEE 596 ASIC DESIGN LAB course of VIT University during Jan13 to May 13.

Faculty-In-Charge(s) (Prof.K.Sivasankaran ) (Prof.R.Sakthivel)

SUBMITTED FOR PRACTICAL EXAMINATION HELD ON

Internal Examiner

External Examiner

EEE596 ASIC DESIGN LAB

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<Project Title>

EEE596 ASIC DESIGN LAB

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Outline

1. 2. 3. 4.

Abstract Literature Survey Methodology Result and Discussion 4.1 Simulation 4.2 Synthesis 4.3 Physical Design 5. Conclusion 6. References 7. Annexure

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EEE596 ASIC DESIGN LAB

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EEE596 ASIC DESIGN LAB

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