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SIMULATION OF SEQUENTIAL CIRCUITS USING HARDWARE DESCRIPTION LANGUAGE (VHDL/ VERILOG HDL SOFTWARE REQUIRED)

AIM: To write a program for the simulation of the sequential circuit using Verilog HDL. APPARATUS REQUIRED: S.No 1. 2. Requirement Xilinx 10.1 ISE PC Quantity 1 1

PROCEDURE: 1) To start with double click on ISE icon. 2) Select files from tab and click on the new project. 3) Give the project name corresponding and choose the location. 4) Choose the kit specification. Property name Value Property category General purpose Family Sparton 3 Device XC 3S400 Package PQ 208 Speed 5 Top level source- type HDL Synthesis tool XSI (HDL Verilog) Simulator ISE Preferred language Verilog Enhanced design Simulator Message filtering Display message

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5) Click on new source and choose Verilog module and give the file name. 6) Choose the post specifications and check the summary. 7) The tool will generate the coding. 8) To synthesis your module, double click on the synthesis in the process window. 9) If module contains any errors if will be displayed. D FLIP FLOP PROGRAM: module DFlipFlop(d, clk, clr, q, qbar); input d; input clk; input clr; output q; output qbar; reg q; assign qbar=~q; always @(posedge clk) if(~clr)q=0; else q=d; endmodule OUTPUT

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T FLIP FLOP PROGRAM: module TFlipFlop(t, clk, q, qbar); input t; input clk; output q; output qbar; reg q; assign qbar=~q; always @ (posedge clk) q=~t; endmodule OUTPUT

SHIFT REGISTER SISO module SISO(d,clk,rst,q); input d,clk,rst; output q; wire w1,w2,w3; dff1 a1(d,clk,rst,w1); dff1 a2(w1,clk,rst,w2); dff1 a3(w2,clk,rst,w3); dff1 a4(w3,clk,rst,q); end module
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SIPO module SIPO(d,clk,rst,q); input d,clk,rst; output [3:0] q; wire w1,w2,w3; dff1 a1(d,clk,rst,w1); dff1 a2(w1,clk,rst,w2); dff1 a3(w2,clk,rst,w3); dff1 a4(w3,clk,rst,q(3)); assign q[0]=w1; assign q[1]=w2; assign q[2]=w3; end module PIPO module PIPO(d,clk,rst,q); input clk,rst; input [3:0]d; output [3:0]q; dff1 a1(d[0],clk,rst,q[0]); dff1 a2(d[1],clk,rst,q[1]); dff1 a3(d[2],clk,rst,q[2]); dff1 a4(d[3],clk,rst,q[3]); end module

RESULT:

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