Slides to Accompany a Video Tutorial on

Harry Porters Relay Computer

Harry Porter, Ph.D.
Portland State University November 7, 2007

+V

Double Throw Relay

Double Throw Relay

+V

Four Pole, Double Throw Relay

Four Pole, Double Throw Relay

+V

Schematic Diagrams

Assume other terminal is connected to ground

Schematic Diagrams

+V

Assume other terminal is connected to ground

The NOT Circuit

in out 0 +V in 1 out

in out 0 1 1 0

Convention: 1 = +12V 0 = not connected

The NOT Circuit

in out 1 +V in 0 out

in out 0 1 1 0

Convention: 1 = +12V 0 = not connected

The OR Circuit
b c
b 0 0 1 1 c 0 1 0 1

b or c
OUT 0 1 1 1

+V b

b or c +V

An Optimization?
b b c b or c c b or c

An Optimization?
b b c d c or d c c or d d b or c b or c

An Optimization?
b b c d c or d c c or d b or c b or c

Whoops!

An Optimization?
b c d c or d c d b or c b +V c or d b or c

1-Bit Logic Circuit

b 0 0 1 1 c 0 1 0 1 NOT AND OR XOR 1 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0

NOT AND OR

c XOR

1-Bit Logic Circuit

b 0 0 1 1 c 0 1 0 1 NOT AND OR XOR 1 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0

V b

NOT AND OR

c XOR

1-Bit Logic Circuit

b 0 0 1 1 c 0 1 0 1 NOT AND OR XOR 1 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0

V b

NOT AND OR

c XOR

1-Bit Logic Circuit

b 0 0 1 1 c 0 1 0 1 NOT AND OR XOR 1 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0

V b

NOT AND OR

c XOR

1-Bit Logic Circuit

b 0 0 1 1 c 0 1 0 1 NOT AND OR XOR 1 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0

V b

NOT AND OR

c XOR

1-Bit Logic Circuit

b 0 0 1 1 c 0 1 0 1 NOT AND OR XOR 1 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0

V b

NOT AND OR

c XOR

Eight 1-bit circuits can be combined to build an...

8-Bit Logic Circuit

B7 C7 B1 C1 B0 C0

Logic Circuit
XOR7 OR7 AND7 NOT7

Logic Circuit
XOR1 OR1 AND1 NOT1

Logic Circuit
XOR0 OR0 AND0 NOT0

The Full Adder Circuit

Cyin B 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Cyout 0 0 0 1 0 1 1 1

Sum 0 1 1 0 1 0 0 1

Carryout

Full Adder

Carryin

Sum

8 full-adders can be combined to build an...

8-Bit Adder
B7 C7 B1 C1 B0 C0 Carry Carry Carry

Full Adder

Full Adder

Full Adder

Sum7

Sum1

Sum0

B C

8 8 8

Sum
Carry

The Zero-Detect Circuit

V+

Zero

Result Bus

The Zero-Detect Circuit

V+

Zero

Result Bus
Sign

Enable Circuit

Enable

Enable Circuit

B XOR C
x7 x6 x5 x4 x3 x2 x1 x0

Enable

Result Bus

Shift Left Circular (SHL)

B
b7 b6 b5 b4 b3 b2 b1 b0

Enable

Result Bus

3-to-8 Decoder
f0 f1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 f2 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 OUTPUT 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1
ADD INC AND OR XOR NOT SHL <unused>

f0 f1 f2

B C

Arithmetic Logic Unit (ALU)

8 8

Function

8-bit Adder
ADD AND INC

8-bit Logic
XOR NOT OR SHL

3-to-8 Decoder
Enable En 8

En En En En En

Data Bus
Zero

Sign

Carry

Zero-Detect

An 8-Bit ALU
Function Code
000 001 010 011 100 101 110 111 add inc and or xor not shl <nop>
3

B C

8 8

ALU
8 Carry Sign Zero

Result

Register Storage

+V

Register Storage

+V A7 A6 A0

Register Storage

+V A7 Select A6 A0

Enable

Bus

Register Storage

Load Select

A7

A6

A0

Enable

Bus

Register Storage

Load Select

A7

A6

A0

Enable

Bus

8-Bit Registers

X Register Load Select

Y Register Load Select

8-Bit Data Bus

16-Bit Address Bus

Load Select X Register Load Select Y Register Load Select

8-Bit Data Bus

A B C D
M1 M2

ALU
M
Z Cy S

8-bit

8-bit Data Bus

16-bit Address Bus

X Y J1 J2

XY J
Inst

PC Inc
16-bit

System Architecture

Increment

Memory
Addr Data

32K Byte Static RAM Chip LEDs

8 FET Power Transistors (to drive relays during a memory-read operation)

A B C D
M1 M2

ALU
M XY J
Inst Z Cy S

8-bit

8-bit Data Bus

16-bit Address Bus

X Y J1 J2

Example:
The ALU Instruction

PC Inc
16-bit

Increment

Memory
Addr Data

A B C D
M1 M2

ALU
M XY J
Inst Z Cy S

8-bit

8-bit Data Bus

16-bit Address Bus

X Y J1 J2

Step 1: Fetch Instruction

MEM-READ

LOAD SELECT

PC Inc
16-bit

Increment

Memory
Addr Data

A B C D
M1 M2

ALU
M XY J
Inst Z Cy S

8-bit

8-bit Data Bus

16-bit Address Bus

X Y J1 J2

Step 2: Increment PC

PC Inc
16-bit

SELECT LOAD

Increment

Memory
Addr Data

A B C D
M1 M2

ALU
M XY J
Inst Z Cy S

8-bit

8-bit Data Bus

16-bit Address Bus

X Y J1 J2

Step 3: Update PC

PC Inc
16-bit

LOAD SELECT

Increment

Memory
Addr Data

LOAD

A B C D
M1 M2

ALU
M XY J
Inst Z Cy S

8-bit

8-bit Data Bus

J1 J2

16-bit Address Bus

X Y

FUNCTION

LOAD

PC Inc
16-bit

Step 4: Execute Instruction

Increment

Memory
Addr Data

Clock
+V Switch +V Output

Clock
+V Switch +V Charging Output

Clock
+V Switch +V Discharging Output

Clock
+V Switch +V Output

Clock
+V +V +V +V

Clock
On +V +V +V On +V

B
Discharging Charging

Clock
On +V +V +V +V On

B
Discharging

C
Charging

Clock
On +V +V +V +V On

B
Discharging

C
Charging

Clock
On +V +V +V +V On

A
Charging

C
Discharging

Clock
On +V +V On +V +V

A
Discharging Charging

Clock Timing Diagram

A B C D
Clock Clock = (A and B) or (C and D)

clock
1 t1

Finite State Machine

2 t2 3 t3 4 t4 5 t5 6 t6 7 t7 8 t8

Outputs

Output from FSA

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3

t1 t2 t3 t4 t5 t6 t7 t8

Instruction Timing - ALU Instruction

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 Select PC Memory Read Load Instr Load Inc Select Inc Load PC ALU Function Load A Load Cond.Code Reg.

Instruction Timing - ALU Instruction

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 Select PC Memory Read Load Instr Load Inc Select Inc Load PC ALU Function Load A Load Cond.Code Reg.

Fetch

Instruction Timing - ALU Instruction

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 Select PC Memory Read Load Instr Load Inc Select Inc Load PC ALU Function Load A Load Cond.Code Reg.

Increment

Instruction Timing - ALU Instruction

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 Select PC Memory Read Load Instr Load Inc Select Inc Load PC ALU Function Load A Load Cond.Code Reg.

Execute

Instruction Decoding
Finite State Machine
1 2 3 4 5 6

Instruction Register
7 6 5 4 3 2 1 0

Combinational Logic

Control Signals
(Load, Select, Mem-Read, etc.)

Instruction Timing - 16-bit Move

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 1 Select PC Memory Read Load Instr Load Inc Select Inc Load PC Select Source-Register Load Dest-Register

(Same as before)

Finite State Machine

1 2 3 4 5 6 7 8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Instruction Decoding and Control

Clock Finite State Machine Instruction Register Data Bus

Instruction Decoding Control Lines

The Instruction Set

Move
0 0 d d d s s s ddd sss

= destination register = source register (A, B, C, D, M1 ,M2 ,X or Y) destination register (A or D) = function code (add, inc, and, or, xor, not, shl) (A or B)

ALU
1 0 0 0 r f f f

r = fff

Load Immediate
0 1 r d d d d d

r = destination register ddddd = value (-16..15)

16-bit Increment
1 0 1 1 0 0 0 0

XY XY + 1

The Instruction Set

Load
1 0 0 1 0 0 r r rr

= destination register (A, B, C, D) reg [M]

Store
1 0 0 1 1 0 r r

rr

= source register (A, B, C, D) [M] reg

Load 16-bit Immediate

1 1 0 0 0 0 0 0 v v v v v v v v v v v v v v v v

Load the immediate value into M (i.e., M1 and M2)

Halt
1 0 1 0 1 1 1 0

The Instruction Set

Goto
1 1 1 0 0 1 1 0 a a a a a a a a a a a a a a a a

Branch to the given address

Call
1 1 1 0 0 1 1 1 a a a a a a a a a a a a a a a a

Branch to the given address Save return location in XY register

Return / Branch Indirect

1 0 1 0 1 0 1 0

PC XY
d = destination register (PC or XY) ss = source register (M, XY or J)

16-Bit Move
1 0 1 0 d s s 0

The Instruction Set

Branch If Negative
1 1 1 1 0 0 0 0 a a a a a a a a a a a a a a a a

Branch to the given address if S = 1

Branch If Carry
1 1 1 0 1 0 0 0 a a a a a a a a a a a a a a a a

Branch to the given address if Cy = 1

Branch If Zero
1 1 1 0 0 1 0 0 a a a a a a a a a a a a a a a a

Branch to the given address if Z = 1

Branch If Not Zero

1 1 1 0 0 0 1 0 a a a a a a a a a a a a a a a a

Branch to the given address if Z = 0

An Example Program
0000 0000 0000 0000 0000 0000 0000

address
0000 0001 0010 0011 0100 0101 0110

0011 0011 1000 1111 0000 0000 0011

instr

1001 0110 0101 0000 0000 0111 0010

0000 0111 0000 1000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100

0101 1001 0001 1000 0000 1000 0011 0000 1000 0011 0000 1000 1111 0000 0001 0000 1000 0011 0000 1000 1110 0000 0000 1010 1110 0110 0000 1111 0110 1000 1111 0101 0000 0000 0111 1110 0000 0000 1011 1001 0010 0000 1001 1110

Y=B Y B X=0 X 0 A=B If sign(Y)==1 BNEG Else . . . . . X=C X C Else: . A=-7 D -7 D=A . Loop: Loop: B=X Shift X left (circular) A=B<<1 . X=A . B=Y Shift Y left (circular) A=B<<1 . Y=A . B=Y If sign(Y)==1 A=B . BNEG Else2 . . . . . B=X X X + C A=B+C . X=A . Else2: . B=D D D + 1 D=B+1 . BNZ Loop If D != 0 goto Loop . . . . HALT HALT

assembly

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